1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2015 Xilinx, Inc. 4 * 5 * Zynq USB HOST xHCI Controller 6 * 7 * Author: Siva Durga Prasad Paladugu<sivadur@xilinx.com> 8 * 9 * This file was reused from Freescale USB xHCI 10 */ 11 12 #include <common.h> 13 #include <usb.h> 14 #include <linux/errno.h> 15 #include <asm/arch-zynqmp/hardware.h> 16 #include <linux/compat.h> 17 #include <linux/usb/dwc3.h> 18 #include "xhci.h" 19 20 /* Declare global data pointer */ 21 /* Default to the ZYNQMP XHCI defines */ 22 #define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 23 #define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC 24 #define USB3_PHY_PARTIAL_RX_POWERON BIT(6) 25 #define USB3_PHY_RX_POWERON BIT(14) 26 #define USB3_PHY_TX_POWERON BIT(15) 27 #define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) 28 #define USB3_PWRCTL_CLK_CMD_SHIFT 14 29 #define USB3_PWRCTL_CLK_FREQ_SHIFT 22 30 31 /* USBOTGSS_WRAPPER definitions */ 32 #define USBOTGSS_WRAPRESET BIT(17) 33 #define USBOTGSS_DMADISABLE BIT(16) 34 #define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4) 35 #define USBOTGSS_STANDBYMODE_SMRT BIT(5) 36 #define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) 37 #define USBOTGSS_IDLEMODE_NOIDLE BIT(2) 38 #define USBOTGSS_IDLEMODE_SMRT BIT(3) 39 #define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) 40 41 /* USBOTGSS_IRQENABLE_SET_0 bit */ 42 #define USBOTGSS_COREIRQ_EN BIT(1) 43 44 /* USBOTGSS_IRQENABLE_SET_1 bits */ 45 #define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1) 46 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3) 47 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4) 48 #define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5) 49 #define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8) 50 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11) 51 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12) 52 #define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13) 53 #define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16) 54 #define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17) 55 56 struct zynqmp_xhci { 57 struct xhci_hccr *hcd; 58 struct dwc3 *dwc3_reg; 59 }; 60 61 static struct zynqmp_xhci zynqmp_xhci; 62 63 unsigned long ctr_addr[] = CONFIG_ZYNQMP_XHCI_LIST; 64 65 static int zynqmp_xhci_core_init(struct zynqmp_xhci *zynqmp_xhci) 66 { 67 int ret = 0; 68 69 ret = dwc3_core_init(zynqmp_xhci->dwc3_reg); 70 if (ret) { 71 debug("%s:failed to initialize core\n", __func__); 72 return ret; 73 } 74 75 /* We are hard-coding DWC3 core to Host Mode */ 76 dwc3_set_mode(zynqmp_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); 77 78 return ret; 79 } 80 81 int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) 82 { 83 struct zynqmp_xhci *ctx = &zynqmp_xhci; 84 int ret = 0; 85 uint32_t hclen; 86 87 if (index < 0 || index >= ARRAY_SIZE(ctr_addr)) 88 return -EINVAL; 89 90 ctx->hcd = (struct xhci_hccr *)ctr_addr[index]; 91 ctx->dwc3_reg = (struct dwc3 *)((void *)ctx->hcd + DWC3_REG_OFFSET); 92 93 ret = board_usb_init(index, USB_INIT_HOST); 94 if (ret != 0) { 95 puts("Failed to initialize board for USB\n"); 96 return ret; 97 } 98 99 ret = zynqmp_xhci_core_init(ctx); 100 if (ret < 0) { 101 puts("Failed to initialize xhci\n"); 102 return ret; 103 } 104 105 *hccr = (struct xhci_hccr *)ctx->hcd; 106 hclen = HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)); 107 *hcor = (struct xhci_hcor *)((uintptr_t) *hccr + hclen); 108 109 debug("zynqmp-xhci: init hccr %p and hcor %p hc_length %d\n", 110 *hccr, *hcor, hclen); 111 112 return ret; 113 } 114 115 void xhci_hcd_stop(int index) 116 { 117 /* 118 * Currently zynqmp socs do not support PHY shutdown from 119 * sw. But this support may be added in future socs. 120 */ 121 122 return; 123 } 124