1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2015 Xilinx, Inc. 4 * 5 * Zynq USB HOST xHCI Controller 6 * 7 * Author: Siva Durga Prasad Paladugu<sivadur@xilinx.com> 8 * 9 * This file was reused from Freescale USB xHCI 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <usb.h> 15 #include <linux/errno.h> 16 #include <asm/arch-zynqmp/hardware.h> 17 #include <linux/compat.h> 18 #include <linux/usb/dwc3.h> 19 #include "xhci.h" 20 21 /* Declare global data pointer */ 22 /* Default to the ZYNQMP XHCI defines */ 23 #define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 24 #define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC 25 #define USB3_PHY_PARTIAL_RX_POWERON BIT(6) 26 #define USB3_PHY_RX_POWERON BIT(14) 27 #define USB3_PHY_TX_POWERON BIT(15) 28 #define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) 29 #define USB3_PWRCTL_CLK_CMD_SHIFT 14 30 #define USB3_PWRCTL_CLK_FREQ_SHIFT 22 31 32 /* USBOTGSS_WRAPPER definitions */ 33 #define USBOTGSS_WRAPRESET BIT(17) 34 #define USBOTGSS_DMADISABLE BIT(16) 35 #define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4) 36 #define USBOTGSS_STANDBYMODE_SMRT BIT(5) 37 #define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) 38 #define USBOTGSS_IDLEMODE_NOIDLE BIT(2) 39 #define USBOTGSS_IDLEMODE_SMRT BIT(3) 40 #define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) 41 42 /* USBOTGSS_IRQENABLE_SET_0 bit */ 43 #define USBOTGSS_COREIRQ_EN BIT(1) 44 45 /* USBOTGSS_IRQENABLE_SET_1 bits */ 46 #define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1) 47 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3) 48 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4) 49 #define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5) 50 #define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8) 51 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11) 52 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12) 53 #define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13) 54 #define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16) 55 #define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17) 56 57 struct zynqmp_xhci { 58 struct usb_platdata usb_plat; 59 struct xhci_ctrl ctrl; 60 struct xhci_hccr *hcd; 61 struct dwc3 *dwc3_reg; 62 }; 63 64 struct zynqmp_xhci_platdata { 65 fdt_addr_t hcd_base; 66 }; 67 68 static int zynqmp_xhci_core_init(struct zynqmp_xhci *zynqmp_xhci) 69 { 70 int ret = 0; 71 72 ret = dwc3_core_init(zynqmp_xhci->dwc3_reg); 73 if (ret) { 74 debug("%s:failed to initialize core\n", __func__); 75 return ret; 76 } 77 78 /* We are hard-coding DWC3 core to Host Mode */ 79 dwc3_set_mode(zynqmp_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); 80 81 return ret; 82 } 83 84 void xhci_hcd_stop(int index) 85 { 86 /* 87 * Currently zynqmp socs do not support PHY shutdown from 88 * sw. But this support may be added in future socs. 89 */ 90 91 return; 92 } 93 94 static int xhci_usb_probe(struct udevice *dev) 95 { 96 struct zynqmp_xhci_platdata *plat = dev_get_platdata(dev); 97 struct zynqmp_xhci *ctx = dev_get_priv(dev); 98 struct xhci_hcor *hcor; 99 int ret; 100 101 ctx->hcd = (struct xhci_hccr *)plat->hcd_base; 102 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); 103 104 ret = zynqmp_xhci_core_init(ctx); 105 if (ret) { 106 puts("XHCI: failed to initialize controller\n"); 107 return -EINVAL; 108 } 109 110 hcor = (struct xhci_hcor *)((ulong)ctx->hcd + 111 HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase))); 112 113 return xhci_register(dev, ctx->hcd, hcor); 114 } 115 116 static int xhci_usb_remove(struct udevice *dev) 117 { 118 return xhci_deregister(dev); 119 } 120 121 static int xhci_usb_ofdata_to_platdata(struct udevice *dev) 122 { 123 struct zynqmp_xhci_platdata *plat = dev_get_platdata(dev); 124 const void *blob = gd->fdt_blob; 125 126 /* Get the base address for XHCI controller from the device node */ 127 plat->hcd_base = fdtdec_get_addr(blob, dev_of_offset(dev), "reg"); 128 if (plat->hcd_base == FDT_ADDR_T_NONE) { 129 debug("Can't get the XHCI register base address\n"); 130 return -ENXIO; 131 } 132 133 return 0; 134 } 135 136 U_BOOT_DRIVER(dwc3_generic_host) = { 137 .name = "dwc3-generic-host", 138 .id = UCLASS_USB, 139 .ofdata_to_platdata = xhci_usb_ofdata_to_platdata, 140 .probe = xhci_usb_probe, 141 .remove = xhci_usb_remove, 142 .ops = &xhci_usb_ops, 143 .platdata_auto_alloc_size = sizeof(struct zynqmp_xhci_platdata), 144 .priv_auto_alloc_size = sizeof(struct zynqmp_xhci), 145 .flags = DM_FLAG_ALLOC_PRIV_DMA, 146 }; 147