1 /* 2 * Copyright 2015 Xilinx, Inc. 3 * 4 * Zynq USB HOST xHCI Controller 5 * 6 * Author: Siva Durga Prasad Paladugu<sivadur@xilinx.com> 7 * 8 * This file was reused from Freescale USB xHCI 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <usb.h> 15 #include <asm-generic/errno.h> 16 #include <asm/arch-zynqmp/hardware.h> 17 #include <linux/compat.h> 18 #include <linux/usb/dwc3.h> 19 #include "xhci.h" 20 21 /* Declare global data pointer */ 22 DECLARE_GLOBAL_DATA_PTR; 23 24 /* Default to the ZYNQMP XHCI defines */ 25 #define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 26 #define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC 27 #define USB3_PHY_PARTIAL_RX_POWERON BIT(6) 28 #define USB3_PHY_RX_POWERON BIT(14) 29 #define USB3_PHY_TX_POWERON BIT(15) 30 #define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) 31 #define USB3_PWRCTL_CLK_CMD_SHIFT 14 32 #define USB3_PWRCTL_CLK_FREQ_SHIFT 22 33 34 /* USBOTGSS_WRAPPER definitions */ 35 #define USBOTGSS_WRAPRESET BIT(17) 36 #define USBOTGSS_DMADISABLE BIT(16) 37 #define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4) 38 #define USBOTGSS_STANDBYMODE_SMRT BIT(5) 39 #define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) 40 #define USBOTGSS_IDLEMODE_NOIDLE BIT(2) 41 #define USBOTGSS_IDLEMODE_SMRT BIT(3) 42 #define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) 43 44 /* USBOTGSS_IRQENABLE_SET_0 bit */ 45 #define USBOTGSS_COREIRQ_EN BIT(1) 46 47 /* USBOTGSS_IRQENABLE_SET_1 bits */ 48 #define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1) 49 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3) 50 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4) 51 #define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5) 52 #define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8) 53 #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11) 54 #define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12) 55 #define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13) 56 #define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16) 57 #define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17) 58 59 struct zynqmp_xhci { 60 struct xhci_hccr *hcd; 61 struct dwc3 *dwc3_reg; 62 }; 63 64 static struct zynqmp_xhci zynqmp_xhci; 65 66 unsigned long ctr_addr[] = CONFIG_ZYNQMP_XHCI_LIST; 67 68 static int zynqmp_xhci_core_init(struct zynqmp_xhci *zynqmp_xhci) 69 { 70 int ret = 0; 71 72 ret = dwc3_core_init(zynqmp_xhci->dwc3_reg); 73 if (ret) { 74 debug("%s:failed to initialize core\n", __func__); 75 return ret; 76 } 77 78 /* We are hard-coding DWC3 core to Host Mode */ 79 dwc3_set_mode(zynqmp_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); 80 81 return ret; 82 } 83 84 int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) 85 { 86 struct zynqmp_xhci *ctx = &zynqmp_xhci; 87 int ret = 0; 88 uint32_t hclen; 89 90 if (index < 0 || index >= ARRAY_SIZE(ctr_addr)) 91 return -EINVAL; 92 93 ctx->hcd = (struct xhci_hccr *)ctr_addr[index]; 94 ctx->dwc3_reg = (struct dwc3 *)((void *)ctx->hcd + DWC3_REG_OFFSET); 95 96 ret = board_usb_init(index, USB_INIT_HOST); 97 if (ret != 0) { 98 puts("Failed to initialize board for USB\n"); 99 return ret; 100 } 101 102 ret = zynqmp_xhci_core_init(ctx); 103 if (ret < 0) { 104 puts("Failed to initialize xhci\n"); 105 return ret; 106 } 107 108 *hccr = (struct xhci_hccr *)ctx->hcd; 109 hclen = HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)); 110 *hcor = (struct xhci_hcor *)((uintptr_t) *hccr + hclen); 111 112 debug("zynqmp-xhci: init hccr %p and hcor %p hc_length %d\n", 113 *hccr, *hcor, hclen); 114 115 return ret; 116 } 117 118 void xhci_hcd_stop(int index) 119 { 120 /* 121 * Currently zynqmp socs do not support PHY shutdown from 122 * sw. But this support may be added in future socs. 123 */ 124 125 return; 126 } 127