1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2016 Rockchip, Inc. 4 * Authors: Daniel Meng <daniel.meng@rock-chips.com> 5 */ 6 #include <common.h> 7 #include <dm.h> 8 #include <malloc.h> 9 #include <usb.h> 10 #include <watchdog.h> 11 #include <linux/errno.h> 12 #include <linux/compat.h> 13 #include <linux/usb/dwc3.h> 14 #include <power/regulator.h> 15 16 #include "xhci.h" 17 18 struct rockchip_xhci_platdata { 19 fdt_addr_t hcd_base; 20 fdt_addr_t phy_base; 21 struct udevice *vbus_supply; 22 }; 23 24 /* 25 * Contains pointers to register base addresses 26 * for the usb controller. 27 */ 28 struct rockchip_xhci { 29 struct usb_platdata usb_plat; 30 struct xhci_ctrl ctrl; 31 struct xhci_hccr *hcd; 32 struct dwc3 *dwc3_reg; 33 }; 34 35 static int xhci_usb_ofdata_to_platdata(struct udevice *dev) 36 { 37 struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); 38 struct udevice *child; 39 int ret = 0; 40 41 /* 42 * Get the base address for XHCI controller from the device node 43 */ 44 plat->hcd_base = dev_read_addr(dev); 45 if (plat->hcd_base == FDT_ADDR_T_NONE) { 46 pr_err("Can't get the XHCI register base address\n"); 47 return -ENXIO; 48 } 49 50 /* Get the base address for usbphy from the device node */ 51 for (device_find_first_child(dev, &child); child; 52 device_find_next_child(&child)) { 53 if (!device_is_compatible(child, "rockchip,rk3399-usb3-phy")) 54 continue; 55 plat->phy_base = devfdt_get_addr(child); 56 break; 57 } 58 59 if (plat->phy_base == FDT_ADDR_T_NONE) { 60 pr_err("Can't get the usbphy register address\n"); 61 return -ENXIO; 62 } 63 64 /* Vbus regulator */ 65 ret = device_get_supply_regulator(dev, "vbus-supply", 66 &plat->vbus_supply); 67 if (ret) 68 debug("Can't get VBus regulator!\n"); 69 70 return 0; 71 } 72 73 /* 74 * rockchip_dwc3_phy_setup() - Configure USB PHY Interface of DWC3 Core 75 * @dwc: Pointer to our controller context structure 76 * @dev: Pointer to ulcass device 77 */ 78 static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg, 79 struct udevice *dev) 80 { 81 u32 reg; 82 u32 utmi_bits; 83 84 /* Set dwc3 usb2 phy config */ 85 reg = readl(&dwc3_reg->g_usb2phycfg[0]); 86 87 if (dev_read_bool(dev, "snps,dis-enblslpm-quirk")) 88 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 89 90 utmi_bits = dev_read_u32_default(dev, "snps,phyif-utmi-bits", -1); 91 if (utmi_bits == 16) { 92 reg |= DWC3_GUSB2PHYCFG_PHYIF; 93 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; 94 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT; 95 } else if (utmi_bits == 8) { 96 reg &= ~DWC3_GUSB2PHYCFG_PHYIF; 97 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; 98 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT; 99 } 100 101 if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk")) 102 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 103 104 if (dev_read_bool(dev, "snps,dis-u2-susphy-quirk")) 105 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 106 107 writel(reg, &dwc3_reg->g_usb2phycfg[0]); 108 } 109 110 static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci, 111 struct udevice *dev) 112 { 113 int ret; 114 115 ret = dwc3_core_init(rkxhci->dwc3_reg); 116 if (ret) { 117 pr_err("failed to initialize core\n"); 118 return ret; 119 } 120 121 rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev); 122 123 /* We are hard-coding DWC3 core to Host Mode */ 124 dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); 125 126 return 0; 127 } 128 129 static int rockchip_xhci_core_exit(struct rockchip_xhci *rkxhci) 130 { 131 return 0; 132 } 133 134 static int xhci_usb_probe(struct udevice *dev) 135 { 136 struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); 137 struct rockchip_xhci *ctx = dev_get_priv(dev); 138 struct xhci_hcor *hcor; 139 int ret; 140 141 ctx->hcd = (struct xhci_hccr *)plat->hcd_base; 142 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); 143 hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd + 144 HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase))); 145 146 if (plat->vbus_supply) { 147 ret = regulator_set_enable(plat->vbus_supply, true); 148 if (ret) { 149 pr_err("XHCI: failed to set VBus supply\n"); 150 return ret; 151 } 152 } 153 154 ret = rockchip_xhci_core_init(ctx, dev); 155 if (ret) { 156 pr_err("XHCI: failed to initialize controller\n"); 157 return ret; 158 } 159 160 return xhci_register(dev, ctx->hcd, hcor); 161 } 162 163 static int xhci_usb_remove(struct udevice *dev) 164 { 165 struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); 166 struct rockchip_xhci *ctx = dev_get_priv(dev); 167 int ret; 168 169 ret = xhci_deregister(dev); 170 if (ret) 171 return ret; 172 ret = rockchip_xhci_core_exit(ctx); 173 if (ret) 174 return ret; 175 176 if (plat->vbus_supply) { 177 ret = regulator_set_enable(plat->vbus_supply, false); 178 if (ret) 179 pr_err("XHCI: failed to set VBus supply\n"); 180 } 181 182 return ret; 183 } 184 185 static const struct udevice_id xhci_usb_ids[] = { 186 { .compatible = "rockchip,rk3399-xhci" }, 187 { .compatible = "rockchip,rk3328-xhci" }, 188 { } 189 }; 190 191 U_BOOT_DRIVER(usb_xhci) = { 192 .name = "xhci_rockchip", 193 .id = UCLASS_USB, 194 .of_match = xhci_usb_ids, 195 .ofdata_to_platdata = xhci_usb_ofdata_to_platdata, 196 .probe = xhci_usb_probe, 197 .remove = xhci_usb_remove, 198 .ops = &xhci_usb_ops, 199 .bind = dm_scan_fdt_dev, 200 .platdata_auto_alloc_size = sizeof(struct rockchip_xhci_platdata), 201 .priv_auto_alloc_size = sizeof(struct rockchip_xhci), 202 .flags = DM_FLAG_ALLOC_PRIV_DMA, 203 }; 204 205 static const struct udevice_id usb_phy_ids[] = { 206 { .compatible = "rockchip,rk3399-usb3-phy" }, 207 { .compatible = "rockchip,rk3328-usb3-phy" }, 208 { } 209 }; 210 211 U_BOOT_DRIVER(usb_phy) = { 212 .name = "usb_phy_rockchip", 213 .of_match = usb_phy_ids, 214 }; 215