1 /* 2 * Copyright (c) 2016 Rockchip, Inc. 3 * Authors: Daniel Meng <daniel.meng@rock-chips.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 #include <common.h> 8 #include <dm.h> 9 #include <fdtdec.h> 10 #include <libfdt.h> 11 #include <malloc.h> 12 #include <usb.h> 13 #include <watchdog.h> 14 #include <linux/errno.h> 15 #include <linux/compat.h> 16 #include <linux/usb/dwc3.h> 17 #include <power/regulator.h> 18 19 #include "xhci.h" 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 struct rockchip_xhci_platdata { 24 fdt_addr_t hcd_base; 25 fdt_addr_t phy_base; 26 struct udevice *vbus_supply; 27 }; 28 29 /* 30 * Contains pointers to register base addresses 31 * for the usb controller. 32 */ 33 struct rockchip_xhci { 34 struct usb_platdata usb_plat; 35 struct xhci_ctrl ctrl; 36 struct xhci_hccr *hcd; 37 struct dwc3 *dwc3_reg; 38 }; 39 40 static int xhci_usb_ofdata_to_platdata(struct udevice *dev) 41 { 42 struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); 43 struct udevice *child; 44 int ret = 0; 45 46 /* 47 * Get the base address for XHCI controller from the device node 48 */ 49 plat->hcd_base = devfdt_get_addr(dev); 50 if (plat->hcd_base == FDT_ADDR_T_NONE) { 51 error("Can't get the XHCI register base address\n"); 52 return -ENXIO; 53 } 54 55 /* Get the base address for usbphy from the device node */ 56 for (device_find_first_child(dev, &child); child; 57 device_find_next_child(&child)) { 58 if (!device_is_compatible(child, "rockchip,rk3399-usb3-phy")) 59 continue; 60 plat->phy_base = devfdt_get_addr(child); 61 break; 62 } 63 64 if (plat->phy_base == FDT_ADDR_T_NONE) { 65 error("Can't get the usbphy register address\n"); 66 return -ENXIO; 67 } 68 69 /* Vbus regulator */ 70 ret = device_get_supply_regulator(dev, "vbus-supply", 71 &plat->vbus_supply); 72 if (ret) 73 debug("Can't get VBus regulator!\n"); 74 75 return 0; 76 } 77 78 /* 79 * rockchip_dwc3_phy_setup() - Configure USB PHY Interface of DWC3 Core 80 * @dwc: Pointer to our controller context structure 81 * @dev: Pointer to ulcass device 82 */ 83 static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg, 84 struct udevice *dev) 85 { 86 u32 reg; 87 u32 utmi_bits; 88 89 /* Set dwc3 usb2 phy config */ 90 reg = readl(&dwc3_reg->g_usb2phycfg[0]); 91 92 if (dev_read_bool(dev, "snps,dis-enblslpm-quirk")) 93 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 94 95 utmi_bits = dev_read_u32_default(dev, "snps,phyif-utmi-bits", -1); 96 if (utmi_bits == 16) { 97 reg |= DWC3_GUSB2PHYCFG_PHYIF; 98 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; 99 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT; 100 } else if (utmi_bits == 8) { 101 reg &= ~DWC3_GUSB2PHYCFG_PHYIF; 102 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; 103 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT; 104 } 105 106 if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk")) 107 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 108 109 if (dev_read_bool(dev, "snps,dis-u2-susphy-quirk")) 110 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 111 112 writel(reg, &dwc3_reg->g_usb2phycfg[0]); 113 } 114 115 static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci, 116 struct udevice *dev) 117 { 118 int ret; 119 120 ret = dwc3_core_init(rkxhci->dwc3_reg); 121 if (ret) { 122 error("failed to initialize core\n"); 123 return ret; 124 } 125 126 rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev); 127 128 /* We are hard-coding DWC3 core to Host Mode */ 129 dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); 130 131 return 0; 132 } 133 134 static int rockchip_xhci_core_exit(struct rockchip_xhci *rkxhci) 135 { 136 return 0; 137 } 138 139 static int xhci_usb_probe(struct udevice *dev) 140 { 141 struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); 142 struct rockchip_xhci *ctx = dev_get_priv(dev); 143 struct xhci_hcor *hcor; 144 int ret; 145 146 ctx->hcd = (struct xhci_hccr *)plat->hcd_base; 147 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); 148 hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd + 149 HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase))); 150 151 if (plat->vbus_supply) { 152 ret = regulator_set_enable(plat->vbus_supply, true); 153 if (ret) { 154 error("XHCI: failed to set VBus supply\n"); 155 return ret; 156 } 157 } 158 159 ret = rockchip_xhci_core_init(ctx, dev); 160 if (ret) { 161 error("XHCI: failed to initialize controller\n"); 162 return ret; 163 } 164 165 return xhci_register(dev, ctx->hcd, hcor); 166 } 167 168 static int xhci_usb_remove(struct udevice *dev) 169 { 170 struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); 171 struct rockchip_xhci *ctx = dev_get_priv(dev); 172 int ret; 173 174 ret = xhci_deregister(dev); 175 if (ret) 176 return ret; 177 ret = rockchip_xhci_core_exit(ctx); 178 if (ret) 179 return ret; 180 181 if (plat->vbus_supply) { 182 ret = regulator_set_enable(plat->vbus_supply, false); 183 if (ret) 184 error("XHCI: failed to set VBus supply\n"); 185 } 186 187 return ret; 188 } 189 190 static const struct udevice_id xhci_usb_ids[] = { 191 { .compatible = "rockchip,rk3399-xhci" }, 192 { .compatible = "rockchip,rk3328-xhci" }, 193 { } 194 }; 195 196 U_BOOT_DRIVER(usb_xhci) = { 197 .name = "xhci_rockchip", 198 .id = UCLASS_USB, 199 .of_match = xhci_usb_ids, 200 .ofdata_to_platdata = xhci_usb_ofdata_to_platdata, 201 .probe = xhci_usb_probe, 202 .remove = xhci_usb_remove, 203 .ops = &xhci_usb_ops, 204 .bind = dm_scan_fdt_dev, 205 .platdata_auto_alloc_size = sizeof(struct rockchip_xhci_platdata), 206 .priv_auto_alloc_size = sizeof(struct rockchip_xhci), 207 .flags = DM_FLAG_ALLOC_PRIV_DMA, 208 }; 209 210 static const struct udevice_id usb_phy_ids[] = { 211 { .compatible = "rockchip,rk3399-usb3-phy" }, 212 { .compatible = "rockchip,rk3328-usb3-phy" }, 213 { } 214 }; 215 216 U_BOOT_DRIVER(usb_phy) = { 217 .name = "usb_phy_rockchip", 218 .of_match = usb_phy_ids, 219 }; 220