1 /* 2 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> 3 * 4 * Renesas RCar USB HOST xHCI Controller 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <clk.h> 11 #include <dm.h> 12 #include <fdtdec.h> 13 #include <usb.h> 14 #include <wait_bit.h> 15 16 #include "xhci.h" 17 #include "xhci-rcar-r8a779x_usb3_v3.h" 18 19 /* Register Offset */ 20 #define RCAR_USB3_DL_CTRL 0x250 /* FW Download Control & Status */ 21 #define RCAR_USB3_FW_DATA0 0x258 /* FW Data0 */ 22 23 /* Register Settings */ 24 /* FW Download Control & Status */ 25 #define RCAR_USB3_DL_CTRL_ENABLE BIT(0) 26 #define RCAR_USB3_DL_CTRL_FW_SUCCESS BIT(4) 27 #define RCAR_USB3_DL_CTRL_FW_SET_DATA0 BIT(8) 28 29 struct rcar_xhci_platdata { 30 fdt_addr_t hcd_base; 31 struct clk clk; 32 }; 33 34 /** 35 * Contains pointers to register base addresses 36 * for the usb controller. 37 */ 38 struct rcar_xhci { 39 struct xhci_ctrl ctrl; /* Needs to come first in this struct! */ 40 struct usb_platdata usb_plat; 41 struct xhci_hccr *hcd; 42 }; 43 44 static int xhci_rcar_download_fw(struct rcar_xhci *ctx, const u32 *fw_data, 45 const size_t fw_array_size) 46 { 47 void __iomem *regs = (void __iomem *)ctx->hcd; 48 int i, ret; 49 50 /* Download R-Car USB3.0 firmware */ 51 setbits_le32(regs + RCAR_USB3_DL_CTRL, RCAR_USB3_DL_CTRL_ENABLE); 52 53 for (i = 0; i < fw_array_size; i++) { 54 writel(fw_data[i], regs + RCAR_USB3_FW_DATA0); 55 setbits_le32(regs + RCAR_USB3_DL_CTRL, 56 RCAR_USB3_DL_CTRL_FW_SET_DATA0); 57 58 ret = wait_for_bit("xhci-rcar", regs + RCAR_USB3_DL_CTRL, 59 RCAR_USB3_DL_CTRL_FW_SET_DATA0, false, 60 10, false); 61 if (ret) 62 break; 63 } 64 65 clrbits_le32(regs + RCAR_USB3_DL_CTRL, RCAR_USB3_DL_CTRL_ENABLE); 66 67 ret = wait_for_bit("xhci-rcar", regs + RCAR_USB3_DL_CTRL, 68 RCAR_USB3_DL_CTRL_FW_SUCCESS, true, 69 10, false); 70 71 return ret; 72 } 73 74 static int xhci_rcar_probe(struct udevice *dev) 75 { 76 struct rcar_xhci_platdata *plat = dev_get_platdata(dev); 77 struct rcar_xhci *ctx = dev_get_priv(dev); 78 struct xhci_hcor *hcor; 79 int len, ret; 80 81 ret = clk_get_by_index(dev, 0, &plat->clk); 82 if (ret < 0) { 83 dev_err(dev, "Failed to get USB3 clock\n"); 84 return ret; 85 } 86 87 ret = clk_enable(&plat->clk); 88 if (ret) { 89 dev_err(dev, "Failed to enable USB3 clock\n"); 90 goto err_clk; 91 } 92 93 ctx->hcd = (struct xhci_hccr *)plat->hcd_base; 94 len = HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)); 95 hcor = (struct xhci_hcor *)((uintptr_t)ctx->hcd + len); 96 97 ret = xhci_rcar_download_fw(ctx, firmware_r8a779x_usb3_v3, 98 ARRAY_SIZE(firmware_r8a779x_usb3_v3)); 99 if (ret) { 100 dev_err(dev, "Failed to download firmware\n"); 101 goto err_fw; 102 } 103 104 ret = xhci_register(dev, ctx->hcd, hcor); 105 if (ret) { 106 dev_err(dev, "Failed to register xHCI\n"); 107 goto err_fw; 108 } 109 110 return 0; 111 112 err_fw: 113 clk_disable(&plat->clk); 114 err_clk: 115 clk_free(&plat->clk); 116 return ret; 117 } 118 119 static int xhci_rcar_deregister(struct udevice *dev) 120 { 121 struct rcar_xhci_platdata *plat = dev_get_platdata(dev); 122 123 clk_disable(&plat->clk); 124 clk_free(&plat->clk); 125 126 return xhci_deregister(dev); 127 } 128 129 static int xhci_rcar_ofdata_to_platdata(struct udevice *dev) 130 { 131 struct rcar_xhci_platdata *plat = dev_get_platdata(dev); 132 133 plat->hcd_base = devfdt_get_addr(dev); 134 if (plat->hcd_base == FDT_ADDR_T_NONE) { 135 debug("Can't get the XHCI register base address\n"); 136 return -ENXIO; 137 } 138 139 return 0; 140 } 141 142 static const struct udevice_id xhci_rcar_ids[] = { 143 { .compatible = "renesas,xhci-r8a7795" }, 144 { .compatible = "renesas,xhci-r8a7796" }, 145 { } 146 }; 147 148 U_BOOT_DRIVER(usb_xhci) = { 149 .name = "xhci_rcar", 150 .id = UCLASS_USB, 151 .probe = xhci_rcar_probe, 152 .remove = xhci_rcar_deregister, 153 .ops = &xhci_usb_ops, 154 .of_match = xhci_rcar_ids, 155 .ofdata_to_platdata = xhci_rcar_ofdata_to_platdata, 156 .platdata_auto_alloc_size = sizeof(struct rcar_xhci_platdata), 157 .priv_auto_alloc_size = sizeof(struct rcar_xhci), 158 .flags = DM_FLAG_ALLOC_PRIV_DMA, 159 }; 160