xref: /openbmc/u-boot/drivers/usb/host/xhci-omap.c (revision d6eae7b0) 
1 /*
2  * OMAP USB HOST xHCI Controller
3  *
4  * (C) Copyright 2013
5  * Texas Instruments, <www.ti.com>
6  *
7  * Author: Dan Murphy <dmurphy@ti.com>
8  *
9  * SPDX-License-Identifier:	GPL-2.0+
10  */
11 
12 #include <common.h>
13 #include <usb.h>
14 #include <asm-generic/errno.h>
15 #include <asm/omap_common.h>
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/xhci-omap.h>
19 
20 #include <linux/compat.h>
21 #include <linux/usb/dwc3.h>
22 
23 #include "xhci.h"
24 
25 /* Declare global data pointer */
26 DECLARE_GLOBAL_DATA_PTR;
27 
28 static struct omap_xhci omap;
29 
30 struct usb_dpll_params {
31 	u16	m;
32 	u8	n;
33 	u8	freq:3;
34 	u8	sd;
35 	u32	mf;
36 };
37 
38 #define	NUM_USB_CLKS		6
39 
40 static struct usb_dpll_params omap_usb3_dpll_params[NUM_USB_CLKS] = {
41 	{1250, 5, 4, 20, 0},		/* 12 MHz */
42 	{3125, 20, 4, 20, 0},		/* 16.8 MHz */
43 	{1172, 8, 4, 20, 65537},	/* 19.2 MHz */
44 	{1250, 12, 4, 20, 0},		/* 26 MHz */
45 	{3125, 47, 4, 20, 92843},	/* 38.4 MHz */
46 	{1000, 7, 4, 10, 0},        /* 20 MHz */
47 };
48 
49 static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs)
50 {
51 	u32 val;
52 
53 	writel(SET_PLL_GO, &phy_regs->pll_go);
54 	do {
55 		val = readl(&phy_regs->pll_status);
56 			if (val & PLL_LOCK)
57 				break;
58 	} while (1);
59 }
60 
61 static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs)
62 {
63 	u32 clk_index = get_sys_clk_index();
64 	u32 val;
65 
66 	val = readl(&phy_regs->pll_config_1);
67 	val &= ~PLL_REGN_MASK;
68 	val |= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT;
69 	writel(val, &phy_regs->pll_config_1);
70 
71 	val = readl(&phy_regs->pll_config_2);
72 	val &= ~PLL_SELFREQDCO_MASK;
73 	val |= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT;
74 	writel(val, &phy_regs->pll_config_2);
75 
76 	val = readl(&phy_regs->pll_config_1);
77 	val &= ~PLL_REGM_MASK;
78 	val |= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT;
79 	writel(val, &phy_regs->pll_config_1);
80 
81 	val = readl(&phy_regs->pll_config_4);
82 	val &= ~PLL_REGM_F_MASK;
83 	val |= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT;
84 	writel(val, &phy_regs->pll_config_4);
85 
86 	val = readl(&phy_regs->pll_config_3);
87 	val &= ~PLL_SD_MASK;
88 	val |= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT;
89 	writel(val, &phy_regs->pll_config_3);
90 
91 	omap_usb_dpll_relock(phy_regs);
92 }
93 
94 static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs)
95 {
96 	u32 rate = get_sys_clk_freq()/1000000;
97 	u32 val;
98 
99 	val = readl((*ctrl)->control_phy_power_usb);
100 	val &= ~(USB3_PWRCTL_CLK_CMD_MASK | USB3_PWRCTL_CLK_FREQ_MASK);
101 	val |= (USB3_PHY_PARTIAL_RX_POWERON | USB3_PHY_TX_RX_POWERON);
102 	val |= rate << USB3_PWRCTL_CLK_FREQ_SHIFT;
103 
104 	writel(val, (*ctrl)->control_phy_power_usb);
105 }
106 
107 static void usb3_phy_power(int on)
108 {
109 	u32 val;
110 
111 	val = readl((*ctrl)->control_phy_power_usb);
112 	if (on) {
113 		val &= ~USB3_PWRCTL_CLK_CMD_MASK;
114 		val |= USB3_PHY_TX_RX_POWERON;
115 	} else {
116 		val &= (~USB3_PWRCTL_CLK_CMD_MASK & ~USB3_PHY_TX_RX_POWERON);
117 	}
118 
119 	writel(val, (*ctrl)->control_phy_power_usb);
120 }
121 
122 static void dwc_usb3_phy_init(struct omap_usb3_phy *phy_regs)
123 {
124 	omap_usb_dpll_lock(phy_regs);
125 
126 	usb3_phy_partial_powerup(phy_regs);
127 	/*
128 	 * Give enough time for the PHY to partially power-up before
129 	 * powering it up completely. delay value suggested by the HW
130 	 * team.
131 	 */
132 	mdelay(100);
133 	usb3_phy_power(1);
134 }
135 
136 static void omap_enable_phy_clocks(struct omap_xhci *omap)
137 {
138 	u32	val;
139 
140 	/* Setting OCP2SCP1 register */
141 	setbits_le32((*prcm)->cm_l3init_ocp2scp1_clkctrl,
142 		     OCP2SCP1_CLKCTRL_MODULEMODE_HW);
143 
144 	/* Turn on 32K AON clk */
145 	setbits_le32((*prcm)->cm_coreaon_usb_phy_core_clkctrl,
146 		     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
147 
148 	/* Setting CM_L3INIT_CLKSTCTRL to 0x0 i.e NO sleep */
149 	writel(0x0, (*prcm)->cm_l3init_clkstctrl);
150 
151 	val = (USBOTGSS_DMADISABLE |
152 			USBOTGSS_STANDBYMODE_SMRT_WKUP |
153 			USBOTGSS_IDLEMODE_NOIDLE);
154 	writel(val, &omap->otg_wrapper->sysconfig);
155 
156 	/* Clear the utmi OTG status */
157 	val = readl(&omap->otg_wrapper->utmi_otg_status);
158 	writel(val, &omap->otg_wrapper->utmi_otg_status);
159 
160 	/* Enable interrupts */
161 	writel(USBOTGSS_COREIRQ_EN, &omap->otg_wrapper->irqenable_set_0);
162 	val = (USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN |
163 			USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN |
164 			USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN	|
165 			USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN	|
166 			USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN	|
167 			USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN	|
168 			USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN |
169 			USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN |
170 			USBOTGSS_IRQ_SET_1_OEVT_EN);
171 	writel(val, &omap->otg_wrapper->irqenable_set_1);
172 
173 	/* Clear the IRQ status */
174 	val = readl(&omap->otg_wrapper->irqstatus_1);
175 	writel(val, &omap->otg_wrapper->irqstatus_1);
176 	val = readl(&omap->otg_wrapper->irqstatus_0);
177 	writel(val, &omap->otg_wrapper->irqstatus_0);
178 
179 	/* Enable the USB OTG Super speed clocks */
180 	val = (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW);
181 	setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, val);
182 
183 };
184 
185 inline int __board_usb_init(void)
186 {
187 	return 0;
188 }
189 int board_usb_init(void) __attribute__((weak, alias("__board_usb_init")));
190 
191 static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
192 {
193 	clrsetbits_le32(&dwc3_reg->g_ctl,
194 			DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
195 			DWC3_GCTL_PRTCAPDIR(mode));
196 }
197 
198 static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
199 {
200 	/* Before Resetting PHY, put Core in Reset */
201 	setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
202 
203 	/* Assert USB3 PHY reset */
204 	setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
205 
206 	/* Assert USB2 PHY reset */
207 	setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
208 
209 	mdelay(100);
210 
211 	/* Clear USB3 PHY reset */
212 	clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
213 
214 	/* Clear USB2 PHY reset */
215 	clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
216 
217 	/* After PHYs are stable we can take Core out of reset state */
218 	clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
219 }
220 
221 static int dwc3_core_init(struct dwc3 *dwc3_reg)
222 {
223 	u32 reg;
224 	u32 revision;
225 	unsigned int dwc3_hwparams1;
226 
227 	revision = readl(&dwc3_reg->g_snpsid);
228 	/* This should read as U3 followed by revision number */
229 	if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
230 		puts("this is not a DesignWare USB3 DRD Core\n");
231 		return -1;
232 	}
233 
234 	dwc3_core_soft_reset(dwc3_reg);
235 
236 	dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
237 
238 	reg = readl(&dwc3_reg->g_ctl);
239 	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
240 	reg &= ~DWC3_GCTL_DISSCRAMBLE;
241 	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
242 	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
243 		reg &= ~DWC3_GCTL_DSBLCLKGTNG;
244 		break;
245 	default:
246 		debug("No power optimization available\n");
247 	}
248 
249 	/*
250 	 * WORKAROUND: DWC3 revisions <1.90a have a bug
251 	 * where the device can fail to connect at SuperSpeed
252 	 * and falls back to high-speed mode which causes
253 	 * the device to enter a Connect/Disconnect loop
254 	 */
255 	if ((revision & DWC3_REVISION_MASK) < 0x190a)
256 		reg |= DWC3_GCTL_U2RSTECN;
257 
258 	writel(reg, &dwc3_reg->g_ctl);
259 
260 	return 0;
261 }
262 
263 static int omap_xhci_core_init(struct omap_xhci *omap)
264 {
265 	int ret = 0;
266 
267 	omap_enable_phy_clocks(omap);
268 
269 	dwc_usb3_phy_init(omap->usb3_phy);
270 
271 	ret = dwc3_core_init(omap->dwc3_reg);
272 	if (ret) {
273 		debug("%s:failed to initialize core\n", __func__);
274 		return ret;
275 	}
276 
277 	/* We are hard-coding DWC3 core to Host Mode */
278 	dwc3_set_mode(omap->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
279 
280 	return ret;
281 }
282 
283 static void omap_xhci_core_exit(struct omap_xhci *omap)
284 {
285 	usb3_phy_power(0);
286 }
287 
288 int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
289 {
290 	struct omap_xhci *ctx = &omap;
291 	int ret = 0;
292 
293 	ctx->hcd = (struct xhci_hccr *)OMAP_XHCI_BASE;
294 	ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
295 	ctx->usb3_phy = (struct omap_usb3_phy *)OMAP_OCP1_SCP_BASE;
296 	ctx->otg_wrapper = (struct omap_dwc_wrapper *)OMAP_OTG_WRAPPER_BASE;
297 
298 	ret = board_usb_init();
299 	if (ret != 0) {
300 		puts("Failed to initialize board for USB\n");
301 		return ret;
302 	}
303 
304 	ret = omap_xhci_core_init(ctx);
305 	if (ret < 0) {
306 		puts("Failed to initialize xhci\n");
307 		return ret;
308 	}
309 
310 	*hccr = (struct xhci_hccr *)(OMAP_XHCI_BASE);
311 	*hcor = (struct xhci_hcor *)((uint32_t) *hccr
312 				+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
313 
314 	debug("omap-xhci: init hccr %x and hcor %x hc_length %d\n",
315 	      (uint32_t)*hccr, (uint32_t)*hcor,
316 	      (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
317 
318 	return ret;
319 }
320 
321 void xhci_hcd_stop(int index)
322 {
323 	struct omap_xhci *ctx = &omap;
324 
325 	omap_xhci_core_exit(ctx);
326 }
327