1 /* 2 * Copyright 2015,2016 Freescale Semiconductor, Inc. 3 * 4 * FSL USB HOST xHCI Controller 5 * 6 * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <usb.h> 13 #include <linux/errno.h> 14 #include <linux/compat.h> 15 #include <linux/usb/xhci-fsl.h> 16 #include <linux/usb/dwc3.h> 17 #include "xhci.h" 18 #include <fsl_errata.h> 19 #include <fsl_usb.h> 20 #include <dm.h> 21 22 /* Declare global data pointer */ 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #ifndef CONFIG_DM_USB 26 static struct fsl_xhci fsl_xhci; 27 unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR; 28 #else 29 struct xhci_fsl_priv { 30 struct xhci_ctrl xhci; 31 fdt_addr_t hcd_base; 32 struct fsl_xhci ctx; 33 }; 34 #endif 35 36 __weak int __board_usb_init(int index, enum usb_init_type init) 37 { 38 return 0; 39 } 40 41 static int erratum_a008751(void) 42 { 43 #if defined(CONFIG_TARGET_LS2080AQDS) || defined(CONFIG_TARGET_LS2080ARDB) 44 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; 45 writel(SCFG_USB3PRM1CR_INIT, scfg + SCFG_USB3PRM1CR / 4); 46 return 0; 47 #endif 48 return 1; 49 } 50 51 static void fsl_apply_xhci_errata(void) 52 { 53 int ret; 54 if (has_erratum_a008751()) { 55 ret = erratum_a008751(); 56 if (ret != 0) 57 puts("Failed to apply erratum a008751\n"); 58 } 59 } 60 61 static void fsl_xhci_set_beat_burst_length(struct dwc3 *dwc3_reg) 62 { 63 clrsetbits_le32(&dwc3_reg->g_sbuscfg0, USB3_ENABLE_BEAT_BURST_MASK, 64 USB3_ENABLE_BEAT_BURST); 65 setbits_le32(&dwc3_reg->g_sbuscfg1, USB3_SET_BEAT_BURST_LIMIT); 66 } 67 68 static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci) 69 { 70 int ret = 0; 71 72 ret = dwc3_core_init(fsl_xhci->dwc3_reg); 73 if (ret) { 74 debug("%s:failed to initialize core\n", __func__); 75 return ret; 76 } 77 78 /* We are hard-coding DWC3 core to Host Mode */ 79 dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); 80 81 /* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */ 82 dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT); 83 84 /* Change beat burst and outstanding pipelined transfers requests */ 85 fsl_xhci_set_beat_burst_length(fsl_xhci->dwc3_reg); 86 87 /* 88 * A-010151: The dwc3 phy TSMC 28-nm HPM 0.9/1.8 V does not 89 * reliably support Rx Detect in P3 mode(P3 is the default 90 * setting). Therefore, some USB3.0 devices may not be detected 91 * reliably in Super Speed mode. So, USB controller to configure 92 * USB in P2 mode whenever the Receive Detect feature is required. 93 * whenever the Receive Detect feature is required. 94 */ 95 if (has_erratum_a010151()) 96 clrsetbits_le32(&fsl_xhci->dwc3_reg->g_usb3pipectl[0], 97 DWC3_GUSB3PIPECTL_DISRXDETP3, 98 DWC3_GUSB3PIPECTL_DISRXDETP3); 99 100 return ret; 101 } 102 103 static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci) 104 { 105 /* 106 * Currently fsl socs do not support PHY shutdown from 107 * sw. But this support may be added in future socs. 108 */ 109 return 0; 110 } 111 112 #ifdef CONFIG_DM_USB 113 static int xhci_fsl_probe(struct udevice *dev) 114 { 115 struct xhci_fsl_priv *priv = dev_get_priv(dev); 116 struct xhci_hccr *hccr; 117 struct xhci_hcor *hcor; 118 119 int ret = 0; 120 121 /* 122 * Get the base address for XHCI controller from the device node 123 */ 124 priv->hcd_base = dev_get_addr(dev); 125 if (priv->hcd_base == FDT_ADDR_T_NONE) { 126 debug("Can't get the XHCI register base address\n"); 127 return -ENXIO; 128 } 129 priv->ctx.hcd = (struct xhci_hccr *)priv->hcd_base; 130 priv->ctx.dwc3_reg = (struct dwc3 *)((char *)(priv->hcd_base) + 131 DWC3_REG_OFFSET); 132 133 fsl_apply_xhci_errata(); 134 135 ret = fsl_xhci_core_init(&priv->ctx); 136 if (ret < 0) { 137 puts("Failed to initialize xhci\n"); 138 return ret; 139 } 140 141 hccr = (struct xhci_hccr *)(priv->ctx.hcd); 142 hcor = (struct xhci_hcor *)((uintptr_t) hccr 143 + HC_LENGTH(xhci_readl(&hccr->cr_capbase))); 144 145 debug("xhci-fsl: init hccr %lx and hcor %lx hc_length %lx\n", 146 (uintptr_t)hccr, (uintptr_t)hcor, 147 (uintptr_t)HC_LENGTH(xhci_readl(&hccr->cr_capbase))); 148 149 return xhci_register(dev, hccr, hcor); 150 } 151 152 static int xhci_fsl_remove(struct udevice *dev) 153 { 154 struct xhci_fsl_priv *priv = dev_get_priv(dev); 155 156 fsl_xhci_core_exit(&priv->ctx); 157 158 return xhci_deregister(dev); 159 } 160 161 static const struct udevice_id xhci_usb_ids[] = { 162 { .compatible = "fsl,layerscape-dwc3", }, 163 { } 164 }; 165 166 U_BOOT_DRIVER(xhci_fsl) = { 167 .name = "xhci_fsl", 168 .id = UCLASS_USB, 169 .of_match = xhci_usb_ids, 170 .probe = xhci_fsl_probe, 171 .remove = xhci_fsl_remove, 172 .ops = &xhci_usb_ops, 173 .platdata_auto_alloc_size = sizeof(struct usb_platdata), 174 .priv_auto_alloc_size = sizeof(struct xhci_fsl_priv), 175 .flags = DM_FLAG_ALLOC_PRIV_DMA, 176 }; 177 #else 178 int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) 179 { 180 struct fsl_xhci *ctx = &fsl_xhci; 181 int ret = 0; 182 183 ctx->hcd = (struct xhci_hccr *)ctr_addr[index]; 184 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); 185 186 ret = board_usb_init(index, USB_INIT_HOST); 187 if (ret != 0) { 188 puts("Failed to initialize board for USB\n"); 189 return ret; 190 } 191 192 fsl_apply_xhci_errata(); 193 194 ret = fsl_xhci_core_init(ctx); 195 if (ret < 0) { 196 puts("Failed to initialize xhci\n"); 197 return ret; 198 } 199 200 *hccr = (struct xhci_hccr *)ctx->hcd; 201 *hcor = (struct xhci_hcor *)((uintptr_t) *hccr 202 + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); 203 204 debug("fsl-xhci: init hccr %lx and hcor %lx hc_length %lx\n", 205 (uintptr_t)*hccr, (uintptr_t)*hcor, 206 (uintptr_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); 207 208 return ret; 209 } 210 211 void xhci_hcd_stop(int index) 212 { 213 struct fsl_xhci *ctx = &fsl_xhci; 214 215 fsl_xhci_core_exit(ctx); 216 } 217 #endif 218