1 /* 2 * SAMSUNG EXYNOS5 USB HOST XHCI Controller 3 * 4 * Copyright (C) 2012 Samsung Electronics Co.Ltd 5 * Vivek Gautam <gautam.vivek@samsung.com> 6 * Vikas Sajjan <vikas.sajjan@samsung.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 /* 12 * This file is a conglomeration for DWC3-init sequence and further 13 * exynos5 specific PHY-init sequence. 14 */ 15 16 #include <common.h> 17 #include <fdtdec.h> 18 #include <libfdt.h> 19 #include <malloc.h> 20 #include <usb.h> 21 #include <watchdog.h> 22 #include <asm/arch/cpu.h> 23 #include <asm/arch/power.h> 24 #include <asm/arch/xhci-exynos.h> 25 #include <asm/gpio.h> 26 #include <asm-generic/errno.h> 27 #include <linux/compat.h> 28 #include <linux/usb/dwc3.h> 29 30 #include "xhci.h" 31 32 /* Declare global data pointer */ 33 DECLARE_GLOBAL_DATA_PTR; 34 35 /** 36 * Contains pointers to register base addresses 37 * for the usb controller. 38 */ 39 struct exynos_xhci { 40 struct exynos_usb3_phy *usb3_phy; 41 struct xhci_hccr *hcd; 42 struct dwc3 *dwc3_reg; 43 struct gpio_desc vbus_gpio; 44 }; 45 46 static struct exynos_xhci exynos; 47 48 #ifdef CONFIG_OF_CONTROL 49 static int exynos_usb3_parse_dt(const void *blob, struct exynos_xhci *exynos) 50 { 51 fdt_addr_t addr; 52 unsigned int node; 53 int depth; 54 55 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_XHCI); 56 if (node <= 0) { 57 debug("XHCI: Can't get device node for xhci\n"); 58 return -ENODEV; 59 } 60 61 /* 62 * Get the base address for XHCI controller from the device node 63 */ 64 addr = fdtdec_get_addr(blob, node, "reg"); 65 if (addr == FDT_ADDR_T_NONE) { 66 debug("Can't get the XHCI register base address\n"); 67 return -ENXIO; 68 } 69 exynos->hcd = (struct xhci_hccr *)addr; 70 71 /* Vbus gpio */ 72 gpio_request_by_name_nodev(blob, node, "samsung,vbus-gpio", 0, 73 &exynos->vbus_gpio, GPIOD_IS_OUT); 74 75 depth = 0; 76 node = fdtdec_next_compatible_subnode(blob, node, 77 COMPAT_SAMSUNG_EXYNOS5_USB3_PHY, &depth); 78 if (node <= 0) { 79 debug("XHCI: Can't get device node for usb3-phy controller\n"); 80 return -ENODEV; 81 } 82 83 /* 84 * Get the base address for usbphy from the device node 85 */ 86 exynos->usb3_phy = (struct exynos_usb3_phy *)fdtdec_get_addr(blob, node, 87 "reg"); 88 if (exynos->usb3_phy == NULL) { 89 debug("Can't get the usbphy register address\n"); 90 return -ENXIO; 91 } 92 93 return 0; 94 } 95 #endif 96 97 static void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy) 98 { 99 u32 reg; 100 101 /* enabling usb_drd phy */ 102 set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN); 103 104 /* Reset USB 3.0 PHY */ 105 writel(0x0, &phy->phy_reg0); 106 107 clrbits_le32(&phy->phy_param0, 108 /* Select PHY CLK source */ 109 PHYPARAM0_REF_USE_PAD | 110 /* Set Loss-of-Signal Detector sensitivity */ 111 PHYPARAM0_REF_LOSLEVEL_MASK); 112 setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL); 113 114 writel(0x0, &phy->phy_resume); 115 116 /* 117 * Setting the Frame length Adj value[6:1] to default 0x20 118 * See xHCI 1.0 spec, 5.2.4 119 */ 120 setbits_le32(&phy->link_system, 121 LINKSYSTEM_XHCI_VERSION_CONTROL | 122 LINKSYSTEM_FLADJ(0x20)); 123 124 /* Set Tx De-Emphasis level */ 125 clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK); 126 setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH); 127 128 setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL); 129 130 /* PHYTEST POWERDOWN Control */ 131 clrbits_le32(&phy->phy_test, 132 PHYTEST_POWERDOWN_SSP | 133 PHYTEST_POWERDOWN_HSP); 134 135 /* UTMI Power Control */ 136 writel(PHYUTMI_OTGDISABLE, &phy->phy_utmi); 137 138 /* Use core clock from main PLL */ 139 reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK | 140 /* Default 24Mhz crystal clock */ 141 PHYCLKRST_FSEL(FSEL_CLKSEL_24M) | 142 PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF | 143 PHYCLKRST_SSC_REFCLKSEL(0x88) | 144 /* Force PortReset of PHY */ 145 PHYCLKRST_PORTRESET | 146 /* Digital power supply in normal operating mode */ 147 PHYCLKRST_RETENABLEN | 148 /* Enable ref clock for SS function */ 149 PHYCLKRST_REF_SSP_EN | 150 /* Enable spread spectrum */ 151 PHYCLKRST_SSC_EN | 152 /* Power down HS Bias and PLL blocks in suspend mode */ 153 PHYCLKRST_COMMONONN; 154 155 writel(reg, &phy->phy_clk_rst); 156 157 /* giving time to Phy clock to settle before resetting */ 158 udelay(10); 159 160 reg &= ~PHYCLKRST_PORTRESET; 161 writel(reg, &phy->phy_clk_rst); 162 } 163 164 static void exynos5_usb3_phy_exit(struct exynos_usb3_phy *phy) 165 { 166 setbits_le32(&phy->phy_utmi, 167 PHYUTMI_OTGDISABLE | 168 PHYUTMI_FORCESUSPEND | 169 PHYUTMI_FORCESLEEP); 170 171 clrbits_le32(&phy->phy_clk_rst, 172 PHYCLKRST_REF_SSP_EN | 173 PHYCLKRST_SSC_EN | 174 PHYCLKRST_COMMONONN); 175 176 /* PHYTEST POWERDOWN Control to remove leakage current */ 177 setbits_le32(&phy->phy_test, 178 PHYTEST_POWERDOWN_SSP | 179 PHYTEST_POWERDOWN_HSP); 180 181 /* disabling usb_drd phy */ 182 set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_DISABLE); 183 } 184 185 static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) 186 { 187 clrsetbits_le32(&dwc3_reg->g_ctl, 188 DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG), 189 DWC3_GCTL_PRTCAPDIR(mode)); 190 } 191 192 static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) 193 { 194 /* Before Resetting PHY, put Core in Reset */ 195 setbits_le32(&dwc3_reg->g_ctl, 196 DWC3_GCTL_CORESOFTRESET); 197 198 /* Assert USB3 PHY reset */ 199 setbits_le32(&dwc3_reg->g_usb3pipectl[0], 200 DWC3_GUSB3PIPECTL_PHYSOFTRST); 201 202 /* Assert USB2 PHY reset */ 203 setbits_le32(&dwc3_reg->g_usb2phycfg, 204 DWC3_GUSB2PHYCFG_PHYSOFTRST); 205 206 mdelay(100); 207 208 /* Clear USB3 PHY reset */ 209 clrbits_le32(&dwc3_reg->g_usb3pipectl[0], 210 DWC3_GUSB3PIPECTL_PHYSOFTRST); 211 212 /* Clear USB2 PHY reset */ 213 clrbits_le32(&dwc3_reg->g_usb2phycfg, 214 DWC3_GUSB2PHYCFG_PHYSOFTRST); 215 216 /* After PHYs are stable we can take Core out of reset state */ 217 clrbits_le32(&dwc3_reg->g_ctl, 218 DWC3_GCTL_CORESOFTRESET); 219 } 220 221 static int dwc3_core_init(struct dwc3 *dwc3_reg) 222 { 223 u32 reg; 224 u32 revision; 225 unsigned int dwc3_hwparams1; 226 227 revision = readl(&dwc3_reg->g_snpsid); 228 /* This should read as U3 followed by revision number */ 229 if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) { 230 puts("this is not a DesignWare USB3 DRD Core\n"); 231 return -EINVAL; 232 } 233 234 dwc3_core_soft_reset(dwc3_reg); 235 236 dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1); 237 238 reg = readl(&dwc3_reg->g_ctl); 239 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 240 reg &= ~DWC3_GCTL_DISSCRAMBLE; 241 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) { 242 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 243 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 244 break; 245 default: 246 debug("No power optimization available\n"); 247 } 248 249 /* 250 * WORKAROUND: DWC3 revisions <1.90a have a bug 251 * where the device can fail to connect at SuperSpeed 252 * and falls back to high-speed mode which causes 253 * the device to enter a Connect/Disconnect loop 254 */ 255 if ((revision & DWC3_REVISION_MASK) < 0x190a) 256 reg |= DWC3_GCTL_U2RSTECN; 257 258 writel(reg, &dwc3_reg->g_ctl); 259 260 return 0; 261 } 262 263 static int exynos_xhci_core_init(struct exynos_xhci *exynos) 264 { 265 int ret; 266 267 exynos5_usb3_phy_init(exynos->usb3_phy); 268 269 ret = dwc3_core_init(exynos->dwc3_reg); 270 if (ret) { 271 debug("failed to initialize core\n"); 272 return -EINVAL; 273 } 274 275 /* We are hard-coding DWC3 core to Host Mode */ 276 dwc3_set_mode(exynos->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); 277 278 return 0; 279 } 280 281 static void exynos_xhci_core_exit(struct exynos_xhci *exynos) 282 { 283 exynos5_usb3_phy_exit(exynos->usb3_phy); 284 } 285 286 int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) 287 { 288 struct exynos_xhci *ctx = &exynos; 289 int ret; 290 291 #ifdef CONFIG_OF_CONTROL 292 exynos_usb3_parse_dt(gd->fdt_blob, ctx); 293 #else 294 ctx->usb3_phy = (struct exynos_usb3_phy *)samsung_get_base_usb3_phy(); 295 ctx->hcd = (struct xhci_hccr *)samsung_get_base_usb_xhci(); 296 #endif 297 298 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); 299 300 #ifdef CONFIG_OF_CONTROL 301 /* setup the Vbus gpio here */ 302 if (dm_gpio_is_valid(&ctx->vbus_gpio)) 303 dm_gpio_set_value(&ctx->vbus_gpio, 1); 304 #endif 305 306 ret = exynos_xhci_core_init(ctx); 307 if (ret) { 308 puts("XHCI: failed to initialize controller\n"); 309 return -EINVAL; 310 } 311 312 *hccr = (ctx->hcd); 313 *hcor = (struct xhci_hcor *)((uint32_t) *hccr 314 + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); 315 316 debug("Exynos5-xhci: init hccr %x and hcor %x hc_length %d\n", 317 (uint32_t)*hccr, (uint32_t)*hcor, 318 (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); 319 320 return 0; 321 } 322 323 void xhci_hcd_stop(int index) 324 { 325 struct exynos_xhci *ctx = &exynos; 326 327 exynos_xhci_core_exit(ctx); 328 } 329