1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * SAMSUNG EXYNOS5 USB HOST XHCI Controller 4 * 5 * Copyright (C) 2012 Samsung Electronics Co.Ltd 6 * Vivek Gautam <gautam.vivek@samsung.com> 7 * Vikas Sajjan <vikas.sajjan@samsung.com> 8 */ 9 10 /* 11 * This file is a conglomeration for DWC3-init sequence and further 12 * exynos5 specific PHY-init sequence. 13 */ 14 15 #include <common.h> 16 #include <dm.h> 17 #include <fdtdec.h> 18 #include <linux/libfdt.h> 19 #include <malloc.h> 20 #include <usb.h> 21 #include <watchdog.h> 22 #include <asm/arch/cpu.h> 23 #include <asm/arch/power.h> 24 #include <asm/arch/xhci-exynos.h> 25 #include <asm/gpio.h> 26 #include <linux/errno.h> 27 #include <linux/compat.h> 28 #include <linux/usb/dwc3.h> 29 30 #include "xhci.h" 31 32 /* Declare global data pointer */ 33 DECLARE_GLOBAL_DATA_PTR; 34 35 struct exynos_xhci_platdata { 36 fdt_addr_t hcd_base; 37 fdt_addr_t phy_base; 38 struct gpio_desc vbus_gpio; 39 }; 40 41 /** 42 * Contains pointers to register base addresses 43 * for the usb controller. 44 */ 45 struct exynos_xhci { 46 struct usb_platdata usb_plat; 47 struct xhci_ctrl ctrl; 48 struct exynos_usb3_phy *usb3_phy; 49 struct xhci_hccr *hcd; 50 struct dwc3 *dwc3_reg; 51 }; 52 53 static int xhci_usb_ofdata_to_platdata(struct udevice *dev) 54 { 55 struct exynos_xhci_platdata *plat = dev_get_platdata(dev); 56 const void *blob = gd->fdt_blob; 57 unsigned int node; 58 int depth; 59 60 /* 61 * Get the base address for XHCI controller from the device node 62 */ 63 plat->hcd_base = devfdt_get_addr(dev); 64 if (plat->hcd_base == FDT_ADDR_T_NONE) { 65 debug("Can't get the XHCI register base address\n"); 66 return -ENXIO; 67 } 68 69 depth = 0; 70 node = fdtdec_next_compatible_subnode(blob, dev_of_offset(dev), 71 COMPAT_SAMSUNG_EXYNOS5_USB3_PHY, &depth); 72 if (node <= 0) { 73 debug("XHCI: Can't get device node for usb3-phy controller\n"); 74 return -ENODEV; 75 } 76 77 /* 78 * Get the base address for usbphy from the device node 79 */ 80 plat->phy_base = fdtdec_get_addr(blob, node, "reg"); 81 if (plat->phy_base == FDT_ADDR_T_NONE) { 82 debug("Can't get the usbphy register address\n"); 83 return -ENXIO; 84 } 85 86 /* Vbus gpio */ 87 gpio_request_by_name(dev, "samsung,vbus-gpio", 0, 88 &plat->vbus_gpio, GPIOD_IS_OUT); 89 90 return 0; 91 } 92 93 static void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy) 94 { 95 u32 reg; 96 97 /* enabling usb_drd phy */ 98 set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN); 99 100 /* Reset USB 3.0 PHY */ 101 writel(0x0, &phy->phy_reg0); 102 103 clrbits_le32(&phy->phy_param0, 104 /* Select PHY CLK source */ 105 PHYPARAM0_REF_USE_PAD | 106 /* Set Loss-of-Signal Detector sensitivity */ 107 PHYPARAM0_REF_LOSLEVEL_MASK); 108 setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL); 109 110 writel(0x0, &phy->phy_resume); 111 112 /* 113 * Setting the Frame length Adj value[6:1] to default 0x20 114 * See xHCI 1.0 spec, 5.2.4 115 */ 116 setbits_le32(&phy->link_system, 117 LINKSYSTEM_XHCI_VERSION_CONTROL | 118 LINKSYSTEM_FLADJ(0x20)); 119 120 /* Set Tx De-Emphasis level */ 121 clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK); 122 setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH); 123 124 setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL); 125 126 /* PHYTEST POWERDOWN Control */ 127 clrbits_le32(&phy->phy_test, 128 PHYTEST_POWERDOWN_SSP | 129 PHYTEST_POWERDOWN_HSP); 130 131 /* UTMI Power Control */ 132 writel(PHYUTMI_OTGDISABLE, &phy->phy_utmi); 133 134 /* Use core clock from main PLL */ 135 reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK | 136 /* Default 24Mhz crystal clock */ 137 PHYCLKRST_FSEL(FSEL_CLKSEL_24M) | 138 PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF | 139 PHYCLKRST_SSC_REFCLKSEL(0x88) | 140 /* Force PortReset of PHY */ 141 PHYCLKRST_PORTRESET | 142 /* Digital power supply in normal operating mode */ 143 PHYCLKRST_RETENABLEN | 144 /* Enable ref clock for SS function */ 145 PHYCLKRST_REF_SSP_EN | 146 /* Enable spread spectrum */ 147 PHYCLKRST_SSC_EN | 148 /* Power down HS Bias and PLL blocks in suspend mode */ 149 PHYCLKRST_COMMONONN; 150 151 writel(reg, &phy->phy_clk_rst); 152 153 /* giving time to Phy clock to settle before resetting */ 154 udelay(10); 155 156 reg &= ~PHYCLKRST_PORTRESET; 157 writel(reg, &phy->phy_clk_rst); 158 } 159 160 static void exynos5_usb3_phy_exit(struct exynos_usb3_phy *phy) 161 { 162 setbits_le32(&phy->phy_utmi, 163 PHYUTMI_OTGDISABLE | 164 PHYUTMI_FORCESUSPEND | 165 PHYUTMI_FORCESLEEP); 166 167 clrbits_le32(&phy->phy_clk_rst, 168 PHYCLKRST_REF_SSP_EN | 169 PHYCLKRST_SSC_EN | 170 PHYCLKRST_COMMONONN); 171 172 /* PHYTEST POWERDOWN Control to remove leakage current */ 173 setbits_le32(&phy->phy_test, 174 PHYTEST_POWERDOWN_SSP | 175 PHYTEST_POWERDOWN_HSP); 176 177 /* disabling usb_drd phy */ 178 set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_DISABLE); 179 } 180 181 static int exynos_xhci_core_init(struct exynos_xhci *exynos) 182 { 183 int ret; 184 185 exynos5_usb3_phy_init(exynos->usb3_phy); 186 187 ret = dwc3_core_init(exynos->dwc3_reg); 188 if (ret) { 189 debug("failed to initialize core\n"); 190 return -EINVAL; 191 } 192 193 /* We are hard-coding DWC3 core to Host Mode */ 194 dwc3_set_mode(exynos->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); 195 196 return 0; 197 } 198 199 static void exynos_xhci_core_exit(struct exynos_xhci *exynos) 200 { 201 exynos5_usb3_phy_exit(exynos->usb3_phy); 202 } 203 204 static int xhci_usb_probe(struct udevice *dev) 205 { 206 struct exynos_xhci_platdata *plat = dev_get_platdata(dev); 207 struct exynos_xhci *ctx = dev_get_priv(dev); 208 struct xhci_hcor *hcor; 209 int ret; 210 211 ctx->hcd = (struct xhci_hccr *)plat->hcd_base; 212 ctx->usb3_phy = (struct exynos_usb3_phy *)plat->phy_base; 213 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); 214 hcor = (struct xhci_hcor *)((uint32_t)ctx->hcd + 215 HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase))); 216 217 /* setup the Vbus gpio here */ 218 if (dm_gpio_is_valid(&plat->vbus_gpio)) 219 dm_gpio_set_value(&plat->vbus_gpio, 1); 220 221 ret = exynos_xhci_core_init(ctx); 222 if (ret) { 223 puts("XHCI: failed to initialize controller\n"); 224 return -EINVAL; 225 } 226 227 return xhci_register(dev, ctx->hcd, hcor); 228 } 229 230 static int xhci_usb_remove(struct udevice *dev) 231 { 232 struct exynos_xhci *ctx = dev_get_priv(dev); 233 int ret; 234 235 ret = xhci_deregister(dev); 236 if (ret) 237 return ret; 238 exynos_xhci_core_exit(ctx); 239 240 return 0; 241 } 242 243 static const struct udevice_id xhci_usb_ids[] = { 244 { .compatible = "samsung,exynos5250-xhci" }, 245 { } 246 }; 247 248 U_BOOT_DRIVER(usb_xhci) = { 249 .name = "xhci_exynos", 250 .id = UCLASS_USB, 251 .of_match = xhci_usb_ids, 252 .ofdata_to_platdata = xhci_usb_ofdata_to_platdata, 253 .probe = xhci_usb_probe, 254 .remove = xhci_usb_remove, 255 .ops = &xhci_usb_ops, 256 .platdata_auto_alloc_size = sizeof(struct exynos_xhci_platdata), 257 .priv_auto_alloc_size = sizeof(struct exynos_xhci), 258 .flags = DM_FLAG_ALLOC_PRIV_DMA, 259 }; 260