1 /* 2 * SAMSUNG EXYNOS5 USB HOST XHCI Controller 3 * 4 * Copyright (C) 2012 Samsung Electronics Co.Ltd 5 * Vivek Gautam <gautam.vivek@samsung.com> 6 * Vikas Sajjan <vikas.sajjan@samsung.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 /* 12 * This file is a conglomeration for DWC3-init sequence and further 13 * exynos5 specific PHY-init sequence. 14 */ 15 16 #include <common.h> 17 #include <dm.h> 18 #include <fdtdec.h> 19 #include <libfdt.h> 20 #include <malloc.h> 21 #include <usb.h> 22 #include <watchdog.h> 23 #include <asm/arch/cpu.h> 24 #include <asm/arch/power.h> 25 #include <asm/arch/xhci-exynos.h> 26 #include <asm/gpio.h> 27 #include <asm-generic/errno.h> 28 #include <linux/compat.h> 29 #include <linux/usb/dwc3.h> 30 31 #include "xhci.h" 32 33 /* Declare global data pointer */ 34 DECLARE_GLOBAL_DATA_PTR; 35 36 #ifdef CONFIG_DM_USB 37 struct exynos_xhci_platdata { 38 fdt_addr_t hcd_base; 39 fdt_addr_t phy_base; 40 struct gpio_desc vbus_gpio; 41 }; 42 #endif 43 44 /** 45 * Contains pointers to register base addresses 46 * for the usb controller. 47 */ 48 struct exynos_xhci { 49 #ifdef CONFIG_DM_USB 50 struct usb_platdata usb_plat; 51 #endif 52 struct xhci_ctrl ctrl; 53 struct exynos_usb3_phy *usb3_phy; 54 struct xhci_hccr *hcd; 55 struct dwc3 *dwc3_reg; 56 #ifndef CONFIG_DM_USB 57 struct gpio_desc vbus_gpio; 58 #endif 59 }; 60 61 #ifndef CONFIG_DM_USB 62 static struct exynos_xhci exynos; 63 #endif 64 65 #ifdef CONFIG_DM_USB 66 static int xhci_usb_ofdata_to_platdata(struct udevice *dev) 67 { 68 struct exynos_xhci_platdata *plat = dev_get_platdata(dev); 69 const void *blob = gd->fdt_blob; 70 unsigned int node; 71 int depth; 72 73 /* 74 * Get the base address for XHCI controller from the device node 75 */ 76 plat->hcd_base = fdtdec_get_addr(blob, dev->of_offset, "reg"); 77 if (plat->hcd_base == FDT_ADDR_T_NONE) { 78 debug("Can't get the XHCI register base address\n"); 79 return -ENXIO; 80 } 81 82 depth = 0; 83 node = fdtdec_next_compatible_subnode(blob, dev->of_offset, 84 COMPAT_SAMSUNG_EXYNOS5_USB3_PHY, &depth); 85 if (node <= 0) { 86 debug("XHCI: Can't get device node for usb3-phy controller\n"); 87 return -ENODEV; 88 } 89 90 /* 91 * Get the base address for usbphy from the device node 92 */ 93 plat->phy_base = fdtdec_get_addr(blob, node, "reg"); 94 if (plat->phy_base == FDT_ADDR_T_NONE) { 95 debug("Can't get the usbphy register address\n"); 96 return -ENXIO; 97 } 98 99 /* Vbus gpio */ 100 gpio_request_by_name(dev, "samsung,vbus-gpio", 0, 101 &plat->vbus_gpio, GPIOD_IS_OUT); 102 103 return 0; 104 } 105 #else 106 static int exynos_usb3_parse_dt(const void *blob, struct exynos_xhci *exynos) 107 { 108 fdt_addr_t addr; 109 unsigned int node; 110 int depth; 111 112 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_XHCI); 113 if (node <= 0) { 114 debug("XHCI: Can't get device node for xhci\n"); 115 return -ENODEV; 116 } 117 118 /* 119 * Get the base address for XHCI controller from the device node 120 */ 121 addr = fdtdec_get_addr(blob, node, "reg"); 122 if (addr == FDT_ADDR_T_NONE) { 123 debug("Can't get the XHCI register base address\n"); 124 return -ENXIO; 125 } 126 exynos->hcd = (struct xhci_hccr *)addr; 127 128 /* Vbus gpio */ 129 gpio_request_by_name_nodev(blob, node, "samsung,vbus-gpio", 0, 130 &exynos->vbus_gpio, GPIOD_IS_OUT); 131 132 depth = 0; 133 node = fdtdec_next_compatible_subnode(blob, node, 134 COMPAT_SAMSUNG_EXYNOS5_USB3_PHY, &depth); 135 if (node <= 0) { 136 debug("XHCI: Can't get device node for usb3-phy controller\n"); 137 return -ENODEV; 138 } 139 140 /* 141 * Get the base address for usbphy from the device node 142 */ 143 exynos->usb3_phy = (struct exynos_usb3_phy *)fdtdec_get_addr(blob, node, 144 "reg"); 145 if (exynos->usb3_phy == NULL) { 146 debug("Can't get the usbphy register address\n"); 147 return -ENXIO; 148 } 149 150 return 0; 151 } 152 #endif 153 154 static void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy) 155 { 156 u32 reg; 157 158 /* enabling usb_drd phy */ 159 set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN); 160 161 /* Reset USB 3.0 PHY */ 162 writel(0x0, &phy->phy_reg0); 163 164 clrbits_le32(&phy->phy_param0, 165 /* Select PHY CLK source */ 166 PHYPARAM0_REF_USE_PAD | 167 /* Set Loss-of-Signal Detector sensitivity */ 168 PHYPARAM0_REF_LOSLEVEL_MASK); 169 setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL); 170 171 writel(0x0, &phy->phy_resume); 172 173 /* 174 * Setting the Frame length Adj value[6:1] to default 0x20 175 * See xHCI 1.0 spec, 5.2.4 176 */ 177 setbits_le32(&phy->link_system, 178 LINKSYSTEM_XHCI_VERSION_CONTROL | 179 LINKSYSTEM_FLADJ(0x20)); 180 181 /* Set Tx De-Emphasis level */ 182 clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK); 183 setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH); 184 185 setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL); 186 187 /* PHYTEST POWERDOWN Control */ 188 clrbits_le32(&phy->phy_test, 189 PHYTEST_POWERDOWN_SSP | 190 PHYTEST_POWERDOWN_HSP); 191 192 /* UTMI Power Control */ 193 writel(PHYUTMI_OTGDISABLE, &phy->phy_utmi); 194 195 /* Use core clock from main PLL */ 196 reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK | 197 /* Default 24Mhz crystal clock */ 198 PHYCLKRST_FSEL(FSEL_CLKSEL_24M) | 199 PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF | 200 PHYCLKRST_SSC_REFCLKSEL(0x88) | 201 /* Force PortReset of PHY */ 202 PHYCLKRST_PORTRESET | 203 /* Digital power supply in normal operating mode */ 204 PHYCLKRST_RETENABLEN | 205 /* Enable ref clock for SS function */ 206 PHYCLKRST_REF_SSP_EN | 207 /* Enable spread spectrum */ 208 PHYCLKRST_SSC_EN | 209 /* Power down HS Bias and PLL blocks in suspend mode */ 210 PHYCLKRST_COMMONONN; 211 212 writel(reg, &phy->phy_clk_rst); 213 214 /* giving time to Phy clock to settle before resetting */ 215 udelay(10); 216 217 reg &= ~PHYCLKRST_PORTRESET; 218 writel(reg, &phy->phy_clk_rst); 219 } 220 221 static void exynos5_usb3_phy_exit(struct exynos_usb3_phy *phy) 222 { 223 setbits_le32(&phy->phy_utmi, 224 PHYUTMI_OTGDISABLE | 225 PHYUTMI_FORCESUSPEND | 226 PHYUTMI_FORCESLEEP); 227 228 clrbits_le32(&phy->phy_clk_rst, 229 PHYCLKRST_REF_SSP_EN | 230 PHYCLKRST_SSC_EN | 231 PHYCLKRST_COMMONONN); 232 233 /* PHYTEST POWERDOWN Control to remove leakage current */ 234 setbits_le32(&phy->phy_test, 235 PHYTEST_POWERDOWN_SSP | 236 PHYTEST_POWERDOWN_HSP); 237 238 /* disabling usb_drd phy */ 239 set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_DISABLE); 240 } 241 242 static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) 243 { 244 clrsetbits_le32(&dwc3_reg->g_ctl, 245 DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG), 246 DWC3_GCTL_PRTCAPDIR(mode)); 247 } 248 249 static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) 250 { 251 /* Before Resetting PHY, put Core in Reset */ 252 setbits_le32(&dwc3_reg->g_ctl, 253 DWC3_GCTL_CORESOFTRESET); 254 255 /* Assert USB3 PHY reset */ 256 setbits_le32(&dwc3_reg->g_usb3pipectl[0], 257 DWC3_GUSB3PIPECTL_PHYSOFTRST); 258 259 /* Assert USB2 PHY reset */ 260 setbits_le32(&dwc3_reg->g_usb2phycfg, 261 DWC3_GUSB2PHYCFG_PHYSOFTRST); 262 263 mdelay(100); 264 265 /* Clear USB3 PHY reset */ 266 clrbits_le32(&dwc3_reg->g_usb3pipectl[0], 267 DWC3_GUSB3PIPECTL_PHYSOFTRST); 268 269 /* Clear USB2 PHY reset */ 270 clrbits_le32(&dwc3_reg->g_usb2phycfg, 271 DWC3_GUSB2PHYCFG_PHYSOFTRST); 272 273 /* After PHYs are stable we can take Core out of reset state */ 274 clrbits_le32(&dwc3_reg->g_ctl, 275 DWC3_GCTL_CORESOFTRESET); 276 } 277 278 static int dwc3_core_init(struct dwc3 *dwc3_reg) 279 { 280 u32 reg; 281 u32 revision; 282 unsigned int dwc3_hwparams1; 283 284 revision = readl(&dwc3_reg->g_snpsid); 285 /* This should read as U3 followed by revision number */ 286 if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) { 287 puts("this is not a DesignWare USB3 DRD Core\n"); 288 return -EINVAL; 289 } 290 291 dwc3_core_soft_reset(dwc3_reg); 292 293 dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1); 294 295 reg = readl(&dwc3_reg->g_ctl); 296 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 297 reg &= ~DWC3_GCTL_DISSCRAMBLE; 298 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) { 299 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 300 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 301 break; 302 default: 303 debug("No power optimization available\n"); 304 } 305 306 /* 307 * WORKAROUND: DWC3 revisions <1.90a have a bug 308 * where the device can fail to connect at SuperSpeed 309 * and falls back to high-speed mode which causes 310 * the device to enter a Connect/Disconnect loop 311 */ 312 if ((revision & DWC3_REVISION_MASK) < 0x190a) 313 reg |= DWC3_GCTL_U2RSTECN; 314 315 writel(reg, &dwc3_reg->g_ctl); 316 317 return 0; 318 } 319 320 static int exynos_xhci_core_init(struct exynos_xhci *exynos) 321 { 322 int ret; 323 324 exynos5_usb3_phy_init(exynos->usb3_phy); 325 326 ret = dwc3_core_init(exynos->dwc3_reg); 327 if (ret) { 328 debug("failed to initialize core\n"); 329 return -EINVAL; 330 } 331 332 /* We are hard-coding DWC3 core to Host Mode */ 333 dwc3_set_mode(exynos->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); 334 335 return 0; 336 } 337 338 static void exynos_xhci_core_exit(struct exynos_xhci *exynos) 339 { 340 exynos5_usb3_phy_exit(exynos->usb3_phy); 341 } 342 343 #ifndef CONFIG_DM_USB 344 int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) 345 { 346 struct exynos_xhci *ctx = &exynos; 347 int ret; 348 349 #ifdef CONFIG_OF_CONTROL 350 exynos_usb3_parse_dt(gd->fdt_blob, ctx); 351 #else 352 ctx->usb3_phy = (struct exynos_usb3_phy *)samsung_get_base_usb3_phy(); 353 ctx->hcd = (struct xhci_hccr *)samsung_get_base_usb_xhci(); 354 #endif 355 356 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); 357 358 #ifdef CONFIG_OF_CONTROL 359 /* setup the Vbus gpio here */ 360 if (dm_gpio_is_valid(&ctx->vbus_gpio)) 361 dm_gpio_set_value(&ctx->vbus_gpio, 1); 362 #endif 363 364 ret = exynos_xhci_core_init(ctx); 365 if (ret) { 366 puts("XHCI: failed to initialize controller\n"); 367 return -EINVAL; 368 } 369 370 *hccr = (ctx->hcd); 371 *hcor = (struct xhci_hcor *)((uint32_t) *hccr 372 + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); 373 374 debug("Exynos5-xhci: init hccr %x and hcor %x hc_length %d\n", 375 (uint32_t)*hccr, (uint32_t)*hcor, 376 (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); 377 378 return 0; 379 } 380 381 void xhci_hcd_stop(int index) 382 { 383 struct exynos_xhci *ctx = &exynos; 384 385 exynos_xhci_core_exit(ctx); 386 } 387 #endif 388 389 #ifdef CONFIG_DM_USB 390 static int xhci_usb_probe(struct udevice *dev) 391 { 392 struct exynos_xhci_platdata *plat = dev_get_platdata(dev); 393 struct exynos_xhci *ctx = dev_get_priv(dev); 394 struct xhci_hcor *hcor; 395 int ret; 396 397 ctx->hcd = (struct xhci_hccr *)plat->hcd_base; 398 ctx->usb3_phy = (struct exynos_usb3_phy *)plat->phy_base; 399 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); 400 hcor = (struct xhci_hcor *)((uint32_t)ctx->hcd + 401 HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase))); 402 403 /* setup the Vbus gpio here */ 404 if (dm_gpio_is_valid(&plat->vbus_gpio)) 405 dm_gpio_set_value(&plat->vbus_gpio, 1); 406 407 ret = exynos_xhci_core_init(ctx); 408 if (ret) { 409 puts("XHCI: failed to initialize controller\n"); 410 return -EINVAL; 411 } 412 413 return xhci_register(dev, ctx->hcd, hcor); 414 } 415 416 static int xhci_usb_remove(struct udevice *dev) 417 { 418 struct exynos_xhci *ctx = dev_get_priv(dev); 419 int ret; 420 421 ret = xhci_deregister(dev); 422 if (ret) 423 return ret; 424 exynos_xhci_core_exit(ctx); 425 426 return 0; 427 } 428 429 static const struct udevice_id xhci_usb_ids[] = { 430 { .compatible = "samsung,exynos5250-xhci" }, 431 { } 432 }; 433 434 U_BOOT_DRIVER(usb_xhci) = { 435 .name = "xhci_exynos", 436 .id = UCLASS_USB, 437 .of_match = xhci_usb_ids, 438 .ofdata_to_platdata = xhci_usb_ofdata_to_platdata, 439 .probe = xhci_usb_probe, 440 .remove = xhci_usb_remove, 441 .ops = &xhci_usb_ops, 442 .platdata_auto_alloc_size = sizeof(struct exynos_xhci_platdata), 443 .priv_auto_alloc_size = sizeof(struct exynos_xhci), 444 .flags = DM_FLAG_ALLOC_PRIV_DMA, 445 }; 446 #endif 447