1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * DWC3 controller driver 5 * 6 * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <asm/io.h> 13 #include <linux/usb/dwc3.h> 14 15 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) 16 { 17 clrsetbits_le32(&dwc3_reg->g_ctl, 18 DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG), 19 DWC3_GCTL_PRTCAPDIR(mode)); 20 } 21 22 void dwc3_phy_reset(struct dwc3 *dwc3_reg) 23 { 24 /* Assert USB3 PHY reset */ 25 setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); 26 27 /* Assert USB2 PHY reset */ 28 setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); 29 30 mdelay(100); 31 32 /* Clear USB3 PHY reset */ 33 clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); 34 35 /* Clear USB2 PHY reset */ 36 clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); 37 } 38 39 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) 40 { 41 /* Before Resetting PHY, put Core in Reset */ 42 setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); 43 44 /* reset USB3 phy - if required */ 45 dwc3_phy_reset(dwc3_reg); 46 47 /* After PHYs are stable we can take Core out of reset state */ 48 clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); 49 } 50 51 int dwc3_core_init(struct dwc3 *dwc3_reg) 52 { 53 u32 reg; 54 u32 revision; 55 unsigned int dwc3_hwparams1; 56 57 revision = readl(&dwc3_reg->g_snpsid); 58 /* This should read as U3 followed by revision number */ 59 if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) { 60 puts("this is not a DesignWare USB3 DRD Core\n"); 61 return -1; 62 } 63 64 dwc3_core_soft_reset(dwc3_reg); 65 66 dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1); 67 68 reg = readl(&dwc3_reg->g_ctl); 69 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 70 reg &= ~DWC3_GCTL_DISSCRAMBLE; 71 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) { 72 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 73 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 74 break; 75 default: 76 debug("No power optimization available\n"); 77 } 78 79 /* 80 * WORKAROUND: DWC3 revisions <1.90a have a bug 81 * where the device can fail to connect at SuperSpeed 82 * and falls back to high-speed mode which causes 83 * the device to enter a Connect/Disconnect loop 84 */ 85 if ((revision & DWC3_REVISION_MASK) < 0x190a) 86 reg |= DWC3_GCTL_U2RSTECN; 87 88 writel(reg, &dwc3_reg->g_ctl); 89 90 return 0; 91 } 92 93 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val) 94 { 95 setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL | 96 GFLADJ_30MHZ(val)); 97 } 98