1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2015 Freescale Semiconductor, Inc. 4 * 5 * DWC3 controller driver 6 * 7 * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com> 8 */ 9 10 #include <common.h> 11 #include <dm.h> 12 #include <fdtdec.h> 13 #include <generic-phy.h> 14 #include <usb.h> 15 16 #include "xhci.h" 17 #include <asm/io.h> 18 #include <linux/usb/dwc3.h> 19 #include <linux/usb/otg.h> 20 21 struct xhci_dwc3_platdata { 22 struct phy *usb_phys; 23 int num_phys; 24 }; 25 26 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) 27 { 28 clrsetbits_le32(&dwc3_reg->g_ctl, 29 DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG), 30 DWC3_GCTL_PRTCAPDIR(mode)); 31 } 32 33 static void dwc3_phy_reset(struct dwc3 *dwc3_reg) 34 { 35 /* Assert USB3 PHY reset */ 36 setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); 37 38 /* Assert USB2 PHY reset */ 39 setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); 40 41 mdelay(100); 42 43 /* Clear USB3 PHY reset */ 44 clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); 45 46 /* Clear USB2 PHY reset */ 47 clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); 48 } 49 50 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) 51 { 52 /* Before Resetting PHY, put Core in Reset */ 53 setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); 54 55 /* reset USB3 phy - if required */ 56 dwc3_phy_reset(dwc3_reg); 57 58 mdelay(100); 59 60 /* After PHYs are stable we can take Core out of reset state */ 61 clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); 62 } 63 64 int dwc3_core_init(struct dwc3 *dwc3_reg) 65 { 66 u32 reg; 67 u32 revision; 68 unsigned int dwc3_hwparams1; 69 70 revision = readl(&dwc3_reg->g_snpsid); 71 /* This should read as U3 followed by revision number */ 72 if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) { 73 puts("this is not a DesignWare USB3 DRD Core\n"); 74 return -1; 75 } 76 77 dwc3_core_soft_reset(dwc3_reg); 78 79 dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1); 80 81 reg = readl(&dwc3_reg->g_ctl); 82 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 83 reg &= ~DWC3_GCTL_DISSCRAMBLE; 84 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) { 85 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 86 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 87 break; 88 default: 89 debug("No power optimization available\n"); 90 } 91 92 /* 93 * WORKAROUND: DWC3 revisions <1.90a have a bug 94 * where the device can fail to connect at SuperSpeed 95 * and falls back to high-speed mode which causes 96 * the device to enter a Connect/Disconnect loop 97 */ 98 if ((revision & DWC3_REVISION_MASK) < 0x190a) 99 reg |= DWC3_GCTL_U2RSTECN; 100 101 writel(reg, &dwc3_reg->g_ctl); 102 103 return 0; 104 } 105 106 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val) 107 { 108 setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL | 109 GFLADJ_30MHZ(val)); 110 } 111 112 #if CONFIG_IS_ENABLED(DM_USB) 113 static int xhci_dwc3_setup_phy(struct udevice *dev) 114 { 115 struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); 116 int i, ret, count; 117 118 /* Return if no phy declared */ 119 if (!dev_read_prop(dev, "phys", NULL)) 120 return 0; 121 122 count = dev_count_phandle_with_args(dev, "phys", "#phy-cells"); 123 if (count <= 0) 124 return count; 125 126 plat->usb_phys = devm_kcalloc(dev, count, sizeof(struct phy), 127 GFP_KERNEL); 128 if (!plat->usb_phys) 129 return -ENOMEM; 130 131 for (i = 0; i < count; i++) { 132 ret = generic_phy_get_by_index(dev, i, &plat->usb_phys[i]); 133 if (ret && ret != -ENOENT) { 134 pr_err("Failed to get USB PHY%d for %s\n", 135 i, dev->name); 136 return ret; 137 } 138 139 ++plat->num_phys; 140 } 141 142 for (i = 0; i < plat->num_phys; i++) { 143 ret = generic_phy_init(&plat->usb_phys[i]); 144 if (ret) { 145 pr_err("Can't init USB PHY%d for %s\n", 146 i, dev->name); 147 goto phys_init_err; 148 } 149 } 150 151 for (i = 0; i < plat->num_phys; i++) { 152 ret = generic_phy_power_on(&plat->usb_phys[i]); 153 if (ret) { 154 pr_err("Can't power USB PHY%d for %s\n", 155 i, dev->name); 156 goto phys_poweron_err; 157 } 158 } 159 160 return 0; 161 162 phys_poweron_err: 163 for (; i >= 0; i--) 164 generic_phy_power_off(&plat->usb_phys[i]); 165 166 for (i = 0; i < plat->num_phys; i++) 167 generic_phy_exit(&plat->usb_phys[i]); 168 169 return ret; 170 171 phys_init_err: 172 for (; i >= 0; i--) 173 generic_phy_exit(&plat->usb_phys[i]); 174 175 return ret; 176 } 177 178 static int xhci_dwc3_shutdown_phy(struct udevice *dev) 179 { 180 struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); 181 int i, ret; 182 183 for (i = 0; i < plat->num_phys; i++) { 184 if (!generic_phy_valid(&plat->usb_phys[i])) 185 continue; 186 187 ret = generic_phy_power_off(&plat->usb_phys[i]); 188 ret |= generic_phy_exit(&plat->usb_phys[i]); 189 if (ret) { 190 pr_err("Can't shutdown USB PHY%d for %s\n", 191 i, dev->name); 192 } 193 } 194 195 return 0; 196 } 197 198 static int xhci_dwc3_probe(struct udevice *dev) 199 { 200 struct xhci_hcor *hcor; 201 struct xhci_hccr *hccr; 202 struct dwc3 *dwc3_reg; 203 enum usb_dr_mode dr_mode; 204 int ret; 205 206 hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev)); 207 hcor = (struct xhci_hcor *)((uintptr_t)hccr + 208 HC_LENGTH(xhci_readl(&(hccr)->cr_capbase))); 209 210 ret = xhci_dwc3_setup_phy(dev); 211 if (ret) 212 return ret; 213 214 dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET); 215 216 dwc3_core_init(dwc3_reg); 217 218 dr_mode = usb_get_dr_mode(dev_of_offset(dev)); 219 if (dr_mode == USB_DR_MODE_UNKNOWN) 220 /* by default set dual role mode to HOST */ 221 dr_mode = USB_DR_MODE_HOST; 222 223 dwc3_set_mode(dwc3_reg, dr_mode); 224 225 return xhci_register(dev, hccr, hcor); 226 } 227 228 static int xhci_dwc3_remove(struct udevice *dev) 229 { 230 xhci_dwc3_shutdown_phy(dev); 231 232 return xhci_deregister(dev); 233 } 234 235 static const struct udevice_id xhci_dwc3_ids[] = { 236 { .compatible = "snps,dwc3" }, 237 { } 238 }; 239 240 U_BOOT_DRIVER(xhci_dwc3) = { 241 .name = "xhci-dwc3", 242 .id = UCLASS_USB, 243 .of_match = xhci_dwc3_ids, 244 .probe = xhci_dwc3_probe, 245 .remove = xhci_dwc3_remove, 246 .ops = &xhci_usb_ops, 247 .priv_auto_alloc_size = sizeof(struct xhci_ctrl), 248 .platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata), 249 .flags = DM_FLAG_ALLOC_PRIV_DMA, 250 }; 251 #endif 252