1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2015 Freescale Semiconductor, Inc. 4 * 5 * DWC3 controller driver 6 * 7 * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com> 8 */ 9 10 #include <common.h> 11 #include <dm.h> 12 #include <fdtdec.h> 13 #include <generic-phy.h> 14 #include <usb.h> 15 #include <dwc3-uboot.h> 16 17 #include "xhci.h" 18 #include <asm/io.h> 19 #include <linux/usb/dwc3.h> 20 #include <linux/usb/otg.h> 21 22 struct xhci_dwc3_platdata { 23 struct phy *usb_phys; 24 int num_phys; 25 }; 26 27 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) 28 { 29 clrsetbits_le32(&dwc3_reg->g_ctl, 30 DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG), 31 DWC3_GCTL_PRTCAPDIR(mode)); 32 } 33 34 static void dwc3_phy_reset(struct dwc3 *dwc3_reg) 35 { 36 /* Assert USB3 PHY reset */ 37 setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); 38 39 /* Assert USB2 PHY reset */ 40 setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); 41 42 mdelay(100); 43 44 /* Clear USB3 PHY reset */ 45 clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); 46 47 /* Clear USB2 PHY reset */ 48 clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); 49 } 50 51 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) 52 { 53 /* Before Resetting PHY, put Core in Reset */ 54 setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); 55 56 /* reset USB3 phy - if required */ 57 dwc3_phy_reset(dwc3_reg); 58 59 mdelay(100); 60 61 /* After PHYs are stable we can take Core out of reset state */ 62 clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); 63 } 64 65 int dwc3_core_init(struct dwc3 *dwc3_reg) 66 { 67 u32 reg; 68 u32 revision; 69 unsigned int dwc3_hwparams1; 70 71 revision = readl(&dwc3_reg->g_snpsid); 72 /* This should read as U3 followed by revision number */ 73 if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) { 74 puts("this is not a DesignWare USB3 DRD Core\n"); 75 return -1; 76 } 77 78 dwc3_core_soft_reset(dwc3_reg); 79 80 dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1); 81 82 reg = readl(&dwc3_reg->g_ctl); 83 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 84 reg &= ~DWC3_GCTL_DISSCRAMBLE; 85 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) { 86 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 87 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 88 break; 89 default: 90 debug("No power optimization available\n"); 91 } 92 93 /* 94 * WORKAROUND: DWC3 revisions <1.90a have a bug 95 * where the device can fail to connect at SuperSpeed 96 * and falls back to high-speed mode which causes 97 * the device to enter a Connect/Disconnect loop 98 */ 99 if ((revision & DWC3_REVISION_MASK) < 0x190a) 100 reg |= DWC3_GCTL_U2RSTECN; 101 102 writel(reg, &dwc3_reg->g_ctl); 103 104 return 0; 105 } 106 107 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val) 108 { 109 setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL | 110 GFLADJ_30MHZ(val)); 111 } 112 113 #if CONFIG_IS_ENABLED(DM_USB) 114 static int xhci_dwc3_probe(struct udevice *dev) 115 { 116 struct xhci_hcor *hcor; 117 struct xhci_hccr *hccr; 118 struct dwc3 *dwc3_reg; 119 enum usb_dr_mode dr_mode; 120 struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); 121 int ret; 122 123 hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev)); 124 hcor = (struct xhci_hcor *)((uintptr_t)hccr + 125 HC_LENGTH(xhci_readl(&(hccr)->cr_capbase))); 126 127 ret = dwc3_setup_phy(dev, &plat->usb_phys, &plat->num_phys); 128 if (ret && (ret != -ENOTSUPP)) 129 return ret; 130 131 dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET); 132 133 dwc3_core_init(dwc3_reg); 134 135 dr_mode = usb_get_dr_mode(dev_of_offset(dev)); 136 if (dr_mode == USB_DR_MODE_UNKNOWN) 137 /* by default set dual role mode to HOST */ 138 dr_mode = USB_DR_MODE_HOST; 139 140 dwc3_set_mode(dwc3_reg, dr_mode); 141 142 return xhci_register(dev, hccr, hcor); 143 } 144 145 static int xhci_dwc3_remove(struct udevice *dev) 146 { 147 struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); 148 149 dwc3_shutdown_phy(dev, plat->usb_phys, plat->num_phys); 150 151 return xhci_deregister(dev); 152 } 153 154 static const struct udevice_id xhci_dwc3_ids[] = { 155 { .compatible = "snps,dwc3" }, 156 { } 157 }; 158 159 U_BOOT_DRIVER(xhci_dwc3) = { 160 .name = "xhci-dwc3", 161 .id = UCLASS_USB, 162 .of_match = xhci_dwc3_ids, 163 .probe = xhci_dwc3_probe, 164 .remove = xhci_dwc3_remove, 165 .ops = &xhci_usb_ops, 166 .priv_auto_alloc_size = sizeof(struct xhci_ctrl), 167 .platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata), 168 .flags = DM_FLAG_ALLOC_PRIV_DMA, 169 }; 170 #endif 171