1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * DWC3 controller driver 5 * 6 * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <dm.h> 13 #include <fdtdec.h> 14 #include <generic-phy.h> 15 #include <usb.h> 16 17 #include "xhci.h" 18 #include <asm/io.h> 19 #include <linux/usb/dwc3.h> 20 #include <linux/usb/otg.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 struct xhci_dwc3_platdata { 25 struct phy usb_phy; 26 struct phy usb3_phy; 27 }; 28 29 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) 30 { 31 clrsetbits_le32(&dwc3_reg->g_ctl, 32 DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG), 33 DWC3_GCTL_PRTCAPDIR(mode)); 34 } 35 36 static void dwc3_phy_reset(struct dwc3 *dwc3_reg) 37 { 38 /* Assert USB3 PHY reset */ 39 setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); 40 41 /* Assert USB2 PHY reset */ 42 setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); 43 44 mdelay(100); 45 46 /* Clear USB3 PHY reset */ 47 clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); 48 49 /* Clear USB2 PHY reset */ 50 clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); 51 } 52 53 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) 54 { 55 /* Before Resetting PHY, put Core in Reset */ 56 setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); 57 58 /* reset USB3 phy - if required */ 59 dwc3_phy_reset(dwc3_reg); 60 61 mdelay(100); 62 63 /* After PHYs are stable we can take Core out of reset state */ 64 clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); 65 } 66 67 int dwc3_core_init(struct dwc3 *dwc3_reg) 68 { 69 u32 reg; 70 u32 revision; 71 unsigned int dwc3_hwparams1; 72 73 revision = readl(&dwc3_reg->g_snpsid); 74 /* This should read as U3 followed by revision number */ 75 if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) { 76 puts("this is not a DesignWare USB3 DRD Core\n"); 77 return -1; 78 } 79 80 dwc3_core_soft_reset(dwc3_reg); 81 82 dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1); 83 84 reg = readl(&dwc3_reg->g_ctl); 85 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 86 reg &= ~DWC3_GCTL_DISSCRAMBLE; 87 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) { 88 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 89 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 90 break; 91 default: 92 debug("No power optimization available\n"); 93 } 94 95 /* 96 * WORKAROUND: DWC3 revisions <1.90a have a bug 97 * where the device can fail to connect at SuperSpeed 98 * and falls back to high-speed mode which causes 99 * the device to enter a Connect/Disconnect loop 100 */ 101 if ((revision & DWC3_REVISION_MASK) < 0x190a) 102 reg |= DWC3_GCTL_U2RSTECN; 103 104 writel(reg, &dwc3_reg->g_ctl); 105 106 return 0; 107 } 108 109 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val) 110 { 111 setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL | 112 GFLADJ_30MHZ(val)); 113 } 114 115 #ifdef CONFIG_DM_USB 116 static int xhci_dwc3_setup_phy(struct udevice *dev, int index, struct phy *phy) 117 { 118 int ret = 0; 119 120 ret = generic_phy_get_by_index(dev, index, phy); 121 if (ret) { 122 if (ret != -ENOENT) { 123 pr_err("Failed to get USB PHY for %s\n", dev->name); 124 return ret; 125 } 126 } else { 127 ret = generic_phy_init(phy); 128 if (ret) { 129 pr_err("Can't init USB PHY for %s\n", dev->name); 130 return ret; 131 } 132 ret = generic_phy_power_on(phy); 133 if (ret) { 134 pr_err("Can't power on USB PHY for %s\n", dev->name); 135 generic_phy_exit(phy); 136 return ret; 137 } 138 } 139 140 return 0; 141 } 142 143 static int xhci_dwc3_shutdown_phy(struct phy *phy) 144 { 145 int ret = 0; 146 147 if (generic_phy_valid(phy)) { 148 ret = generic_phy_power_off(phy); 149 if (ret) 150 return ret; 151 152 ret = generic_phy_exit(phy); 153 if (ret) 154 return ret; 155 } 156 157 return 0; 158 } 159 160 static int xhci_dwc3_probe(struct udevice *dev) 161 { 162 struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); 163 struct xhci_hcor *hcor; 164 struct xhci_hccr *hccr; 165 struct dwc3 *dwc3_reg; 166 enum usb_dr_mode dr_mode; 167 int ret; 168 169 hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev)); 170 hcor = (struct xhci_hcor *)((uintptr_t)hccr + 171 HC_LENGTH(xhci_readl(&(hccr)->cr_capbase))); 172 173 ret = xhci_dwc3_setup_phy(dev, 0, &plat->usb_phy); 174 if (ret) { 175 pr_err("Failed to setup USB PHY for %s\n", dev->name); 176 return ret; 177 } 178 179 ret = xhci_dwc3_setup_phy(dev, 1, &plat->usb3_phy); 180 if (ret) { 181 pr_err("Failed to setup USB3 PHY for %s\n", dev->name); 182 xhci_dwc3_shutdown_phy(&plat->usb_phy); 183 return ret; 184 } 185 186 dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET); 187 188 dwc3_core_init(dwc3_reg); 189 190 dr_mode = usb_get_dr_mode(dev_of_offset(dev)); 191 if (dr_mode == USB_DR_MODE_UNKNOWN) 192 /* by default set dual role mode to HOST */ 193 dr_mode = USB_DR_MODE_HOST; 194 195 dwc3_set_mode(dwc3_reg, dr_mode); 196 197 return xhci_register(dev, hccr, hcor); 198 } 199 200 static int xhci_dwc3_remove(struct udevice *dev) 201 { 202 struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); 203 int ret; 204 205 ret = xhci_dwc3_shutdown_phy(&plat->usb_phy); 206 if (ret) 207 pr_err("Can't shutdown USB PHY for %s\n", dev->name); 208 209 ret = xhci_dwc3_shutdown_phy(&plat->usb3_phy); 210 if (ret) 211 pr_err("Can't shutdown USB3 PHY for %s\n", dev->name); 212 213 return xhci_deregister(dev); 214 } 215 216 static const struct udevice_id xhci_dwc3_ids[] = { 217 { .compatible = "snps,dwc3" }, 218 { } 219 }; 220 221 U_BOOT_DRIVER(xhci_dwc3) = { 222 .name = "xhci-dwc3", 223 .id = UCLASS_USB, 224 .of_match = xhci_dwc3_ids, 225 .probe = xhci_dwc3_probe, 226 .remove = xhci_dwc3_remove, 227 .ops = &xhci_usb_ops, 228 .priv_auto_alloc_size = sizeof(struct xhci_ctrl), 229 .platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata), 230 .flags = DM_FLAG_ALLOC_PRIV_DMA, 231 }; 232 #endif 233