xref: /openbmc/u-boot/drivers/usb/host/xhci-dwc3.c (revision 4de512018ba7d57f1672be21c7459281f7c97514)
1 /*
2  * Copyright 2015 Freescale Semiconductor, Inc.
3  *
4  * DWC3 controller driver
5  *
6  * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10 
11 #include <common.h>
12 #include <dm.h>
13 #include <fdtdec.h>
14 #include <generic-phy.h>
15 #include <usb.h>
16 
17 #include "xhci.h"
18 #include <asm/io.h>
19 #include <linux/usb/dwc3.h>
20 #include <linux/usb/otg.h>
21 
22 DECLARE_GLOBAL_DATA_PTR;
23 
24 struct xhci_dwc3_platdata {
25 	struct phy usb_phy;
26 };
27 
28 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
29 {
30 	clrsetbits_le32(&dwc3_reg->g_ctl,
31 			DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
32 			DWC3_GCTL_PRTCAPDIR(mode));
33 }
34 
35 static void dwc3_phy_reset(struct dwc3 *dwc3_reg)
36 {
37 	/* Assert USB3 PHY reset */
38 	setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
39 
40 	/* Assert USB2 PHY reset */
41 	setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
42 
43 	mdelay(100);
44 
45 	/* Clear USB3 PHY reset */
46 	clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
47 
48 	/* Clear USB2 PHY reset */
49 	clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
50 }
51 
52 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
53 {
54 	/* Before Resetting PHY, put Core in Reset */
55 	setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
56 
57 	/* reset USB3 phy - if required */
58 	dwc3_phy_reset(dwc3_reg);
59 
60 	mdelay(100);
61 
62 	/* After PHYs are stable we can take Core out of reset state */
63 	clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
64 }
65 
66 int dwc3_core_init(struct dwc3 *dwc3_reg)
67 {
68 	u32 reg;
69 	u32 revision;
70 	unsigned int dwc3_hwparams1;
71 
72 	revision = readl(&dwc3_reg->g_snpsid);
73 	/* This should read as U3 followed by revision number */
74 	if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
75 		puts("this is not a DesignWare USB3 DRD Core\n");
76 		return -1;
77 	}
78 
79 	dwc3_core_soft_reset(dwc3_reg);
80 
81 	dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
82 
83 	reg = readl(&dwc3_reg->g_ctl);
84 	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
85 	reg &= ~DWC3_GCTL_DISSCRAMBLE;
86 	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
87 	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
88 		reg &= ~DWC3_GCTL_DSBLCLKGTNG;
89 		break;
90 	default:
91 		debug("No power optimization available\n");
92 	}
93 
94 	/*
95 	 * WORKAROUND: DWC3 revisions <1.90a have a bug
96 	 * where the device can fail to connect at SuperSpeed
97 	 * and falls back to high-speed mode which causes
98 	 * the device to enter a Connect/Disconnect loop
99 	 */
100 	if ((revision & DWC3_REVISION_MASK) < 0x190a)
101 		reg |= DWC3_GCTL_U2RSTECN;
102 
103 	writel(reg, &dwc3_reg->g_ctl);
104 
105 	return 0;
106 }
107 
108 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
109 {
110 	setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
111 			GFLADJ_30MHZ(val));
112 }
113 
114 static int xhci_dwc3_probe(struct udevice *dev)
115 {
116 	struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
117 	struct xhci_hcor *hcor;
118 	struct xhci_hccr *hccr;
119 	struct dwc3 *dwc3_reg;
120 	enum usb_dr_mode dr_mode;
121 	int ret;
122 
123 	hccr = (struct xhci_hccr *)devfdt_get_addr(dev);
124 	hcor = (struct xhci_hcor *)((phys_addr_t)hccr +
125 			HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
126 
127 	ret = generic_phy_get_by_index(dev, 0, &plat->usb_phy);
128 	if (ret) {
129 		if (ret != -ENOENT) {
130 			error("Failed to get USB PHY for %s\n", dev->name);
131 			return ret;
132 		}
133 	} else {
134 		ret = generic_phy_init(&plat->usb_phy);
135 		if (ret) {
136 			error("Can't init USB PHY for %s\n", dev->name);
137 			return ret;
138 		}
139 	}
140 
141 	dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
142 
143 	dwc3_core_init(dwc3_reg);
144 
145 	dr_mode = usb_get_dr_mode(dev_of_offset(dev));
146 	if (dr_mode == USB_DR_MODE_UNKNOWN)
147 		/* by default set dual role mode to HOST */
148 		dr_mode = USB_DR_MODE_HOST;
149 
150 	dwc3_set_mode(dwc3_reg, dr_mode);
151 
152 	return xhci_register(dev, hccr, hcor);
153 }
154 
155 static int xhci_dwc3_remove(struct udevice *dev)
156 {
157 	struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
158 	int ret;
159 
160 	if (generic_phy_valid(&plat->usb_phy)) {
161 		ret = generic_phy_exit(&plat->usb_phy);
162 		if (ret) {
163 			error("Can't deinit USB PHY for %s\n", dev->name);
164 			return ret;
165 		}
166 	}
167 
168 	return xhci_deregister(dev);
169 }
170 
171 static const struct udevice_id xhci_dwc3_ids[] = {
172 	{ .compatible = "snps,dwc3" },
173 	{ }
174 };
175 
176 U_BOOT_DRIVER(xhci_dwc3) = {
177 	.name = "xhci-dwc3",
178 	.id = UCLASS_USB,
179 	.of_match = xhci_dwc3_ids,
180 	.probe = xhci_dwc3_probe,
181 	.remove = xhci_dwc3_remove,
182 	.ops = &xhci_usb_ops,
183 	.priv_auto_alloc_size = sizeof(struct xhci_ctrl),
184 	.platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata),
185 	.flags = DM_FLAG_ALLOC_PRIV_DMA,
186 };
187