1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * DWC3 controller driver 5 * 6 * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <dm.h> 13 #include <fdtdec.h> 14 #include <generic-phy.h> 15 #include <usb.h> 16 17 #include "xhci.h" 18 #include <asm/io.h> 19 #include <linux/usb/dwc3.h> 20 #include <linux/usb/otg.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 struct xhci_dwc3_platdata { 25 struct phy *usb_phys; 26 int num_phys; 27 }; 28 29 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) 30 { 31 clrsetbits_le32(&dwc3_reg->g_ctl, 32 DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG), 33 DWC3_GCTL_PRTCAPDIR(mode)); 34 } 35 36 static void dwc3_phy_reset(struct dwc3 *dwc3_reg) 37 { 38 /* Assert USB3 PHY reset */ 39 setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); 40 41 /* Assert USB2 PHY reset */ 42 setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); 43 44 mdelay(100); 45 46 /* Clear USB3 PHY reset */ 47 clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); 48 49 /* Clear USB2 PHY reset */ 50 clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); 51 } 52 53 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) 54 { 55 /* Before Resetting PHY, put Core in Reset */ 56 setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); 57 58 /* reset USB3 phy - if required */ 59 dwc3_phy_reset(dwc3_reg); 60 61 mdelay(100); 62 63 /* After PHYs are stable we can take Core out of reset state */ 64 clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); 65 } 66 67 int dwc3_core_init(struct dwc3 *dwc3_reg) 68 { 69 u32 reg; 70 u32 revision; 71 unsigned int dwc3_hwparams1; 72 73 revision = readl(&dwc3_reg->g_snpsid); 74 /* This should read as U3 followed by revision number */ 75 if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) { 76 puts("this is not a DesignWare USB3 DRD Core\n"); 77 return -1; 78 } 79 80 dwc3_core_soft_reset(dwc3_reg); 81 82 dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1); 83 84 reg = readl(&dwc3_reg->g_ctl); 85 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 86 reg &= ~DWC3_GCTL_DISSCRAMBLE; 87 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) { 88 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 89 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 90 break; 91 default: 92 debug("No power optimization available\n"); 93 } 94 95 /* 96 * WORKAROUND: DWC3 revisions <1.90a have a bug 97 * where the device can fail to connect at SuperSpeed 98 * and falls back to high-speed mode which causes 99 * the device to enter a Connect/Disconnect loop 100 */ 101 if ((revision & DWC3_REVISION_MASK) < 0x190a) 102 reg |= DWC3_GCTL_U2RSTECN; 103 104 writel(reg, &dwc3_reg->g_ctl); 105 106 return 0; 107 } 108 109 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val) 110 { 111 setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL | 112 GFLADJ_30MHZ(val)); 113 } 114 115 #ifdef CONFIG_DM_USB 116 static int xhci_dwc3_setup_phy(struct udevice *dev, int count) 117 { 118 struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); 119 int i, ret; 120 121 if (!count) 122 return 0; 123 124 plat->usb_phys = devm_kcalloc(dev, count, sizeof(struct phy), 125 GFP_KERNEL); 126 if (!plat->usb_phys) 127 return -ENOMEM; 128 129 for (i = 0; i < count; i++) { 130 ret = generic_phy_get_by_index(dev, i, &plat->usb_phys[i]); 131 if (ret && ret != -ENOENT) { 132 pr_err("Failed to get USB PHY%d for %s\n", 133 i, dev->name); 134 return ret; 135 } 136 137 ++plat->num_phys; 138 } 139 140 for (i = 0; i < plat->num_phys; i++) { 141 ret = generic_phy_init(&plat->usb_phys[i]); 142 if (ret) { 143 pr_err("Can't init USB PHY%d for %s\n", 144 i, dev->name); 145 goto phys_init_err; 146 } 147 } 148 149 for (i = 0; i < plat->num_phys; i++) { 150 ret = generic_phy_power_on(&plat->usb_phys[i]); 151 if (ret) { 152 pr_err("Can't power USB PHY%d for %s\n", 153 i, dev->name); 154 goto phys_poweron_err; 155 } 156 } 157 158 return 0; 159 160 161 phys_poweron_err: 162 for (; i >= 0; i--) 163 generic_phy_power_off(&plat->usb_phys[i]); 164 165 for (i = 0; i < plat->num_phys; i++) 166 generic_phy_exit(&plat->usb_phys[i]); 167 168 return ret; 169 170 phys_init_err: 171 for (; i >= 0; i--) 172 generic_phy_exit(&plat->usb_phys[i]); 173 174 return ret; 175 } 176 177 static int xhci_dwc3_shutdown_phy(struct udevice *dev) 178 { 179 struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); 180 int i, ret; 181 182 for (i = 0; i < plat->num_phys; i++) { 183 if (!generic_phy_valid(&plat->usb_phys[i])) 184 continue; 185 186 ret = generic_phy_power_off(&plat->usb_phys[i]); 187 ret |= generic_phy_exit(&plat->usb_phys[i]); 188 if (ret) { 189 pr_err("Can't shutdown USB PHY%d for %s\n", 190 i, dev->name); 191 } 192 } 193 194 return 0; 195 } 196 197 static int xhci_dwc3_probe(struct udevice *dev) 198 { 199 struct xhci_hcor *hcor; 200 struct xhci_hccr *hccr; 201 struct dwc3 *dwc3_reg; 202 enum usb_dr_mode dr_mode; 203 int ret; 204 205 hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev)); 206 hcor = (struct xhci_hcor *)((uintptr_t)hccr + 207 HC_LENGTH(xhci_readl(&(hccr)->cr_capbase))); 208 209 ret = xhci_dwc3_setup_phy(dev, dev_count_phandle_with_args( 210 dev, "phys", "#phy-cells")); 211 if (ret) 212 return ret; 213 214 dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET); 215 216 dwc3_core_init(dwc3_reg); 217 218 dr_mode = usb_get_dr_mode(dev_of_offset(dev)); 219 if (dr_mode == USB_DR_MODE_UNKNOWN) 220 /* by default set dual role mode to HOST */ 221 dr_mode = USB_DR_MODE_HOST; 222 223 dwc3_set_mode(dwc3_reg, dr_mode); 224 225 return xhci_register(dev, hccr, hcor); 226 } 227 228 static int xhci_dwc3_remove(struct udevice *dev) 229 { 230 xhci_dwc3_shutdown_phy(dev); 231 232 return xhci_deregister(dev); 233 } 234 235 static const struct udevice_id xhci_dwc3_ids[] = { 236 { .compatible = "snps,dwc3" }, 237 { } 238 }; 239 240 U_BOOT_DRIVER(xhci_dwc3) = { 241 .name = "xhci-dwc3", 242 .id = UCLASS_USB, 243 .of_match = xhci_dwc3_ids, 244 .probe = xhci_dwc3_probe, 245 .remove = xhci_dwc3_remove, 246 .ops = &xhci_usb_ops, 247 .priv_auto_alloc_size = sizeof(struct xhci_ctrl), 248 .platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata), 249 .flags = DM_FLAG_ALLOC_PRIV_DMA, 250 }; 251 #endif 252