1 /* 2 * (C) Copyright 2012 3 * eInfochips Ltd. <www.einfochips.com> 4 * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com> 5 * 6 * (C) Copyright 2009 7 * Marvell Semiconductor <www.marvell.com> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 25 * MA 02110-1301 USA 26 */ 27 28 #include <common.h> 29 #include <asm/io.h> 30 #include <usb.h> 31 #include <asm/arch/cpu.h> 32 #include <asm/arch/armada100.h> 33 #include <asm/arch/utmi-armada100.h> 34 35 static int utmi_phy_init(void) 36 { 37 struct armd1usb_phy_reg *phy_regs = 38 (struct armd1usb_phy_reg *)UTMI_PHY_BASE; 39 int timeout; 40 41 setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP); 42 udelay(1000); 43 setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP); 44 45 clrbits_le32(&phy_regs->utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK); 46 setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER); 47 48 setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL); 49 50 /* Calibrate pll */ 51 timeout = 10000; 52 while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0)) 53 ; 54 if (!timeout) 55 return -1; 56 57 udelay(200); 58 setbits_le32(&phy_regs->utmi_pll, VCOCAL_START); 59 udelay(400); 60 clrbits_le32(&phy_regs->utmi_pll, VCOCAL_START); 61 62 udelay(200); 63 setbits_le32(&phy_regs->utmi_tx, RCAL_START); 64 udelay(400); 65 clrbits_le32(&phy_regs->utmi_tx, RCAL_START); 66 67 timeout = 10000; 68 while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0)) 69 ; 70 if (!timeout) 71 return -1; 72 73 return 0; 74 } 75 76 /* 77 * Initialize USB host controller's UTMI Physical interface 78 */ 79 int utmi_init(void) 80 { 81 struct armd1mpmu_registers *mpmu_regs = 82 (struct armd1mpmu_registers *)ARMD1_MPMU_BASE; 83 84 struct armd1apmu_registers *apmu_regs = 85 (struct armd1apmu_registers *)ARMD1_APMU_BASE; 86 87 /* Turn on 26Mhz ref clock for UTMI PLL */ 88 setbits_le32(&mpmu_regs->acgr, APB2_26M_EN | AP_26M); 89 90 /* USB Clock reset */ 91 writel(USB_SPH_AXICLK_EN, &apmu_regs->usbcrc); 92 writel(USB_SPH_AXICLK_EN | USB_SPH_AXI_RST, &apmu_regs->usbcrc); 93 94 /* Initialize UTMI transceiver */ 95 return utmi_phy_init(); 96 } 97