1 /* 2 * R8A66597 HCD (Host Controller Driver) for u-boot 3 * 4 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #ifndef __R8A66597_H__ 10 #define __R8A66597_H__ 11 12 #define SYSCFG0 0x00 13 #define SYSCFG1 0x02 14 #define SYSSTS0 0x04 15 #define SYSSTS1 0x06 16 #define DVSTCTR0 0x08 17 #define DVSTCTR1 0x0A 18 #define TESTMODE 0x0C 19 #define PINCFG 0x0E 20 #define DMA0CFG 0x10 21 #define DMA1CFG 0x12 22 #define CFIFO 0x14 23 #define D0FIFO 0x18 24 #define D1FIFO 0x1C 25 #define CFIFOSEL 0x20 26 #define CFIFOCTR 0x22 27 #define CFIFOSIE 0x24 28 #define D0FIFOSEL 0x28 29 #define D0FIFOCTR 0x2A 30 #define D1FIFOSEL 0x2C 31 #define D1FIFOCTR 0x2E 32 #define INTENB0 0x30 33 #define INTENB1 0x32 34 #define INTENB2 0x34 35 #define BRDYENB 0x36 36 #define NRDYENB 0x38 37 #define BEMPENB 0x3A 38 #define SOFCFG 0x3C 39 #define INTSTS0 0x40 40 #define INTSTS1 0x42 41 #define INTSTS2 0x44 42 #define BRDYSTS 0x46 43 #define NRDYSTS 0x48 44 #define BEMPSTS 0x4A 45 #define FRMNUM 0x4C 46 #define UFRMNUM 0x4E 47 #define USBADDR 0x50 48 #define USBREQ 0x54 49 #define USBVAL 0x56 50 #define USBINDX 0x58 51 #define USBLENG 0x5A 52 #define DCPCFG 0x5C 53 #define DCPMAXP 0x5E 54 #define DCPCTR 0x60 55 #define PIPESEL 0x64 56 #define PIPECFG 0x68 57 #define PIPEBUF 0x6A 58 #define PIPEMAXP 0x6C 59 #define PIPEPERI 0x6E 60 #define PIPE1CTR 0x70 61 #define PIPE2CTR 0x72 62 #define PIPE3CTR 0x74 63 #define PIPE4CTR 0x76 64 #define PIPE5CTR 0x78 65 #define PIPE6CTR 0x7A 66 #define PIPE7CTR 0x7C 67 #define PIPE8CTR 0x7E 68 #define PIPE9CTR 0x80 69 #define PIPE1TRE 0x90 70 #define PIPE1TRN 0x92 71 #define PIPE2TRE 0x94 72 #define PIPE2TRN 0x96 73 #define PIPE3TRE 0x98 74 #define PIPE3TRN 0x9A 75 #define PIPE4TRE 0x9C 76 #define PIPE4TRN 0x9E 77 #define PIPE5TRE 0xA0 78 #define PIPE5TRN 0xA2 79 #define DEVADD0 0xD0 80 #define DEVADD1 0xD2 81 #define DEVADD2 0xD4 82 #define DEVADD3 0xD6 83 #define DEVADD4 0xD8 84 #define DEVADD5 0xDA 85 #define DEVADD6 0xDC 86 #define DEVADD7 0xDE 87 #define DEVADD8 0xE0 88 #define DEVADD9 0xE2 89 #define DEVADDA 0xE4 90 #define SUSPMODE0 0x102 /* RZ/A only */ 91 92 /* System Configuration Control Register */ 93 #if !defined(CONFIG_RZA_USB) 94 #define XTAL 0xC000 /* b15-14: Crystal selection */ 95 #define XTAL48 0x8000 /* 48MHz */ 96 #define XTAL24 0x4000 /* 24MHz */ 97 #define XTAL12 0x0000 /* 12MHz */ 98 #define XCKE 0x2000 /* b13: External clock enable */ 99 #define PLLC 0x0800 /* b11: PLL control */ 100 #define SCKE 0x0400 /* b10: USB clock enable */ 101 #define PCSDIS 0x0200 /* b9: not CS wakeup */ 102 #define LPSME 0x0100 /* b8: Low power sleep mode */ 103 #endif 104 #define HSE 0x0080 /* b7: Hi-speed enable */ 105 #define DCFM 0x0040 /* b6: Controller function select */ 106 #define DRPD 0x0020 /* b5: D+/- pull down control */ 107 #define DPRPU 0x0010 /* b4: D+ pull up control */ 108 #if defined(CONFIG_RZA_USB) 109 #define XTAL 0x0004 /* b2: Crystal selection */ 110 #define XTAL12 0x0004 /* 12MHz */ 111 #define XTAL48 0x0000 /* 48MHz */ 112 #define UPLLE 0x0002 /* b1: internal PLL control */ 113 #endif 114 #define USBE 0x0001 /* b0: USB module operation enable */ 115 116 /* System Configuration Status Register */ 117 #define OVCBIT 0x8000 /* b15-14: Over-current bit */ 118 #define OVCMON 0xC000 /* b15-14: Over-current monitor */ 119 #define SOFEA 0x0020 /* b5: SOF monitor */ 120 #define IDMON 0x0004 /* b3: ID-pin monitor */ 121 #define LNST 0x0003 /* b1-0: D+, D- line status */ 122 #define SE1 0x0003 /* SE1 */ 123 #define FS_KSTS 0x0002 /* Full-Speed K State */ 124 #define FS_JSTS 0x0001 /* Full-Speed J State */ 125 #define LS_JSTS 0x0002 /* Low-Speed J State */ 126 #define LS_KSTS 0x0001 /* Low-Speed K State */ 127 #define SE0 0x0000 /* SE0 */ 128 129 /* Device State Control Register */ 130 #define EXTLP0 0x0400 /* b10: External port */ 131 #define VBOUT 0x0200 /* b9: VBUS output */ 132 #define WKUP 0x0100 /* b8: Remote wakeup */ 133 #define RWUPE 0x0080 /* b7: Remote wakeup sense */ 134 #define USBRST 0x0040 /* b6: USB reset enable */ 135 #define RESUME 0x0020 /* b5: Resume enable */ 136 #define UACT 0x0010 /* b4: USB bus enable */ 137 #define RHST 0x0007 /* b1-0: Reset handshake status */ 138 #define HSPROC 0x0004 /* HS handshake is processing */ 139 #define HSMODE 0x0003 /* Hi-Speed mode */ 140 #define FSMODE 0x0002 /* Full-Speed mode */ 141 #define LSMODE 0x0001 /* Low-Speed mode */ 142 #define UNDECID 0x0000 /* Undecided */ 143 144 /* Test Mode Register */ 145 #define UTST 0x000F /* b3-0: Test select */ 146 #define H_TST_PACKET 0x000C /* HOST TEST Packet */ 147 #define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */ 148 #define H_TST_K 0x000A /* HOST TEST K */ 149 #define H_TST_J 0x0009 /* HOST TEST J */ 150 #define H_TST_NORMAL 0x0000 /* HOST Normal Mode */ 151 #define P_TST_PACKET 0x0004 /* PERI TEST Packet */ 152 #define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */ 153 #define P_TST_K 0x0002 /* PERI TEST K */ 154 #define P_TST_J 0x0001 /* PERI TEST J */ 155 #define P_TST_NORMAL 0x0000 /* PERI Normal Mode */ 156 157 /* Data Pin Configuration Register */ 158 #define LDRV 0x8000 /* b15: Drive Current Adjust */ 159 #define VIF1 0x0000 /* VIF = 1.8V */ 160 #define VIF3 0x8000 /* VIF = 3.3V */ 161 #define INTA 0x0001 /* b1: USB INT-pin active */ 162 163 /* DMAx Pin Configuration Register */ 164 #define DREQA 0x4000 /* b14: Dreq active select */ 165 #define BURST 0x2000 /* b13: Burst mode */ 166 #define DACKA 0x0400 /* b10: Dack active select */ 167 #define DFORM 0x0380 /* b9-7: DMA mode select */ 168 #define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */ 169 #define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */ 170 #define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */ 171 #define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */ 172 #define DENDA 0x0040 /* b6: Dend active select */ 173 #define PKTM 0x0020 /* b5: Packet mode */ 174 #define DENDE 0x0010 /* b4: Dend enable */ 175 #define OBUS 0x0004 /* b2: OUTbus mode */ 176 177 /* CFIFO/DxFIFO Port Select Register */ 178 #define RCNT 0x8000 /* b15: Read count mode */ 179 #define REW 0x4000 /* b14: Buffer rewind */ 180 #define DCLRM 0x2000 /* b13: DMA buffer clear mode */ 181 #define DREQE 0x1000 /* b12: DREQ output enable */ 182 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) 183 #define MBW 0x0800 184 #else 185 #if !defined(CONFIG_RZA_USB) 186 #define MBW 0x0400 /* b10: Maximum bit width for FIFO access */ 187 #else 188 #define MBW 0x0800 /* b10: Maximum bit width for FIFO access */ 189 #endif 190 #endif 191 #define MBW_8 0x0000 /* 8bit */ 192 #define MBW_16 0x0400 /* 16bit */ 193 #define MBW_32 0x0800 /* 32bit */ 194 #define BIGEND 0x0100 /* b8: Big endian mode */ 195 #define BYTE_LITTLE 0x0000 /* little dendian */ 196 #define BYTE_BIG 0x0100 /* big endifan */ 197 #define ISEL 0x0020 /* b5: DCP FIFO port direction select */ 198 #define CURPIPE 0x000F /* b2-0: PIPE select */ 199 200 /* CFIFO/DxFIFO Port Control Register */ 201 #define BVAL 0x8000 /* b15: Buffer valid flag */ 202 #define BCLR 0x4000 /* b14: Buffer clear */ 203 #define FRDY 0x2000 /* b13: FIFO ready */ 204 #define DTLN 0x0FFF /* b11-0: FIFO received data length */ 205 206 /* Interrupt Enable Register 0 */ 207 #define VBSE 0x8000 /* b15: VBUS interrupt */ 208 #define RSME 0x4000 /* b14: Resume interrupt */ 209 #define SOFE 0x2000 /* b13: Frame update interrupt */ 210 #define DVSE 0x1000 /* b12: Device state transition interrupt */ 211 #define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */ 212 #define BEMPE 0x0400 /* b10: Buffer empty interrupt */ 213 #define NRDYE 0x0200 /* b9: Buffer not ready interrupt */ 214 #define BRDYE 0x0100 /* b8: Buffer ready interrupt */ 215 216 /* Interrupt Enable Register 1 */ 217 #define OVRCRE 0x8000 /* b15: Over-current interrupt */ 218 #define BCHGE 0x4000 /* b14: USB us chenge interrupt */ 219 #define DTCHE 0x1000 /* b12: Detach sense interrupt */ 220 #define ATTCHE 0x0800 /* b11: Attach sense interrupt */ 221 #define EOFERRE 0x0040 /* b6: EOF error interrupt */ 222 #define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */ 223 #define SACKE 0x0010 /* b4: SETUP ACK interrupt */ 224 225 /* BRDY Interrupt Enable/Status Register */ 226 #define BRDY9 0x0200 /* b9: PIPE9 */ 227 #define BRDY8 0x0100 /* b8: PIPE8 */ 228 #define BRDY7 0x0080 /* b7: PIPE7 */ 229 #define BRDY6 0x0040 /* b6: PIPE6 */ 230 #define BRDY5 0x0020 /* b5: PIPE5 */ 231 #define BRDY4 0x0010 /* b4: PIPE4 */ 232 #define BRDY3 0x0008 /* b3: PIPE3 */ 233 #define BRDY2 0x0004 /* b2: PIPE2 */ 234 #define BRDY1 0x0002 /* b1: PIPE1 */ 235 #define BRDY0 0x0001 /* b1: PIPE0 */ 236 237 /* NRDY Interrupt Enable/Status Register */ 238 #define NRDY9 0x0200 /* b9: PIPE9 */ 239 #define NRDY8 0x0100 /* b8: PIPE8 */ 240 #define NRDY7 0x0080 /* b7: PIPE7 */ 241 #define NRDY6 0x0040 /* b6: PIPE6 */ 242 #define NRDY5 0x0020 /* b5: PIPE5 */ 243 #define NRDY4 0x0010 /* b4: PIPE4 */ 244 #define NRDY3 0x0008 /* b3: PIPE3 */ 245 #define NRDY2 0x0004 /* b2: PIPE2 */ 246 #define NRDY1 0x0002 /* b1: PIPE1 */ 247 #define NRDY0 0x0001 /* b1: PIPE0 */ 248 249 /* BEMP Interrupt Enable/Status Register */ 250 #define BEMP9 0x0200 /* b9: PIPE9 */ 251 #define BEMP8 0x0100 /* b8: PIPE8 */ 252 #define BEMP7 0x0080 /* b7: PIPE7 */ 253 #define BEMP6 0x0040 /* b6: PIPE6 */ 254 #define BEMP5 0x0020 /* b5: PIPE5 */ 255 #define BEMP4 0x0010 /* b4: PIPE4 */ 256 #define BEMP3 0x0008 /* b3: PIPE3 */ 257 #define BEMP2 0x0004 /* b2: PIPE2 */ 258 #define BEMP1 0x0002 /* b1: PIPE1 */ 259 #define BEMP0 0x0001 /* b0: PIPE0 */ 260 261 /* SOF Pin Configuration Register */ 262 #define TRNENSEL 0x0100 /* b8: Select transaction enable period */ 263 #define BRDYM 0x0040 /* b6: BRDY clear timing */ 264 #define INTL 0x0020 /* b5: Interrupt sense select */ 265 #define EDGESTS 0x0010 /* b4: */ 266 #define SOFMODE 0x000C /* b3-2: SOF pin select */ 267 #define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */ 268 #define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */ 269 #define SOF_DISABLE 0x0000 /* SOF OUT Disable */ 270 271 /* Interrupt Status Register 0 */ 272 #define VBINT 0x8000 /* b15: VBUS interrupt */ 273 #define RESM 0x4000 /* b14: Resume interrupt */ 274 #define SOFR 0x2000 /* b13: SOF frame update interrupt */ 275 #define DVST 0x1000 /* b12: Device state transition interrupt */ 276 #define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */ 277 #define BEMP 0x0400 /* b10: Buffer empty interrupt */ 278 #define NRDY 0x0200 /* b9: Buffer not ready interrupt */ 279 #define BRDY 0x0100 /* b8: Buffer ready interrupt */ 280 #define VBSTS 0x0080 /* b7: VBUS input port */ 281 #define DVSQ 0x0070 /* b6-4: Device state */ 282 #define DS_SPD_CNFG 0x0070 /* Suspend Configured */ 283 #define DS_SPD_ADDR 0x0060 /* Suspend Address */ 284 #define DS_SPD_DFLT 0x0050 /* Suspend Default */ 285 #define DS_SPD_POWR 0x0040 /* Suspend Powered */ 286 #define DS_SUSP 0x0040 /* Suspend */ 287 #define DS_CNFG 0x0030 /* Configured */ 288 #define DS_ADDS 0x0020 /* Address */ 289 #define DS_DFLT 0x0010 /* Default */ 290 #define DS_POWR 0x0000 /* Powered */ 291 #define DVSQS 0x0030 /* b5-4: Device state */ 292 #define VALID 0x0008 /* b3: Setup packet detected flag */ 293 #define CTSQ 0x0007 /* b2-0: Control transfer stage */ 294 #define CS_SQER 0x0006 /* Sequence error */ 295 #define CS_WRND 0x0005 /* Control write nodata status stage */ 296 #define CS_WRSS 0x0004 /* Control write status stage */ 297 #define CS_WRDS 0x0003 /* Control write data stage */ 298 #define CS_RDSS 0x0002 /* Control read status stage */ 299 #define CS_RDDS 0x0001 /* Control read data stage */ 300 #define CS_IDST 0x0000 /* Idle or setup stage */ 301 302 /* Interrupt Status Register 1 */ 303 #define OVRCR 0x8000 /* b15: Over-current interrupt */ 304 #define BCHG 0x4000 /* b14: USB bus chenge interrupt */ 305 #define DTCH 0x1000 /* b12: Detach sense interrupt */ 306 #define ATTCH 0x0800 /* b11: Attach sense interrupt */ 307 #define EOFERR 0x0040 /* b6: EOF-error interrupt */ 308 #define SIGN 0x0020 /* b5: Setup ignore interrupt */ 309 #define SACK 0x0010 /* b4: Setup acknowledge interrupt */ 310 311 /* Frame Number Register */ 312 #define OVRN 0x8000 /* b15: Overrun error */ 313 #define CRCE 0x4000 /* b14: Received data error */ 314 #define FRNM 0x07FF /* b10-0: Frame number */ 315 316 /* Micro Frame Number Register */ 317 #define UFRNM 0x0007 /* b2-0: Micro frame number */ 318 319 /* Default Control Pipe Maxpacket Size Register */ 320 /* Pipe Maxpacket Size Register */ 321 #define DEVSEL 0xF000 /* b15-14: Device address select */ 322 #define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */ 323 324 /* Default Control Pipe Control Register */ 325 #define BSTS 0x8000 /* b15: Buffer status */ 326 #define SUREQ 0x4000 /* b14: Send USB request */ 327 #define CSCLR 0x2000 /* b13: complete-split status clear */ 328 #define CSSTS 0x1000 /* b12: complete-split status */ 329 #define SUREQCLR 0x0800 /* b11: stop setup request */ 330 #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */ 331 #define SQSET 0x0080 /* b7: Sequence toggle bit set */ 332 #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */ 333 #define PBUSY 0x0020 /* b5: pipe busy */ 334 #define PINGE 0x0010 /* b4: ping enable */ 335 #define CCPL 0x0004 /* b2: Enable control transfer complete */ 336 #define PID 0x0003 /* b1-0: Response PID */ 337 #define PID_STALL11 0x0003 /* STALL */ 338 #define PID_STALL 0x0002 /* STALL */ 339 #define PID_BUF 0x0001 /* BUF */ 340 #define PID_NAK 0x0000 /* NAK */ 341 342 /* Pipe Window Select Register */ 343 #define PIPENM 0x0007 /* b2-0: Pipe select */ 344 345 /* Pipe Configuration Register */ 346 #define R8A66597_TYP 0xC000 /* b15-14: Transfer type */ 347 #define R8A66597_ISO 0xC000 /* Isochronous */ 348 #define R8A66597_INT 0x8000 /* Interrupt */ 349 #define R8A66597_BULK 0x4000 /* Bulk */ 350 #define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */ 351 #define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */ 352 #define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */ 353 #define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */ 354 #define R8A66597_DIR 0x0010 /* b4: Transfer direction select */ 355 #define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */ 356 357 /* Pipe Buffer Configuration Register */ 358 #define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */ 359 #define BUFNMB 0x007F /* b6-0: Pipe buffer number */ 360 #define PIPE0BUF 256 361 #define PIPExBUF 64 362 363 /* Pipe Maxpacket Size Register */ 364 #define MXPS 0x07FF /* b10-0: Maxpacket size */ 365 366 /* Pipe Cycle Configuration Register */ 367 #define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */ 368 #define IITV 0x0007 /* b2-0: Isochronous interval */ 369 370 /* Pipex Control Register */ 371 #define BSTS 0x8000 /* b15: Buffer status */ 372 #define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */ 373 #define CSCLR 0x2000 /* b13: complete-split status clear */ 374 #define CSSTS 0x1000 /* b12: complete-split status */ 375 #define ATREPM 0x0400 /* b10: Auto repeat mode */ 376 #define ACLRM 0x0200 /* b9: Out buffer auto clear mode */ 377 #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */ 378 #define SQSET 0x0080 /* b7: Sequence toggle bit set */ 379 #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */ 380 #define PBUSY 0x0020 /* b5: pipe busy */ 381 #define PID 0x0003 /* b1-0: Response PID */ 382 383 /* PIPExTRE */ 384 #define TRENB 0x0200 /* b9: Transaction counter enable */ 385 #define TRCLR 0x0100 /* b8: Transaction counter clear */ 386 387 /* PIPExTRN */ 388 #define TRNCNT 0xFFFF /* b15-0: Transaction counter */ 389 390 /* DEVADDx */ 391 #define UPPHUB 0x7800 392 #define HUBPORT 0x0700 393 #define USBSPD 0x00C0 394 #define RTPORT 0x0001 395 396 /* Suspend Mode Register */ 397 #define SUSPM 0x4000 /* b14: Suspend */ 398 399 #define R8A66597_MAX_NUM_PIPE 10 400 #define R8A66597_BUF_BSIZE 8 401 #define R8A66597_MAX_DEVICE 10 402 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) 403 #define R8A66597_MAX_ROOT_HUB 1 404 #else 405 #define R8A66597_MAX_ROOT_HUB 2 406 #endif 407 #define R8A66597_MAX_SAMPLING 5 408 #define R8A66597_RH_POLL_TIME 10 409 410 #define BULK_IN_PIPENUM 3 411 #define BULK_IN_BUFNUM 8 412 413 #define BULK_OUT_PIPENUM 4 414 #define BULK_OUT_BUFNUM 40 415 416 #define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5)) 417 #define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9)) 418 #define make_devsel(addr) (addr << 12) 419 420 struct r8a66597 { 421 unsigned long reg; 422 unsigned short pipe_config; /* bit field */ 423 unsigned short port_status; 424 unsigned short port_change; 425 u16 speed; /* HSMODE or FSMODE or LSMODE */ 426 unsigned char rh_devnum; 427 }; 428 429 static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset) 430 { 431 return inw(r8a66597->reg + offset); 432 } 433 434 static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597, 435 unsigned long offset, void *buf, 436 int len) 437 { 438 int i; 439 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) || defined(CONFIG_RZA_USB) 440 unsigned long fifoaddr = r8a66597->reg + offset; 441 unsigned long count; 442 unsigned long *p = buf; 443 444 count = len / 4; 445 for (i = 0; i < count; i++) 446 p[i] = inl(r8a66597->reg + offset); 447 448 if (len & 0x00000003) { 449 unsigned long tmp = inl(fifoaddr); 450 memcpy((unsigned char *)buf + count * 4, &tmp, len & 0x03); 451 } 452 #else 453 unsigned short *p = buf; 454 455 len = (len + 1) / 2; 456 for (i = 0; i < len; i++) 457 p[i] = inw(r8a66597->reg + offset); 458 #endif 459 } 460 461 static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val, 462 unsigned long offset) 463 { 464 outw(val, r8a66597->reg + offset); 465 } 466 467 static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597, 468 unsigned long offset, void *buf, 469 int len) 470 { 471 int i; 472 unsigned long fifoaddr = r8a66597->reg + offset; 473 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) || defined(CONFIG_RZA_USB) 474 unsigned long count; 475 unsigned char *pb; 476 unsigned long *p = buf; 477 478 count = len / 4; 479 for (i = 0; i < count; i++) 480 outl(p[i], fifoaddr); 481 482 if (len & 0x00000003) { 483 pb = (unsigned char *)buf + count * 4; 484 for (i = 0; i < (len & 0x00000003); i++) { 485 if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND) 486 outb(pb[i], fifoaddr + i); 487 else 488 outb(pb[i], fifoaddr + 3 - i); 489 } 490 } 491 #else 492 int odd = len & 0x0001; 493 unsigned short *p = buf; 494 495 len = len / 2; 496 for (i = 0; i < len; i++) 497 outw(p[i], fifoaddr); 498 499 if (odd) { 500 unsigned char *pb = (unsigned char *)(buf + len); 501 outb(*pb, fifoaddr); 502 } 503 #endif 504 } 505 506 static inline void r8a66597_mdfy(struct r8a66597 *r8a66597, 507 u16 val, u16 pat, unsigned long offset) 508 { 509 u16 tmp; 510 tmp = r8a66597_read(r8a66597, offset); 511 tmp = tmp & (~pat); 512 tmp = tmp | val; 513 r8a66597_write(r8a66597, tmp, offset); 514 } 515 516 #define r8a66597_bclr(r8a66597, val, offset) \ 517 r8a66597_mdfy(r8a66597, 0, val, offset) 518 #define r8a66597_bset(r8a66597, val, offset) \ 519 r8a66597_mdfy(r8a66597, val, 0, offset) 520 521 static inline unsigned long get_syscfg_reg(int port) 522 { 523 return port == 0 ? SYSCFG0 : SYSCFG1; 524 } 525 526 static inline unsigned long get_syssts_reg(int port) 527 { 528 return port == 0 ? SYSSTS0 : SYSSTS1; 529 } 530 531 static inline unsigned long get_dvstctr_reg(int port) 532 { 533 return port == 0 ? DVSTCTR0 : DVSTCTR1; 534 } 535 536 static inline unsigned long get_dmacfg_reg(int port) 537 { 538 return port == 0 ? DMA0CFG : DMA1CFG; 539 } 540 541 static inline unsigned long get_intenb_reg(int port) 542 { 543 return port == 0 ? INTENB1 : INTENB2; 544 } 545 546 static inline unsigned long get_intsts_reg(int port) 547 { 548 return port == 0 ? INTSTS1 : INTSTS2; 549 } 550 551 static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port) 552 { 553 unsigned long dvstctr_reg = get_dvstctr_reg(port); 554 555 return r8a66597_read(r8a66597, dvstctr_reg) & RHST; 556 } 557 558 static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port, 559 int power) 560 { 561 unsigned long dvstctr_reg = get_dvstctr_reg(port); 562 563 if (power) 564 r8a66597_bset(r8a66597, VBOUT, dvstctr_reg); 565 else 566 r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg); 567 } 568 569 #define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2) 570 #define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4) 571 #define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4) 572 #define get_devadd_addr(address) (DEVADD0 + address * 2) 573 574 575 /* USB HUB CONSTANTS (not OHCI-specific; see hub.h, based on usb_ohci.h) */ 576 577 /* destination of request */ 578 #define RH_INTERFACE 0x01 579 #define RH_ENDPOINT 0x02 580 #define RH_OTHER 0x03 581 582 #define RH_CLASS 0x20 583 #define RH_VENDOR 0x40 584 585 /* Requests: bRequest << 8 | bmRequestType */ 586 #define RH_GET_STATUS 0x0080 587 #define RH_CLEAR_FEATURE 0x0100 588 #define RH_SET_FEATURE 0x0300 589 #define RH_SET_ADDRESS 0x0500 590 #define RH_GET_DESCRIPTOR 0x0680 591 #define RH_SET_DESCRIPTOR 0x0700 592 #define RH_GET_CONFIGURATION 0x0880 593 #define RH_SET_CONFIGURATION 0x0900 594 #define RH_GET_STATE 0x0280 595 #define RH_GET_INTERFACE 0x0A80 596 #define RH_SET_INTERFACE 0x0B00 597 #define RH_SYNC_FRAME 0x0C80 598 /* Our Vendor Specific Request */ 599 #define RH_SET_EP 0x2000 600 601 /* Hub port features */ 602 #define RH_PORT_CONNECTION 0x00 603 #define RH_PORT_ENABLE 0x01 604 #define RH_PORT_SUSPEND 0x02 605 #define RH_PORT_OVER_CURRENT 0x03 606 #define RH_PORT_RESET 0x04 607 #define RH_PORT_POWER 0x08 608 #define RH_PORT_LOW_SPEED 0x09 609 610 #define RH_C_PORT_CONNECTION 0x10 611 #define RH_C_PORT_ENABLE 0x11 612 #define RH_C_PORT_SUSPEND 0x12 613 #define RH_C_PORT_OVER_CURRENT 0x13 614 #define RH_C_PORT_RESET 0x14 615 616 /* Hub features */ 617 #define RH_C_HUB_LOCAL_POWER 0x00 618 #define RH_C_HUB_OVER_CURRENT 0x01 619 620 #define RH_DEVICE_REMOTE_WAKEUP 0x00 621 #define RH_ENDPOINT_STALL 0x01 622 623 #define RH_ACK 0x01 624 #define RH_REQ_ERR -1 625 #define RH_NACK 0x00 626 627 /* OHCI ROOT HUB REGISTER MASKS */ 628 629 /* roothub.portstatus [i] bits */ 630 #define RH_PS_CCS 0x00000001 /* current connect status */ 631 #define RH_PS_PES 0x00000002 /* port enable status*/ 632 #define RH_PS_PSS 0x00000004 /* port suspend status */ 633 #define RH_PS_POCI 0x00000008 /* port over current indicator */ 634 #define RH_PS_PRS 0x00000010 /* port reset status */ 635 #define RH_PS_PPS 0x00000100 /* port power status */ 636 #define RH_PS_LSDA 0x00000200 /* low speed device attached */ 637 #define RH_PS_CSC 0x00010000 /* connect status change */ 638 #define RH_PS_PESC 0x00020000 /* port enable status change */ 639 #define RH_PS_PSSC 0x00040000 /* port suspend status change */ 640 #define RH_PS_OCIC 0x00080000 /* over current indicator change */ 641 #define RH_PS_PRSC 0x00100000 /* port reset status change */ 642 643 /* roothub.status bits */ 644 #define RH_HS_LPS 0x00000001 /* local power status */ 645 #define RH_HS_OCI 0x00000002 /* over current indicator */ 646 #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ 647 #define RH_HS_LPSC 0x00010000 /* local power status change */ 648 #define RH_HS_OCIC 0x00020000 /* over current indicator change */ 649 #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ 650 651 /* roothub.b masks */ 652 #define RH_B_DR 0x0000ffff /* device removable flags */ 653 #define RH_B_PPCM 0xffff0000 /* port power control mask */ 654 655 /* roothub.a masks */ 656 #define RH_A_NDP (0xff << 0) /* number of downstream ports */ 657 #define RH_A_PSM (1 << 8) /* power switching mode */ 658 #define RH_A_NPS (1 << 9) /* no power switching */ 659 #define RH_A_DT (1 << 10) /* device type (mbz) */ 660 #define RH_A_OCPM (1 << 11) /* over current protection mode */ 661 #define RH_A_NOCP (1 << 12) /* no over current protection */ 662 #define RH_A_POTPGT (0xff << 24) /* power on to power good time */ 663 664 #endif /* __R8A66597_H__ */ 665