1 /* 2 * URB OHCI HCD (Host Controller Driver) for USB. 3 * 4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 5 * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net> 6 * 7 * usb-ohci.h 8 */ 9 10 /* 11 * e.g. PCI controllers need this 12 */ 13 #ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS 14 # define ohci_readl(a) __swap_32(*((volatile u32 *)(a))) 15 # define ohci_writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a)) 16 #else 17 # define ohci_readl(a) (*((volatile u32 *)(a))) 18 # define ohci_writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a)) 19 #endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */ 20 21 /* functions for doing board or CPU specific setup/cleanup */ 22 extern int usb_board_init(void); 23 extern int usb_board_stop(void); 24 extern int usb_board_init_fail(void); 25 26 extern int usb_cpu_init(void); 27 extern int usb_cpu_stop(void); 28 extern int usb_cpu_init_fail(void); 29 30 31 static int cc_to_error[16] = { 32 33 /* mapping of the OHCI CC status to error codes */ 34 /* No Error */ 0, 35 /* CRC Error */ USB_ST_CRC_ERR, 36 /* Bit Stuff */ USB_ST_BIT_ERR, 37 /* Data Togg */ USB_ST_CRC_ERR, 38 /* Stall */ USB_ST_STALLED, 39 /* DevNotResp */ -1, 40 /* PIDCheck */ USB_ST_BIT_ERR, 41 /* UnExpPID */ USB_ST_BIT_ERR, 42 /* DataOver */ USB_ST_BUF_ERR, 43 /* DataUnder */ USB_ST_BUF_ERR, 44 /* reservd */ -1, 45 /* reservd */ -1, 46 /* BufferOver */ USB_ST_BUF_ERR, 47 /* BuffUnder */ USB_ST_BUF_ERR, 48 /* Not Access */ -1, 49 /* Not Access */ -1 50 }; 51 52 static const char *cc_to_string[16] = { 53 "No Error", 54 "CRC: Last data packet from endpoint contained a CRC error.", 55 "BITSTUFFING: Last data packet from endpoint contained a bit " \ 56 "stuffing violation", 57 "DATATOGGLEMISMATCH: Last packet from endpoint had data toggle PID\n" \ 58 "that did not match the expected value.", 59 "STALL: TD was moved to the Done Queue because the endpoint returned" \ 60 " a STALL PID", 61 "DEVICENOTRESPONDING: Device did not respond to token (IN) or did\n" \ 62 "not provide a handshake (OUT)", 63 "PIDCHECKFAILURE: Check bits on PID from endpoint failed on data PID\n"\ 64 "(IN) or handshake (OUT)", 65 "UNEXPECTEDPID: Receive PID was not valid when encountered or PID\n" \ 66 "value is not defined.", 67 "DATAOVERRUN: The amount of data returned by the endpoint exceeded\n" \ 68 "either the size of the maximum data packet allowed\n" \ 69 "from the endpoint (found in MaximumPacketSize field\n" \ 70 "of ED) or the remaining buffer size.", 71 "DATAUNDERRUN: The endpoint returned less than MaximumPacketSize\n" \ 72 "and that amount was not sufficient to fill the\n" \ 73 "specified buffer", 74 "reserved1", 75 "reserved2", 76 "BUFFEROVERRUN: During an IN, HC received data from endpoint faster\n" \ 77 "than it could be written to system memory", 78 "BUFFERUNDERRUN: During an OUT, HC could not retrieve data from\n" \ 79 "system memory fast enough to keep up with data USB " \ 80 "data rate.", 81 "NOT ACCESSED: This code is set by software before the TD is placed" \ 82 "on a list to be processed by the HC.(1)", 83 "NOT ACCESSED: This code is set by software before the TD is placed" \ 84 "on a list to be processed by the HC.(2)", 85 }; 86 87 /* ED States */ 88 89 #define ED_NEW 0x00 90 #define ED_UNLINK 0x01 91 #define ED_OPER 0x02 92 #define ED_DEL 0x04 93 #define ED_URB_DEL 0x08 94 95 /* usb_ohci_ed */ 96 struct ed { 97 __u32 hwINFO; 98 __u32 hwTailP; 99 __u32 hwHeadP; 100 __u32 hwNextED; 101 102 struct ed *ed_prev; 103 __u8 int_period; 104 __u8 int_branch; 105 __u8 int_load; 106 __u8 int_interval; 107 __u8 state; 108 __u8 type; 109 __u16 last_iso; 110 struct ed *ed_rm_list; 111 112 struct usb_device *usb_dev; 113 void *purb; 114 __u32 unused[2]; 115 } __attribute__((aligned(16))); 116 typedef struct ed ed_t; 117 118 119 /* TD info field */ 120 #define TD_CC 0xf0000000 121 #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) 122 #define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) 123 #define TD_EC 0x0C000000 124 #define TD_T 0x03000000 125 #define TD_T_DATA0 0x02000000 126 #define TD_T_DATA1 0x03000000 127 #define TD_T_TOGGLE 0x00000000 128 #define TD_R 0x00040000 129 #define TD_DI 0x00E00000 130 #define TD_DI_SET(X) (((X) & 0x07)<< 21) 131 #define TD_DP 0x00180000 132 #define TD_DP_SETUP 0x00000000 133 #define TD_DP_IN 0x00100000 134 #define TD_DP_OUT 0x00080000 135 136 #define TD_ISO 0x00010000 137 #define TD_DEL 0x00020000 138 139 /* CC Codes */ 140 #define TD_CC_NOERROR 0x00 141 #define TD_CC_CRC 0x01 142 #define TD_CC_BITSTUFFING 0x02 143 #define TD_CC_DATATOGGLEM 0x03 144 #define TD_CC_STALL 0x04 145 #define TD_DEVNOTRESP 0x05 146 #define TD_PIDCHECKFAIL 0x06 147 #define TD_UNEXPECTEDPID 0x07 148 #define TD_DATAOVERRUN 0x08 149 #define TD_DATAUNDERRUN 0x09 150 #define TD_BUFFEROVERRUN 0x0C 151 #define TD_BUFFERUNDERRUN 0x0D 152 #define TD_NOTACCESSED 0x0F 153 154 155 #define MAXPSW 1 156 157 struct td { 158 __u32 hwINFO; 159 __u32 hwCBP; /* Current Buffer Pointer */ 160 __u32 hwNextTD; /* Next TD Pointer */ 161 __u32 hwBE; /* Memory Buffer End Pointer */ 162 163 /* #ifndef CONFIG_MPC5200 /\* this seems wrong *\/ */ 164 __u16 hwPSW[MAXPSW]; 165 /* #endif */ 166 __u8 unused; 167 __u8 index; 168 struct ed *ed; 169 struct td *next_dl_td; 170 struct usb_device *usb_dev; 171 int transfer_len; 172 __u32 data; 173 174 __u32 unused2[2]; 175 } __attribute__((aligned(32))); 176 typedef struct td td_t; 177 178 #define OHCI_ED_SKIP (1 << 14) 179 180 /* 181 * The HCCA (Host Controller Communications Area) is a 256 byte 182 * structure defined in the OHCI spec. that the host controller is 183 * told the base address of. It must be 256-byte aligned. 184 */ 185 186 #define NUM_INTS 32 /* part of the OHCI standard */ 187 struct ohci_hcca { 188 __u32 int_table[NUM_INTS]; /* Interrupt ED table */ 189 #if defined(CONFIG_MPC5200) 190 __u16 pad1; /* set to 0 on each frame_no change */ 191 __u16 frame_no; /* current frame number */ 192 #else 193 __u16 frame_no; /* current frame number */ 194 __u16 pad1; /* set to 0 on each frame_no change */ 195 #endif 196 __u32 done_head; /* info returned for an interrupt */ 197 u8 reserved_for_hc[116]; 198 } __attribute__((aligned(256))); 199 200 201 /* 202 * Maximum number of root hub ports. 203 */ 204 #ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 205 # error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!" 206 #endif 207 208 /* 209 * This is the structure of the OHCI controller's memory mapped I/O 210 * region. This is Memory Mapped I/O. You must use the ohci_readl() and 211 * ohci_writel() macros defined in this file to access these!! 212 */ 213 struct ohci_regs { 214 /* control and status registers */ 215 __u32 revision; 216 __u32 control; 217 __u32 cmdstatus; 218 __u32 intrstatus; 219 __u32 intrenable; 220 __u32 intrdisable; 221 /* memory pointers */ 222 __u32 hcca; 223 __u32 ed_periodcurrent; 224 __u32 ed_controlhead; 225 __u32 ed_controlcurrent; 226 __u32 ed_bulkhead; 227 __u32 ed_bulkcurrent; 228 __u32 donehead; 229 /* frame counters */ 230 __u32 fminterval; 231 __u32 fmremaining; 232 __u32 fmnumber; 233 __u32 periodicstart; 234 __u32 lsthresh; 235 /* Root hub ports */ 236 struct ohci_roothub_regs { 237 __u32 a; 238 __u32 b; 239 __u32 status; 240 __u32 portstatus[CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS]; 241 } roothub; 242 } __attribute__((aligned(32))); 243 244 /* Some EHCI controls */ 245 #define EHCI_USBCMD_OFF 0x20 246 #define EHCI_USBCMD_HCRESET (1 << 1) 247 248 /* OHCI CONTROL AND STATUS REGISTER MASKS */ 249 250 /* 251 * HcControl (control) register masks 252 */ 253 #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ 254 #define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ 255 #define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ 256 #define OHCI_CTRL_CLE (1 << 4) /* control list enable */ 257 #define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ 258 #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ 259 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ 260 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ 261 #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ 262 263 /* pre-shifted values for HCFS */ 264 # define OHCI_USB_RESET (0 << 6) 265 # define OHCI_USB_RESUME (1 << 6) 266 # define OHCI_USB_OPER (2 << 6) 267 # define OHCI_USB_SUSPEND (3 << 6) 268 269 /* 270 * HcCommandStatus (cmdstatus) register masks 271 */ 272 #define OHCI_HCR (1 << 0) /* host controller reset */ 273 #define OHCI_CLF (1 << 1) /* control list filled */ 274 #define OHCI_BLF (1 << 2) /* bulk list filled */ 275 #define OHCI_OCR (1 << 3) /* ownership change request */ 276 #define OHCI_SOC (3 << 16) /* scheduling overrun count */ 277 278 /* 279 * masks used with interrupt registers: 280 * HcInterruptStatus (intrstatus) 281 * HcInterruptEnable (intrenable) 282 * HcInterruptDisable (intrdisable) 283 */ 284 #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ 285 #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ 286 #define OHCI_INTR_SF (1 << 2) /* start frame */ 287 #define OHCI_INTR_RD (1 << 3) /* resume detect */ 288 #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ 289 #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ 290 #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ 291 #define OHCI_INTR_OC (1 << 30) /* ownership change */ 292 #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ 293 294 295 /* Virtual Root HUB */ 296 struct virt_root_hub { 297 int devnum; /* Address of Root Hub endpoint */ 298 void *dev; /* was urb */ 299 void *int_addr; 300 int send; 301 int interval; 302 }; 303 304 /* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ 305 306 /* destination of request */ 307 #define RH_INTERFACE 0x01 308 #define RH_ENDPOINT 0x02 309 #define RH_OTHER 0x03 310 311 #define RH_CLASS 0x20 312 #define RH_VENDOR 0x40 313 314 /* Requests: bRequest << 8 | bmRequestType */ 315 #define RH_GET_STATUS 0x0080 316 #define RH_CLEAR_FEATURE 0x0100 317 #define RH_SET_FEATURE 0x0300 318 #define RH_SET_ADDRESS 0x0500 319 #define RH_GET_DESCRIPTOR 0x0680 320 #define RH_SET_DESCRIPTOR 0x0700 321 #define RH_GET_CONFIGURATION 0x0880 322 #define RH_SET_CONFIGURATION 0x0900 323 #define RH_GET_STATE 0x0280 324 #define RH_GET_INTERFACE 0x0A80 325 #define RH_SET_INTERFACE 0x0B00 326 #define RH_SYNC_FRAME 0x0C80 327 /* Our Vendor Specific Request */ 328 #define RH_SET_EP 0x2000 329 330 331 /* Hub port features */ 332 #define RH_PORT_CONNECTION 0x00 333 #define RH_PORT_ENABLE 0x01 334 #define RH_PORT_SUSPEND 0x02 335 #define RH_PORT_OVER_CURRENT 0x03 336 #define RH_PORT_RESET 0x04 337 #define RH_PORT_POWER 0x08 338 #define RH_PORT_LOW_SPEED 0x09 339 340 #define RH_C_PORT_CONNECTION 0x10 341 #define RH_C_PORT_ENABLE 0x11 342 #define RH_C_PORT_SUSPEND 0x12 343 #define RH_C_PORT_OVER_CURRENT 0x13 344 #define RH_C_PORT_RESET 0x14 345 346 /* Hub features */ 347 #define RH_C_HUB_LOCAL_POWER 0x00 348 #define RH_C_HUB_OVER_CURRENT 0x01 349 350 #define RH_DEVICE_REMOTE_WAKEUP 0x00 351 #define RH_ENDPOINT_STALL 0x01 352 353 #define RH_ACK 0x01 354 #define RH_REQ_ERR -1 355 #define RH_NACK 0x00 356 357 358 /* OHCI ROOT HUB REGISTER MASKS */ 359 360 /* roothub.portstatus [i] bits */ 361 #define RH_PS_CCS 0x00000001 /* current connect status */ 362 #define RH_PS_PES 0x00000002 /* port enable status*/ 363 #define RH_PS_PSS 0x00000004 /* port suspend status */ 364 #define RH_PS_POCI 0x00000008 /* port over current indicator */ 365 #define RH_PS_PRS 0x00000010 /* port reset status */ 366 #define RH_PS_PPS 0x00000100 /* port power status */ 367 #define RH_PS_LSDA 0x00000200 /* low speed device attached */ 368 #define RH_PS_CSC 0x00010000 /* connect status change */ 369 #define RH_PS_PESC 0x00020000 /* port enable status change */ 370 #define RH_PS_PSSC 0x00040000 /* port suspend status change */ 371 #define RH_PS_OCIC 0x00080000 /* over current indicator change */ 372 #define RH_PS_PRSC 0x00100000 /* port reset status change */ 373 374 /* roothub.status bits */ 375 #define RH_HS_LPS 0x00000001 /* local power status */ 376 #define RH_HS_OCI 0x00000002 /* over current indicator */ 377 #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ 378 #define RH_HS_LPSC 0x00010000 /* local power status change */ 379 #define RH_HS_OCIC 0x00020000 /* over current indicator change */ 380 #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ 381 382 /* roothub.b masks */ 383 #define RH_B_DR 0x0000ffff /* device removable flags */ 384 #define RH_B_PPCM 0xffff0000 /* port power control mask */ 385 386 /* roothub.a masks */ 387 #define RH_A_NDP (0xff << 0) /* number of downstream ports */ 388 #define RH_A_PSM (1 << 8) /* power switching mode */ 389 #define RH_A_NPS (1 << 9) /* no power switching */ 390 #define RH_A_DT (1 << 10) /* device type (mbz) */ 391 #define RH_A_OCPM (1 << 11) /* over current protection mode */ 392 #define RH_A_NOCP (1 << 12) /* no over current protection */ 393 #define RH_A_POTPGT (0xff << 24) /* power on to power good time */ 394 395 /* urb */ 396 #define N_URB_TD 48 397 typedef struct 398 { 399 ed_t *ed; 400 __u16 length; /* number of tds associated with this request */ 401 __u16 td_cnt; /* number of tds already serviced */ 402 struct usb_device *dev; 403 int state; 404 unsigned long pipe; 405 void *transfer_buffer; 406 int transfer_buffer_length; 407 int interval; 408 int actual_length; 409 int finished; 410 td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ 411 } urb_priv_t; 412 #define URB_DEL 1 413 414 /* 415 * This is the full ohci controller description 416 * 417 * Note how the "proper" USB information is just 418 * a subset of what the full implementation needs. (Linus) 419 */ 420 421 422 typedef struct ohci { 423 struct ohci_hcca *hcca; /* hcca */ 424 /*dma_addr_t hcca_dma;*/ 425 426 int irq; 427 int disabled; /* e.g. got a UE, we're hung */ 428 int sleeping; 429 unsigned long flags; /* for HC bugs */ 430 431 struct ohci_regs *regs; /* OHCI controller's memory */ 432 433 int ohci_int_load[32]; /* load of the 32 Interrupt Chains (for load balancing)*/ 434 ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ 435 ed_t *ed_bulktail; /* last endpoint of bulk list */ 436 ed_t *ed_controltail; /* last endpoint of control list */ 437 int intrstatus; 438 __u32 hc_control; /* copy of the hc control reg */ 439 struct usb_device *dev[32]; 440 struct virt_root_hub rh; 441 442 const char *slot_name; 443 } ohci_t; 444 445 #define NUM_EDS 8 /* num of preallocated endpoint descriptors */ 446 447 struct ohci_device { 448 ed_t ed[NUM_EDS]; 449 int ed_cnt; 450 }; 451 452 /* hcd */ 453 /* endpoint */ 454 static int ep_link(ohci_t * ohci, ed_t * ed); 455 static int ep_unlink(ohci_t * ohci, ed_t * ed); 456 static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe, 457 int interval, int load); 458 459 /*-------------------------------------------------------------------------*/ 460 461 /* we need more TDs than EDs */ 462 #define NUM_TD 64 463 464 /* +1 so we can align the storage */ 465 td_t gtd[NUM_TD+1]; 466 /* pointers to aligned storage */ 467 td_t *ptd; 468 469 /* TDs ... */ 470 static inline struct td * 471 td_alloc (struct usb_device *usb_dev) 472 { 473 int i; 474 struct td *td; 475 476 td = NULL; 477 for (i = 0; i < NUM_TD; i++) 478 { 479 if (ptd[i].usb_dev == NULL) 480 { 481 td = &ptd[i]; 482 td->usb_dev = usb_dev; 483 break; 484 } 485 } 486 487 return td; 488 } 489 490 static inline void 491 ed_free (struct ed *ed) 492 { 493 ed->usb_dev = NULL; 494 } 495