1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2008 by NXP Semiconductors 4 * @Author: Based on code by Kevin Wells 5 * @Descr: USB driver - Embedded Artists LPC3250 OEM Board support functions 6 * 7 * Copyright (c) 2015 Tyco Fire Protection Products. 8 */ 9 10 #include <common.h> 11 #include <dm.h> 12 #include <errno.h> 13 #include <wait_bit.h> 14 #include <asm/io.h> 15 #include <asm/arch/cpu.h> 16 #include <asm/arch/clk.h> 17 #include <asm/arch/i2c.h> 18 #include <usb.h> 19 #include <i2c.h> 20 21 /* OTG I2C controller module register structures */ 22 struct otgi2c_regs { 23 u32 otg_i2c_txrx; /* OTG I2C Tx/Rx Data FIFO */ 24 u32 otg_i2c_stat; /* OTG I2C Status Register */ 25 u32 otg_i2c_ctrl; /* OTG I2C Control Register */ 26 u32 otg_i2c_clk_hi; /* OTG I2C Clock Divider high */ 27 u32 otg_i2c_clk_lo; /* OTG I2C Clock Divider low */ 28 }; 29 30 /* OTG controller module register structures */ 31 struct otg_regs { 32 u32 reserved1[64]; 33 u32 otg_int_sts; /* OTG int status register */ 34 u32 otg_int_enab; /* OTG int enable register */ 35 u32 otg_int_set; /* OTG int set register */ 36 u32 otg_int_clr; /* OTG int clear register */ 37 u32 otg_sts_ctrl; /* OTG status/control register */ 38 u32 otg_timer; /* OTG timer register */ 39 u32 reserved2[122]; 40 struct otgi2c_regs otg_i2c; 41 u32 reserved3[824]; 42 u32 otg_clk_ctrl; /* OTG clock control reg */ 43 u32 otg_clk_sts; /* OTG clock status reg */ 44 }; 45 46 /* otg_sts_ctrl register definitions */ 47 #define OTG_HOST_EN (1 << 0) /* Enable host mode */ 48 49 /* otg_clk_ctrl and otg_clk_sts register definitions */ 50 #define OTG_CLK_AHB_EN (1 << 4) /* Enable AHB clock */ 51 #define OTG_CLK_OTG_EN (1 << 3) /* Enable OTG clock */ 52 #define OTG_CLK_I2C_EN (1 << 2) /* Enable I2C clock */ 53 #define OTG_CLK_HOST_EN (1 << 0) /* Enable host clock */ 54 55 /* ISP1301 USB transceiver I2C registers */ 56 #define MC1_SPEED_REG (1 << 0) 57 #define MC1_DAT_SE0 (1 << 2) 58 #define MC1_UART_EN (1 << 6) 59 60 #define MC2_SPD_SUSP_CTRL (1 << 1) 61 #define MC2_BI_DI (1 << 2) 62 #define MC2_PSW_EN (1 << 6) 63 64 #define OTG1_DP_PULLUP (1 << 0) 65 #define OTG1_DM_PULLUP (1 << 1) 66 #define OTG1_DP_PULLDOWN (1 << 2) 67 #define OTG1_DM_PULLDOWN (1 << 3) 68 #define OTG1_VBUS_DRV (1 << 5) 69 70 #define ISP1301_I2C_ADDR CONFIG_USB_ISP1301_I2C_ADDR 71 72 #define ISP1301_I2C_MODE_CONTROL_1_SET 0x04 73 #define ISP1301_I2C_MODE_CONTROL_1_CLR 0x05 74 #define ISP1301_I2C_MODE_CONTROL_2_SET 0x12 75 #define ISP1301_I2C_MODE_CONTROL_2_CLR 0x13 76 #define ISP1301_I2C_OTG_CONTROL_1_SET 0x06 77 #define ISP1301_I2C_OTG_CONTROL_1_CLR 0x07 78 #define ISP1301_I2C_INTERRUPT_LATCH_CLR 0x0B 79 #define ISP1301_I2C_INTERRUPT_FALLING_CLR 0x0D 80 #define ISP1301_I2C_INTERRUPT_RISING_CLR 0x0F 81 82 static struct otg_regs *otg = (struct otg_regs *)USB_BASE; 83 static struct clk_pm_regs *clk_pwr = (struct clk_pm_regs *)CLK_PM_BASE; 84 85 static int isp1301_set_value(struct udevice *dev, int reg, u8 value) 86 { 87 #ifndef CONFIG_DM_I2C 88 return i2c_write(ISP1301_I2C_ADDR, reg, 1, &value, 1); 89 #else 90 return dm_i2c_write(dev, reg, &value, 1); 91 #endif 92 } 93 94 static void isp1301_configure(struct udevice *dev) 95 { 96 #ifndef CONFIG_DM_I2C 97 i2c_set_bus_num(I2C_2); 98 #endif 99 100 /* 101 * LPC32XX only supports DAT_SE0 USB mode 102 * This sequence is important 103 */ 104 105 /* Disable transparent UART mode first */ 106 isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_CLR, MC1_UART_EN); 107 108 isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_CLR, ~MC1_SPEED_REG); 109 isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_SET, MC1_SPEED_REG); 110 isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_2_CLR, ~0); 111 isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_2_SET, 112 MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL); 113 114 isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_CLR, ~0); 115 isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_SET, MC1_DAT_SE0); 116 isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET, 117 OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN); 118 isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_CLR, 119 OTG1_DM_PULLUP | OTG1_DP_PULLUP); 120 isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_LATCH_CLR, ~0); 121 isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_FALLING_CLR, ~0); 122 isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_RISING_CLR, ~0); 123 124 /* Enable usb_need_clk clock after transceiver is initialized */ 125 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBDVND_EN); 126 } 127 128 static int usbpll_setup(void) 129 { 130 u32 ret; 131 132 /* make sure clocks are disabled */ 133 clrbits_le32(&clk_pwr->usb_ctrl, 134 CLK_USBCTRL_CLK_EN1 | CLK_USBCTRL_CLK_EN2); 135 136 /* start PLL clock input */ 137 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN1); 138 139 /* Setup PLL. */ 140 setbits_le32(&clk_pwr->usb_ctrl, 141 CLK_USBCTRL_FDBK_PLUS1(192 - 1)); 142 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_POSTDIV_2POW(0x01)); 143 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_PWRUP); 144 145 ret = wait_for_bit_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_STS, 146 true, CONFIG_SYS_HZ, false); 147 if (ret) 148 return ret; 149 150 /* enable PLL output */ 151 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN2); 152 153 return 0; 154 } 155 156 int usb_cpu_init(void) 157 { 158 u32 ret; 159 struct udevice *dev = NULL; 160 161 #ifdef CONFIG_DM_I2C 162 ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR, 1, &dev); 163 if (ret) { 164 debug("%s: No bus %d\n", __func__, I2C_2); 165 return ret; 166 } 167 #endif 168 169 /* 170 * USB pins routing setup is done by "lpc32xx_usb_init()" and should 171 * be call by board "board_init()" or "misc_init_r()" functions. 172 */ 173 174 /* enable AHB slave USB clock */ 175 setbits_le32(&clk_pwr->usb_ctrl, 176 CLK_USBCTRL_HCLK_EN | CLK_USBCTRL_BUS_KEEPER); 177 178 /* enable I2C clock */ 179 writel(OTG_CLK_I2C_EN, &otg->otg_clk_ctrl); 180 ret = wait_for_bit_le32(&otg->otg_clk_sts, OTG_CLK_I2C_EN, true, 181 CONFIG_SYS_HZ, false); 182 if (ret) 183 return ret; 184 185 /* Configure ISP1301 */ 186 isp1301_configure(dev); 187 188 /* setup USB clocks and PLL */ 189 ret = usbpll_setup(); 190 if (ret) 191 return ret; 192 193 /* enable usb_host_need_clk */ 194 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBHSTND_EN); 195 196 /* enable all needed USB clocks */ 197 const u32 mask = OTG_CLK_AHB_EN | OTG_CLK_OTG_EN | 198 OTG_CLK_I2C_EN | OTG_CLK_HOST_EN; 199 writel(mask, &otg->otg_clk_ctrl); 200 201 ret = wait_for_bit_le32(&otg->otg_clk_sts, mask, true, 202 CONFIG_SYS_HZ, false); 203 if (ret) 204 return ret; 205 206 setbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN); 207 isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV); 208 209 return 0; 210 } 211 212 int usb_cpu_stop(void) 213 { 214 struct udevice *dev = NULL; 215 int ret = 0; 216 217 #ifdef CONFIG_DM_I2C 218 ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR, 1, &dev); 219 if (ret) { 220 debug("%s: No bus %d\n", __func__, I2C_2); 221 return ret; 222 } 223 #endif 224 225 /* vbus off */ 226 isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV); 227 228 clrbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN); 229 230 clrbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_HCLK_EN); 231 232 return ret; 233 } 234 235 int usb_cpu_init_fail(void) 236 { 237 return usb_cpu_stop(); 238 } 239