1 /* 2 * Copyright (C) 2008 by NXP Semiconductors 3 * @Author: Based on code by Kevin Wells 4 * @Descr: USB driver - Embedded Artists LPC3250 OEM Board support functions 5 * 6 * Copyright (c) 2015 Tyco Fire Protection Products. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <errno.h> 13 #include <asm/io.h> 14 #include <asm/arch/cpu.h> 15 #include <asm/arch/clk.h> 16 #include <usb.h> 17 #include <i2c.h> 18 19 /* OTG I2C controller module register structures */ 20 struct otgi2c_regs { 21 u32 otg_i2c_txrx; /* OTG I2C Tx/Rx Data FIFO */ 22 u32 otg_i2c_stat; /* OTG I2C Status Register */ 23 u32 otg_i2c_ctrl; /* OTG I2C Control Register */ 24 u32 otg_i2c_clk_hi; /* OTG I2C Clock Divider high */ 25 u32 otg_i2c_clk_lo; /* OTG I2C Clock Divider low */ 26 }; 27 28 /* OTG controller module register structures */ 29 struct otg_regs { 30 u32 reserved1[64]; 31 u32 otg_int_sts; /* OTG int status register */ 32 u32 otg_int_enab; /* OTG int enable register */ 33 u32 otg_int_set; /* OTG int set register */ 34 u32 otg_int_clr; /* OTG int clear register */ 35 u32 otg_sts_ctrl; /* OTG status/control register */ 36 u32 otg_timer; /* OTG timer register */ 37 u32 reserved2[122]; 38 struct otgi2c_regs otg_i2c; 39 u32 reserved3[824]; 40 u32 otg_clk_ctrl; /* OTG clock control reg */ 41 u32 otg_clk_sts; /* OTG clock status reg */ 42 }; 43 44 /* otg_sts_ctrl register definitions */ 45 #define OTG_HOST_EN (1 << 0) /* Enable host mode */ 46 47 /* otg_clk_ctrl and otg_clk_sts register definitions */ 48 #define OTG_CLK_AHB_EN (1 << 4) /* Enable AHB clock */ 49 #define OTG_CLK_OTG_EN (1 << 3) /* Enable OTG clock */ 50 #define OTG_CLK_I2C_EN (1 << 2) /* Enable I2C clock */ 51 #define OTG_CLK_HOST_EN (1 << 0) /* Enable host clock */ 52 53 /* ISP1301 USB transceiver I2C registers */ 54 #define MC1_SPEED_REG (1 << 0) 55 #define MC1_DAT_SE0 (1 << 2) 56 #define MC1_UART_EN (1 << 6) 57 58 #define MC2_SPD_SUSP_CTRL (1 << 1) 59 #define MC2_BI_DI (1 << 2) 60 #define MC2_PSW_EN (1 << 6) 61 62 #define OTG1_DP_PULLUP (1 << 0) 63 #define OTG1_DM_PULLUP (1 << 1) 64 #define OTG1_DP_PULLDOWN (1 << 2) 65 #define OTG1_DM_PULLDOWN (1 << 3) 66 #define OTG1_VBUS_DRV (1 << 5) 67 68 #define ISP1301_I2C_ADDR CONFIG_USB_ISP1301_I2C_ADDR 69 70 #define ISP1301_I2C_MODE_CONTROL_1_SET 0x04 71 #define ISP1301_I2C_MODE_CONTROL_1_CLR 0x05 72 #define ISP1301_I2C_MODE_CONTROL_2_SET 0x12 73 #define ISP1301_I2C_MODE_CONTROL_2_CLR 0x13 74 #define ISP1301_I2C_OTG_CONTROL_1_SET 0x06 75 #define ISP1301_I2C_OTG_CONTROL_1_CLR 0x07 76 #define ISP1301_I2C_INTERRUPT_LATCH_CLR 0x0B 77 #define ISP1301_I2C_INTERRUPT_FALLING_CLR 0x0D 78 #define ISP1301_I2C_INTERRUPT_RISING_CLR 0x0F 79 80 static struct otg_regs *otg = (struct otg_regs *)USB_BASE; 81 static struct clk_pm_regs *clk_pwr = (struct clk_pm_regs *)CLK_PM_BASE; 82 83 static int wait_for_bit(void *reg, const u32 mask, bool set) 84 { 85 u32 val; 86 unsigned long start = get_timer(0); 87 88 while (1) { 89 val = readl(reg); 90 if (!set) 91 val = ~val; 92 93 if ((val & mask) == mask) 94 return 0; 95 96 if (get_timer(start) > CONFIG_SYS_HZ) 97 break; 98 99 udelay(1); 100 } 101 102 error("Timeout (reg=%p mask=%08x wait_set=%i)\n", reg, mask, set); 103 104 return -ETIMEDOUT; 105 } 106 107 static int isp1301_set_value(int reg, u8 value) 108 { 109 return i2c_write(ISP1301_I2C_ADDR, reg, 1, &value, 1); 110 } 111 112 static void isp1301_configure(void) 113 { 114 i2c_set_bus_num(I2C_2); 115 116 /* 117 * LPC32XX only supports DAT_SE0 USB mode 118 * This sequence is important 119 */ 120 121 /* Disable transparent UART mode first */ 122 isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_CLR, MC1_UART_EN); 123 124 isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_CLR, ~MC1_SPEED_REG); 125 isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_SET, MC1_SPEED_REG); 126 isp1301_set_value(ISP1301_I2C_MODE_CONTROL_2_CLR, ~0); 127 isp1301_set_value(ISP1301_I2C_MODE_CONTROL_2_SET, 128 MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL); 129 130 isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_CLR, ~0); 131 isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_SET, MC1_DAT_SE0); 132 isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_SET, 133 OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN); 134 isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_CLR, 135 OTG1_DM_PULLUP | OTG1_DP_PULLUP); 136 isp1301_set_value(ISP1301_I2C_INTERRUPT_LATCH_CLR, ~0); 137 isp1301_set_value(ISP1301_I2C_INTERRUPT_FALLING_CLR, ~0); 138 isp1301_set_value(ISP1301_I2C_INTERRUPT_RISING_CLR, ~0); 139 140 /* Enable usb_need_clk clock after transceiver is initialized */ 141 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBDVND_EN); 142 } 143 144 static int usbpll_setup(void) 145 { 146 u32 ret; 147 148 /* make sure clocks are disabled */ 149 clrbits_le32(&clk_pwr->usb_ctrl, 150 CLK_USBCTRL_CLK_EN1 | CLK_USBCTRL_CLK_EN2); 151 152 /* start PLL clock input */ 153 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN1); 154 155 /* Setup PLL. */ 156 setbits_le32(&clk_pwr->usb_ctrl, 157 CLK_USBCTRL_FDBK_PLUS1(192 - 1)); 158 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_POSTDIV_2POW(0x01)); 159 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_PWRUP); 160 161 ret = wait_for_bit(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_STS, 1); 162 if (ret) 163 return ret; 164 165 /* enable PLL output */ 166 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN2); 167 168 return 0; 169 } 170 171 int usb_cpu_init(void) 172 { 173 u32 ret; 174 175 /* 176 * USB pins routing setup is done by "lpc32xx_usb_init()" and should 177 * be call by board "board_init()" or "misc_init_r()" functions. 178 */ 179 180 /* enable AHB slave USB clock */ 181 setbits_le32(&clk_pwr->usb_ctrl, 182 CLK_USBCTRL_HCLK_EN | CLK_USBCTRL_BUS_KEEPER); 183 184 /* enable I2C clock */ 185 writel(OTG_CLK_I2C_EN, &otg->otg_clk_ctrl); 186 ret = wait_for_bit(&otg->otg_clk_sts, OTG_CLK_I2C_EN, 1); 187 if (ret) 188 return ret; 189 190 /* Configure ISP1301 */ 191 isp1301_configure(); 192 193 /* setup USB clocks and PLL */ 194 ret = usbpll_setup(); 195 if (ret) 196 return ret; 197 198 /* enable usb_host_need_clk */ 199 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBHSTND_EN); 200 201 /* enable all needed USB clocks */ 202 const u32 mask = OTG_CLK_AHB_EN | OTG_CLK_OTG_EN | 203 OTG_CLK_I2C_EN | OTG_CLK_HOST_EN; 204 writel(mask, &otg->otg_clk_ctrl); 205 206 ret = wait_for_bit(&otg->otg_clk_sts, mask, 1); 207 if (ret) 208 return ret; 209 210 setbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN); 211 isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV); 212 213 return 0; 214 } 215 216 int usb_cpu_stop(void) 217 { 218 /* vbus off */ 219 isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV); 220 221 clrbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN); 222 223 clrbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_HCLK_EN); 224 225 return 0; 226 } 227 228 int usb_cpu_init_fail(void) 229 { 230 return usb_cpu_stop(); 231 } 232