1 /* 2 * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus. 3 * 4 * Interrupt support is added. Now, it has been tested 5 * on ULI1575 chip and works well with USB keyboard. 6 * 7 * (C) Copyright 2007 8 * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com> 9 * 10 * (C) Copyright 2003 11 * Gary Jennejohn, DENX Software Engineering <garyj@denx.de> 12 * 13 * Note: Much of this code has been derived from Linux 2.4 14 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 15 * (C) Copyright 2000-2002 David Brownell 16 * 17 * Modified for the MP2USB by (C) Copyright 2005 Eric Benard 18 * ebenard@eukrea.com - based on s3c24x0's driver 19 * 20 * SPDX-License-Identifier: GPL-2.0+ 21 */ 22 /* 23 * IMPORTANT NOTES 24 * 1 - Read doc/README.generic_usb_ohci 25 * 2 - this driver is intended for use with USB Mass Storage Devices 26 * (BBB) and USB keyboard. There is NO support for Isochronous pipes! 27 * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG 28 * to activate workaround for bug #41 or this driver will NOT work! 29 */ 30 31 #include <common.h> 32 #include <asm/byteorder.h> 33 #include <dm.h> 34 #include <errno.h> 35 36 #if defined(CONFIG_PCI_OHCI) 37 # include <pci.h> 38 #if !defined(CONFIG_PCI_OHCI_DEVNO) 39 #define CONFIG_PCI_OHCI_DEVNO 0 40 #endif 41 #endif 42 43 #include <malloc.h> 44 #include <memalign.h> 45 #include <usb.h> 46 47 #include "ohci.h" 48 49 #ifdef CONFIG_AT91RM9200 50 #include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */ 51 #endif 52 53 #if defined(CONFIG_CPU_ARM920T) || \ 54 defined(CONFIG_S3C24X0) || \ 55 defined(CONFIG_440EP) || \ 56 defined(CONFIG_PCI_OHCI) || \ 57 defined(CONFIG_MPC5200) || \ 58 defined(CONFIG_SYS_OHCI_USE_NPS) 59 # define OHCI_USE_NPS /* force NoPowerSwitching mode */ 60 #endif 61 62 #undef OHCI_VERBOSE_DEBUG /* not always helpful */ 63 #undef DEBUG 64 #undef SHOW_INFO 65 #undef OHCI_FILL_TRACE 66 67 /* For initializing controller (mask in an HCFS mode too) */ 68 #define OHCI_CONTROL_INIT \ 69 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE 70 71 #ifdef CONFIG_PCI_OHCI 72 static struct pci_device_id ohci_pci_ids[] = { 73 {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ 74 {0x1033, 0x0035}, /* NEC PCI OHCI module ids */ 75 {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */ 76 /* Please add supported PCI OHCI controller ids here */ 77 {0, 0} 78 }; 79 #endif 80 81 #ifdef CONFIG_PCI_EHCI_DEVNO 82 static struct pci_device_id ehci_pci_ids[] = { 83 {0x1131, 0x1562}, /* Philips 1562 PCI EHCI module ids */ 84 /* Please add supported PCI EHCI controller ids here */ 85 {0, 0} 86 }; 87 #endif 88 89 #ifdef DEBUG 90 #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) 91 #else 92 #define dbg(format, arg...) do {} while (0) 93 #endif /* DEBUG */ 94 #define err(format, arg...) printf("ERROR: " format "\n", ## arg) 95 #ifdef SHOW_INFO 96 #define info(format, arg...) printf("INFO: " format "\n", ## arg) 97 #else 98 #define info(format, arg...) do {} while (0) 99 #endif 100 101 #ifdef CONFIG_SYS_OHCI_BE_CONTROLLER 102 # define m16_swap(x) cpu_to_be16(x) 103 # define m32_swap(x) cpu_to_be32(x) 104 #else 105 # define m16_swap(x) cpu_to_le16(x) 106 # define m32_swap(x) cpu_to_le32(x) 107 #endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */ 108 109 /* We really should do proper cache flushing everywhere */ 110 #define flush_dcache_buffer(addr, size) \ 111 flush_dcache_range((unsigned long)(addr), \ 112 ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN)) 113 #define invalidate_dcache_buffer(addr, size) \ 114 invalidate_dcache_range((unsigned long)(addr), \ 115 ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN)) 116 117 /* Do not use sizeof(ed / td) as our ed / td structs contain extra members */ 118 #define flush_dcache_ed(addr) flush_dcache_buffer(addr, 16) 119 #define flush_dcache_td(addr) flush_dcache_buffer(addr, 16) 120 #define flush_dcache_iso_td(addr) flush_dcache_buffer(addr, 32) 121 #define flush_dcache_hcca(addr) flush_dcache_buffer(addr, 256) 122 #define invalidate_dcache_ed(addr) invalidate_dcache_buffer(addr, 16) 123 #define invalidate_dcache_td(addr) invalidate_dcache_buffer(addr, 16) 124 #define invalidate_dcache_iso_td(addr) invalidate_dcache_buffer(addr, 32) 125 #define invalidate_dcache_hcca(addr) invalidate_dcache_buffer(addr, 256) 126 127 #ifdef CONFIG_DM_USB 128 /* 129 * The various ohci_mdelay(1) calls in the code seem unnecessary. We keep 130 * them around when building for older boards not yet converted to the dm 131 * just in case (to avoid regressions), for dm this turns them into nops. 132 */ 133 #define ohci_mdelay(x) 134 #else 135 #define ohci_mdelay(x) mdelay(x) 136 #endif 137 138 #ifndef CONFIG_DM_USB 139 /* global ohci_t */ 140 static ohci_t gohci; 141 /* this must be aligned to a 256 byte boundary */ 142 struct ohci_hcca ghcca[1]; 143 #endif 144 145 /* mapping of the OHCI CC status to error codes */ 146 static int cc_to_error[16] = { 147 /* No Error */ 0, 148 /* CRC Error */ USB_ST_CRC_ERR, 149 /* Bit Stuff */ USB_ST_BIT_ERR, 150 /* Data Togg */ USB_ST_CRC_ERR, 151 /* Stall */ USB_ST_STALLED, 152 /* DevNotResp */ -1, 153 /* PIDCheck */ USB_ST_BIT_ERR, 154 /* UnExpPID */ USB_ST_BIT_ERR, 155 /* DataOver */ USB_ST_BUF_ERR, 156 /* DataUnder */ USB_ST_BUF_ERR, 157 /* reservd */ -1, 158 /* reservd */ -1, 159 /* BufferOver */ USB_ST_BUF_ERR, 160 /* BuffUnder */ USB_ST_BUF_ERR, 161 /* Not Access */ -1, 162 /* Not Access */ -1 163 }; 164 165 static const char *cc_to_string[16] = { 166 "No Error", 167 "CRC: Last data packet from endpoint contained a CRC error.", 168 "BITSTUFFING: Last data packet from endpoint contained a bit " \ 169 "stuffing violation", 170 "DATATOGGLEMISMATCH: Last packet from endpoint had data toggle PID\n" \ 171 "that did not match the expected value.", 172 "STALL: TD was moved to the Done Queue because the endpoint returned" \ 173 " a STALL PID", 174 "DEVICENOTRESPONDING: Device did not respond to token (IN) or did\n" \ 175 "not provide a handshake (OUT)", 176 "PIDCHECKFAILURE: Check bits on PID from endpoint failed on data PID\n"\ 177 "(IN) or handshake (OUT)", 178 "UNEXPECTEDPID: Receive PID was not valid when encountered or PID\n" \ 179 "value is not defined.", 180 "DATAOVERRUN: The amount of data returned by the endpoint exceeded\n" \ 181 "either the size of the maximum data packet allowed\n" \ 182 "from the endpoint (found in MaximumPacketSize field\n" \ 183 "of ED) or the remaining buffer size.", 184 "DATAUNDERRUN: The endpoint returned less than MaximumPacketSize\n" \ 185 "and that amount was not sufficient to fill the\n" \ 186 "specified buffer", 187 "reserved1", 188 "reserved2", 189 "BUFFEROVERRUN: During an IN, HC received data from endpoint faster\n" \ 190 "than it could be written to system memory", 191 "BUFFERUNDERRUN: During an OUT, HC could not retrieve data from\n" \ 192 "system memory fast enough to keep up with data USB " \ 193 "data rate.", 194 "NOT ACCESSED: This code is set by software before the TD is placed" \ 195 "on a list to be processed by the HC.(1)", 196 "NOT ACCESSED: This code is set by software before the TD is placed" \ 197 "on a list to be processed by the HC.(2)", 198 }; 199 200 static inline u32 roothub_a(struct ohci *hc) 201 { return ohci_readl(&hc->regs->roothub.a); } 202 static inline u32 roothub_b(struct ohci *hc) 203 { return ohci_readl(&hc->regs->roothub.b); } 204 static inline u32 roothub_status(struct ohci *hc) 205 { return ohci_readl(&hc->regs->roothub.status); } 206 static inline u32 roothub_portstatus(struct ohci *hc, int i) 207 { return ohci_readl(&hc->regs->roothub.portstatus[i]); } 208 209 /* forward declaration */ 210 static int hc_interrupt(ohci_t *ohci); 211 static void td_submit_job(ohci_t *ohci, struct usb_device *dev, 212 unsigned long pipe, void *buffer, int transfer_len, 213 struct devrequest *setup, urb_priv_t *urb, 214 int interval); 215 static int ep_link(ohci_t * ohci, ed_t * ed); 216 static int ep_unlink(ohci_t * ohci, ed_t * ed); 217 static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev, 218 unsigned long pipe, int interval, int load); 219 220 /*-------------------------------------------------------------------------*/ 221 222 /* TDs ... */ 223 static struct td *td_alloc(ohci_dev_t *ohci_dev, struct usb_device *usb_dev) 224 { 225 int i; 226 struct td *td; 227 228 td = NULL; 229 for (i = 0; i < NUM_TD; i++) 230 { 231 if (ohci_dev->tds[i].usb_dev == NULL) 232 { 233 td = &ohci_dev->tds[i]; 234 td->usb_dev = usb_dev; 235 break; 236 } 237 } 238 239 return td; 240 } 241 242 static inline void ed_free(struct ed *ed) 243 { 244 ed->usb_dev = NULL; 245 } 246 247 /*-------------------------------------------------------------------------* 248 * URB support functions 249 *-------------------------------------------------------------------------*/ 250 251 /* free HCD-private data associated with this URB */ 252 253 static void urb_free_priv(urb_priv_t *urb) 254 { 255 int i; 256 int last; 257 struct td *td; 258 259 last = urb->length - 1; 260 if (last >= 0) { 261 for (i = 0; i <= last; i++) { 262 td = urb->td[i]; 263 if (td) { 264 td->usb_dev = NULL; 265 urb->td[i] = NULL; 266 } 267 } 268 } 269 free(urb); 270 } 271 272 /*-------------------------------------------------------------------------*/ 273 274 #ifdef DEBUG 275 static int sohci_get_current_frame_number(ohci_t *ohci); 276 277 /* debug| print the main components of an URB 278 * small: 0) header + data packets 1) just header */ 279 280 static void pkt_print(ohci_t *ohci, urb_priv_t *purb, struct usb_device *dev, 281 unsigned long pipe, void *buffer, int transfer_len, 282 struct devrequest *setup, char *str, int small) 283 { 284 dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx", 285 str, 286 sohci_get_current_frame_number(ohci), 287 usb_pipedevice(pipe), 288 usb_pipeendpoint(pipe), 289 usb_pipeout(pipe)? 'O': 'I', 290 usb_pipetype(pipe) < 2 ? \ 291 (usb_pipeint(pipe)? "INTR": "ISOC"): \ 292 (usb_pipecontrol(pipe)? "CTRL": "BULK"), 293 (purb ? purb->actual_length : 0), 294 transfer_len, dev->status); 295 #ifdef OHCI_VERBOSE_DEBUG 296 if (!small) { 297 int i, len; 298 299 if (usb_pipecontrol(pipe)) { 300 printf(__FILE__ ": cmd(8):"); 301 for (i = 0; i < 8 ; i++) 302 printf(" %02x", ((__u8 *) setup) [i]); 303 printf("\n"); 304 } 305 if (transfer_len > 0 && buffer) { 306 printf(__FILE__ ": data(%d/%d):", 307 (purb ? purb->actual_length : 0), 308 transfer_len); 309 len = usb_pipeout(pipe)? transfer_len: 310 (purb ? purb->actual_length : 0); 311 for (i = 0; i < 16 && i < len; i++) 312 printf(" %02x", ((__u8 *) buffer) [i]); 313 printf("%s\n", i < len? "...": ""); 314 } 315 } 316 #endif 317 } 318 319 /* just for debugging; prints non-empty branches of the int ed tree 320 * inclusive iso eds */ 321 void ep_print_int_eds(ohci_t *ohci, char *str) 322 { 323 int i, j; 324 __u32 *ed_p; 325 for (i = 0; i < 32; i++) { 326 j = 5; 327 ed_p = &(ohci->hcca->int_table [i]); 328 if (*ed_p == 0) 329 continue; 330 invalidate_dcache_ed(ed_p); 331 printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i); 332 while (*ed_p != 0 && j--) { 333 ed_t *ed = (ed_t *)m32_swap(ed_p); 334 invalidate_dcache_ed(ed); 335 printf(" ed: %4x;", ed->hwINFO); 336 ed_p = &ed->hwNextED; 337 } 338 printf("\n"); 339 } 340 } 341 342 static void ohci_dump_intr_mask(char *label, __u32 mask) 343 { 344 dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s", 345 label, 346 mask, 347 (mask & OHCI_INTR_MIE) ? " MIE" : "", 348 (mask & OHCI_INTR_OC) ? " OC" : "", 349 (mask & OHCI_INTR_RHSC) ? " RHSC" : "", 350 (mask & OHCI_INTR_FNO) ? " FNO" : "", 351 (mask & OHCI_INTR_UE) ? " UE" : "", 352 (mask & OHCI_INTR_RD) ? " RD" : "", 353 (mask & OHCI_INTR_SF) ? " SF" : "", 354 (mask & OHCI_INTR_WDH) ? " WDH" : "", 355 (mask & OHCI_INTR_SO) ? " SO" : "" 356 ); 357 } 358 359 static void maybe_print_eds(char *label, __u32 value) 360 { 361 ed_t *edp = (ed_t *)value; 362 363 if (value) { 364 dbg("%s %08x", label, value); 365 invalidate_dcache_ed(edp); 366 dbg("%08x", edp->hwINFO); 367 dbg("%08x", edp->hwTailP); 368 dbg("%08x", edp->hwHeadP); 369 dbg("%08x", edp->hwNextED); 370 } 371 } 372 373 static char *hcfs2string(int state) 374 { 375 switch (state) { 376 case OHCI_USB_RESET: return "reset"; 377 case OHCI_USB_RESUME: return "resume"; 378 case OHCI_USB_OPER: return "operational"; 379 case OHCI_USB_SUSPEND: return "suspend"; 380 } 381 return "?"; 382 } 383 384 /* dump control and status registers */ 385 static void ohci_dump_status(ohci_t *controller) 386 { 387 struct ohci_regs *regs = controller->regs; 388 __u32 temp; 389 390 temp = ohci_readl(®s->revision) & 0xff; 391 if (temp != 0x10) 392 dbg("spec %d.%d", (temp >> 4), (temp & 0x0f)); 393 394 temp = ohci_readl(®s->control); 395 dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, 396 (temp & OHCI_CTRL_RWE) ? " RWE" : "", 397 (temp & OHCI_CTRL_RWC) ? " RWC" : "", 398 (temp & OHCI_CTRL_IR) ? " IR" : "", 399 hcfs2string(temp & OHCI_CTRL_HCFS), 400 (temp & OHCI_CTRL_BLE) ? " BLE" : "", 401 (temp & OHCI_CTRL_CLE) ? " CLE" : "", 402 (temp & OHCI_CTRL_IE) ? " IE" : "", 403 (temp & OHCI_CTRL_PLE) ? " PLE" : "", 404 temp & OHCI_CTRL_CBSR 405 ); 406 407 temp = ohci_readl(®s->cmdstatus); 408 dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, 409 (temp & OHCI_SOC) >> 16, 410 (temp & OHCI_OCR) ? " OCR" : "", 411 (temp & OHCI_BLF) ? " BLF" : "", 412 (temp & OHCI_CLF) ? " CLF" : "", 413 (temp & OHCI_HCR) ? " HCR" : "" 414 ); 415 416 ohci_dump_intr_mask("intrstatus", ohci_readl(®s->intrstatus)); 417 ohci_dump_intr_mask("intrenable", ohci_readl(®s->intrenable)); 418 419 maybe_print_eds("ed_periodcurrent", 420 ohci_readl(®s->ed_periodcurrent)); 421 422 maybe_print_eds("ed_controlhead", ohci_readl(®s->ed_controlhead)); 423 maybe_print_eds("ed_controlcurrent", 424 ohci_readl(®s->ed_controlcurrent)); 425 426 maybe_print_eds("ed_bulkhead", ohci_readl(®s->ed_bulkhead)); 427 maybe_print_eds("ed_bulkcurrent", ohci_readl(®s->ed_bulkcurrent)); 428 429 maybe_print_eds("donehead", ohci_readl(®s->donehead)); 430 } 431 432 static void ohci_dump_roothub(ohci_t *controller, int verbose) 433 { 434 __u32 temp, ndp, i; 435 436 temp = roothub_a(controller); 437 ndp = (temp & RH_A_NDP); 438 #ifdef CONFIG_AT91C_PQFP_UHPBUG 439 ndp = (ndp == 2) ? 1:0; 440 #endif 441 if (verbose) { 442 dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, 443 ((temp & RH_A_POTPGT) >> 24) & 0xff, 444 (temp & RH_A_NOCP) ? " NOCP" : "", 445 (temp & RH_A_OCPM) ? " OCPM" : "", 446 (temp & RH_A_DT) ? " DT" : "", 447 (temp & RH_A_NPS) ? " NPS" : "", 448 (temp & RH_A_PSM) ? " PSM" : "", 449 ndp 450 ); 451 temp = roothub_b(controller); 452 dbg("roothub.b: %08x PPCM=%04x DR=%04x", 453 temp, 454 (temp & RH_B_PPCM) >> 16, 455 (temp & RH_B_DR) 456 ); 457 temp = roothub_status(controller); 458 dbg("roothub.status: %08x%s%s%s%s%s%s", 459 temp, 460 (temp & RH_HS_CRWE) ? " CRWE" : "", 461 (temp & RH_HS_OCIC) ? " OCIC" : "", 462 (temp & RH_HS_LPSC) ? " LPSC" : "", 463 (temp & RH_HS_DRWE) ? " DRWE" : "", 464 (temp & RH_HS_OCI) ? " OCI" : "", 465 (temp & RH_HS_LPS) ? " LPS" : "" 466 ); 467 } 468 469 for (i = 0; i < ndp; i++) { 470 temp = roothub_portstatus(controller, i); 471 dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", 472 i, 473 temp, 474 (temp & RH_PS_PRSC) ? " PRSC" : "", 475 (temp & RH_PS_OCIC) ? " OCIC" : "", 476 (temp & RH_PS_PSSC) ? " PSSC" : "", 477 (temp & RH_PS_PESC) ? " PESC" : "", 478 (temp & RH_PS_CSC) ? " CSC" : "", 479 480 (temp & RH_PS_LSDA) ? " LSDA" : "", 481 (temp & RH_PS_PPS) ? " PPS" : "", 482 (temp & RH_PS_PRS) ? " PRS" : "", 483 (temp & RH_PS_POCI) ? " POCI" : "", 484 (temp & RH_PS_PSS) ? " PSS" : "", 485 486 (temp & RH_PS_PES) ? " PES" : "", 487 (temp & RH_PS_CCS) ? " CCS" : "" 488 ); 489 } 490 } 491 492 static void ohci_dump(ohci_t *controller, int verbose) 493 { 494 dbg("OHCI controller usb-%s state", controller->slot_name); 495 496 /* dumps some of the state we know about */ 497 ohci_dump_status(controller); 498 if (verbose) 499 ep_print_int_eds(controller, "hcca"); 500 invalidate_dcache_hcca(controller->hcca); 501 dbg("hcca frame #%04x", controller->hcca->frame_no); 502 ohci_dump_roothub(controller, 1); 503 } 504 #endif /* DEBUG */ 505 506 /*-------------------------------------------------------------------------* 507 * Interface functions (URB) 508 *-------------------------------------------------------------------------*/ 509 510 /* get a transfer request */ 511 512 int sohci_submit_job(ohci_t *ohci, ohci_dev_t *ohci_dev, urb_priv_t *urb, 513 struct devrequest *setup) 514 { 515 ed_t *ed; 516 urb_priv_t *purb_priv = urb; 517 int i, size = 0; 518 struct usb_device *dev = urb->dev; 519 unsigned long pipe = urb->pipe; 520 void *buffer = urb->transfer_buffer; 521 int transfer_len = urb->transfer_buffer_length; 522 int interval = urb->interval; 523 524 /* when controller's hung, permit only roothub cleanup attempts 525 * such as powering down ports */ 526 if (ohci->disabled) { 527 err("sohci_submit_job: EPIPE"); 528 return -1; 529 } 530 531 /* we're about to begin a new transaction here so mark the 532 * URB unfinished */ 533 urb->finished = 0; 534 535 /* every endpoint has a ed, locate and fill it */ 536 ed = ep_add_ed(ohci_dev, dev, pipe, interval, 1); 537 if (!ed) { 538 err("sohci_submit_job: ENOMEM"); 539 return -1; 540 } 541 542 /* for the private part of the URB we need the number of TDs (size) */ 543 switch (usb_pipetype(pipe)) { 544 case PIPE_BULK: /* one TD for every 4096 Byte */ 545 size = (transfer_len - 1) / 4096 + 1; 546 break; 547 case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ 548 size = (transfer_len == 0)? 2: 549 (transfer_len - 1) / 4096 + 3; 550 break; 551 case PIPE_INTERRUPT: /* 1 TD */ 552 size = 1; 553 break; 554 } 555 556 ed->purb = urb; 557 558 if (size >= (N_URB_TD - 1)) { 559 err("need %d TDs, only have %d", size, N_URB_TD); 560 return -1; 561 } 562 purb_priv->pipe = pipe; 563 564 /* fill the private part of the URB */ 565 purb_priv->length = size; 566 purb_priv->ed = ed; 567 purb_priv->actual_length = 0; 568 569 /* allocate the TDs */ 570 /* note that td[0] was allocated in ep_add_ed */ 571 for (i = 0; i < size; i++) { 572 purb_priv->td[i] = td_alloc(ohci_dev, dev); 573 if (!purb_priv->td[i]) { 574 purb_priv->length = i; 575 urb_free_priv(purb_priv); 576 err("sohci_submit_job: ENOMEM"); 577 return -1; 578 } 579 } 580 581 if (ed->state == ED_NEW || (ed->state & ED_DEL)) { 582 urb_free_priv(purb_priv); 583 err("sohci_submit_job: EINVAL"); 584 return -1; 585 } 586 587 /* link the ed into a chain if is not already */ 588 if (ed->state != ED_OPER) 589 ep_link(ohci, ed); 590 591 /* fill the TDs and link it to the ed */ 592 td_submit_job(ohci, dev, pipe, buffer, transfer_len, 593 setup, purb_priv, interval); 594 595 return 0; 596 } 597 598 /*-------------------------------------------------------------------------*/ 599 600 #ifdef DEBUG 601 /* tell us the current USB frame number */ 602 static int sohci_get_current_frame_number(ohci_t *ohci) 603 { 604 invalidate_dcache_hcca(ohci->hcca); 605 return m16_swap(ohci->hcca->frame_no); 606 } 607 #endif 608 609 /*-------------------------------------------------------------------------* 610 * ED handling functions 611 *-------------------------------------------------------------------------*/ 612 613 /* search for the right branch to insert an interrupt ed into the int tree 614 * do some load ballancing; 615 * returns the branch and 616 * sets the interval to interval = 2^integer (ld (interval)) */ 617 618 static int ep_int_ballance(ohci_t *ohci, int interval, int load) 619 { 620 int i, branch = 0; 621 622 /* search for the least loaded interrupt endpoint 623 * branch of all 32 branches 624 */ 625 for (i = 0; i < 32; i++) 626 if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i]) 627 branch = i; 628 629 branch = branch % interval; 630 for (i = branch; i < 32; i += interval) 631 ohci->ohci_int_load [i] += load; 632 633 return branch; 634 } 635 636 /*-------------------------------------------------------------------------*/ 637 638 /* 2^int( ld (inter)) */ 639 640 static int ep_2_n_interval(int inter) 641 { 642 int i; 643 for (i = 0; ((inter >> i) > 1) && (i < 5); i++); 644 return 1 << i; 645 } 646 647 /*-------------------------------------------------------------------------*/ 648 649 /* the int tree is a binary tree 650 * in order to process it sequentially the indexes of the branches have to 651 * be mapped the mapping reverses the bits of a word of num_bits length */ 652 static int ep_rev(int num_bits, int word) 653 { 654 int i, wout = 0; 655 656 for (i = 0; i < num_bits; i++) 657 wout |= (((word >> i) & 1) << (num_bits - i - 1)); 658 return wout; 659 } 660 661 /*-------------------------------------------------------------------------* 662 * ED handling functions 663 *-------------------------------------------------------------------------*/ 664 665 /* link an ed into one of the HC chains */ 666 667 static int ep_link(ohci_t *ohci, ed_t *edi) 668 { 669 volatile ed_t *ed = edi; 670 int int_branch; 671 int i; 672 int inter; 673 int interval; 674 int load; 675 __u32 *ed_p; 676 677 ed->state = ED_OPER; 678 ed->int_interval = 0; 679 680 switch (ed->type) { 681 case PIPE_CONTROL: 682 ed->hwNextED = 0; 683 flush_dcache_ed(ed); 684 if (ohci->ed_controltail == NULL) 685 ohci_writel(ed, &ohci->regs->ed_controlhead); 686 else 687 ohci->ed_controltail->hwNextED = 688 m32_swap((unsigned long)ed); 689 690 ed->ed_prev = ohci->ed_controltail; 691 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && 692 !ohci->ed_rm_list[1] && !ohci->sleeping) { 693 ohci->hc_control |= OHCI_CTRL_CLE; 694 ohci_writel(ohci->hc_control, &ohci->regs->control); 695 } 696 ohci->ed_controltail = edi; 697 break; 698 699 case PIPE_BULK: 700 ed->hwNextED = 0; 701 flush_dcache_ed(ed); 702 if (ohci->ed_bulktail == NULL) 703 ohci_writel(ed, &ohci->regs->ed_bulkhead); 704 else 705 ohci->ed_bulktail->hwNextED = 706 m32_swap((unsigned long)ed); 707 708 ed->ed_prev = ohci->ed_bulktail; 709 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && 710 !ohci->ed_rm_list[1] && !ohci->sleeping) { 711 ohci->hc_control |= OHCI_CTRL_BLE; 712 ohci_writel(ohci->hc_control, &ohci->regs->control); 713 } 714 ohci->ed_bulktail = edi; 715 break; 716 717 case PIPE_INTERRUPT: 718 load = ed->int_load; 719 interval = ep_2_n_interval(ed->int_period); 720 ed->int_interval = interval; 721 int_branch = ep_int_ballance(ohci, interval, load); 722 ed->int_branch = int_branch; 723 724 for (i = 0; i < ep_rev(6, interval); i += inter) { 725 inter = 1; 726 for (ed_p = &(ohci->hcca->int_table[\ 727 ep_rev(5, i) + int_branch]); 728 (*ed_p != 0) && 729 (((ed_t *)ed_p)->int_interval >= interval); 730 ed_p = &(((ed_t *)ed_p)->hwNextED)) 731 inter = ep_rev(6, 732 ((ed_t *)ed_p)->int_interval); 733 ed->hwNextED = *ed_p; 734 flush_dcache_ed(ed); 735 *ed_p = m32_swap((unsigned long)ed); 736 flush_dcache_hcca(ohci->hcca); 737 } 738 break; 739 } 740 return 0; 741 } 742 743 /*-------------------------------------------------------------------------*/ 744 745 /* scan the periodic table to find and unlink this ED */ 746 static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed, 747 unsigned index, unsigned period) 748 { 749 __maybe_unused unsigned long aligned_ed_p; 750 751 for (; index < NUM_INTS; index += period) { 752 __u32 *ed_p = &ohci->hcca->int_table [index]; 753 754 /* ED might have been unlinked through another path */ 755 while (*ed_p != 0) { 756 if (((struct ed *) 757 m32_swap((unsigned long)ed_p)) == ed) { 758 *ed_p = ed->hwNextED; 759 aligned_ed_p = (unsigned long)ed_p; 760 aligned_ed_p &= ~(ARCH_DMA_MINALIGN - 1); 761 flush_dcache_range(aligned_ed_p, 762 aligned_ed_p + ARCH_DMA_MINALIGN); 763 break; 764 } 765 ed_p = &(((struct ed *) 766 m32_swap((unsigned long)ed_p))->hwNextED); 767 } 768 } 769 } 770 771 /* unlink an ed from one of the HC chains. 772 * just the link to the ed is unlinked. 773 * the link from the ed still points to another operational ed or 0 774 * so the HC can eventually finish the processing of the unlinked ed */ 775 776 static int ep_unlink(ohci_t *ohci, ed_t *edi) 777 { 778 volatile ed_t *ed = edi; 779 int i; 780 781 ed->hwINFO |= m32_swap(OHCI_ED_SKIP); 782 flush_dcache_ed(ed); 783 784 switch (ed->type) { 785 case PIPE_CONTROL: 786 if (ed->ed_prev == NULL) { 787 if (!ed->hwNextED) { 788 ohci->hc_control &= ~OHCI_CTRL_CLE; 789 ohci_writel(ohci->hc_control, 790 &ohci->regs->control); 791 } 792 ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)), 793 &ohci->regs->ed_controlhead); 794 } else { 795 ed->ed_prev->hwNextED = ed->hwNextED; 796 flush_dcache_ed(ed->ed_prev); 797 } 798 if (ohci->ed_controltail == ed) { 799 ohci->ed_controltail = ed->ed_prev; 800 } else { 801 ((ed_t *)m32_swap( 802 *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; 803 } 804 break; 805 806 case PIPE_BULK: 807 if (ed->ed_prev == NULL) { 808 if (!ed->hwNextED) { 809 ohci->hc_control &= ~OHCI_CTRL_BLE; 810 ohci_writel(ohci->hc_control, 811 &ohci->regs->control); 812 } 813 ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)), 814 &ohci->regs->ed_bulkhead); 815 } else { 816 ed->ed_prev->hwNextED = ed->hwNextED; 817 flush_dcache_ed(ed->ed_prev); 818 } 819 if (ohci->ed_bulktail == ed) { 820 ohci->ed_bulktail = ed->ed_prev; 821 } else { 822 ((ed_t *)m32_swap( 823 *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; 824 } 825 break; 826 827 case PIPE_INTERRUPT: 828 periodic_unlink(ohci, ed, 0, 1); 829 for (i = ed->int_branch; i < 32; i += ed->int_interval) 830 ohci->ohci_int_load[i] -= ed->int_load; 831 break; 832 } 833 ed->state = ED_UNLINK; 834 return 0; 835 } 836 837 /*-------------------------------------------------------------------------*/ 838 839 /* add/reinit an endpoint; this should be done once at the 840 * usb_set_configuration command, but the USB stack is a little bit 841 * stateless so we do it at every transaction if the state of the ed 842 * is ED_NEW then a dummy td is added and the state is changed to 843 * ED_UNLINK in all other cases the state is left unchanged the ed 844 * info fields are setted anyway even though most of them should not 845 * change 846 */ 847 static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev, 848 unsigned long pipe, int interval, int load) 849 { 850 td_t *td; 851 ed_t *ed_ret; 852 volatile ed_t *ed; 853 854 ed = ed_ret = &ohci_dev->ed[(usb_pipeendpoint(pipe) << 1) | 855 (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))]; 856 857 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { 858 err("ep_add_ed: pending delete"); 859 /* pending delete request */ 860 return NULL; 861 } 862 863 if (ed->state == ED_NEW) { 864 /* dummy td; end of td list for ed */ 865 td = td_alloc(ohci_dev, usb_dev); 866 ed->hwTailP = m32_swap((unsigned long)td); 867 ed->hwHeadP = ed->hwTailP; 868 ed->state = ED_UNLINK; 869 ed->type = usb_pipetype(pipe); 870 ohci_dev->ed_cnt++; 871 } 872 873 ed->hwINFO = m32_swap(usb_pipedevice(pipe) 874 | usb_pipeendpoint(pipe) << 7 875 | (usb_pipeisoc(pipe)? 0x8000: 0) 876 | (usb_pipecontrol(pipe)? 0: \ 877 (usb_pipeout(pipe)? 0x800: 0x1000)) 878 | (usb_dev->speed == USB_SPEED_LOW) << 13 879 | usb_maxpacket(usb_dev, pipe) << 16); 880 881 if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) { 882 ed->int_period = interval; 883 ed->int_load = load; 884 } 885 886 flush_dcache_ed(ed); 887 888 return ed_ret; 889 } 890 891 /*-------------------------------------------------------------------------* 892 * TD handling functions 893 *-------------------------------------------------------------------------*/ 894 895 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ 896 897 static void td_fill(ohci_t *ohci, unsigned int info, 898 void *data, int len, 899 struct usb_device *dev, int index, urb_priv_t *urb_priv) 900 { 901 volatile td_t *td, *td_pt; 902 #ifdef OHCI_FILL_TRACE 903 int i; 904 #endif 905 906 if (index > urb_priv->length) { 907 err("index > length"); 908 return; 909 } 910 /* use this td as the next dummy */ 911 td_pt = urb_priv->td [index]; 912 td_pt->hwNextTD = 0; 913 flush_dcache_td(td_pt); 914 915 /* fill the old dummy TD */ 916 td = urb_priv->td [index] = 917 (td_t *)(m32_swap(urb_priv->ed->hwTailP) & ~0xf); 918 919 td->ed = urb_priv->ed; 920 td->next_dl_td = NULL; 921 td->index = index; 922 td->data = (__u32)data; 923 #ifdef OHCI_FILL_TRACE 924 if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) { 925 for (i = 0; i < len; i++) 926 printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]); 927 printf("\n"); 928 } 929 #endif 930 if (!len) 931 data = 0; 932 933 td->hwINFO = m32_swap(info); 934 td->hwCBP = m32_swap((unsigned long)data); 935 if (data) 936 td->hwBE = m32_swap((unsigned long)(data + len - 1)); 937 else 938 td->hwBE = 0; 939 940 td->hwNextTD = m32_swap((unsigned long)td_pt); 941 flush_dcache_td(td); 942 943 /* append to queue */ 944 td->ed->hwTailP = td->hwNextTD; 945 flush_dcache_ed(td->ed); 946 } 947 948 /*-------------------------------------------------------------------------*/ 949 950 /* prepare all TDs of a transfer */ 951 952 static void td_submit_job(ohci_t *ohci, struct usb_device *dev, 953 unsigned long pipe, void *buffer, int transfer_len, 954 struct devrequest *setup, urb_priv_t *urb, 955 int interval) 956 { 957 int data_len = transfer_len; 958 void *data; 959 int cnt = 0; 960 __u32 info = 0; 961 unsigned int toggle = 0; 962 963 flush_dcache_buffer(buffer, data_len); 964 965 /* OHCI handles the DATA-toggles itself, we just use the USB-toggle 966 * bits for reseting */ 967 if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { 968 toggle = TD_T_TOGGLE; 969 } else { 970 toggle = TD_T_DATA0; 971 usb_settoggle(dev, usb_pipeendpoint(pipe), 972 usb_pipeout(pipe), 1); 973 } 974 urb->td_cnt = 0; 975 if (data_len) 976 data = buffer; 977 else 978 data = 0; 979 980 switch (usb_pipetype(pipe)) { 981 case PIPE_BULK: 982 info = usb_pipeout(pipe)? 983 TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; 984 while (data_len > 4096) { 985 td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), 986 data, 4096, dev, cnt, urb); 987 data += 4096; data_len -= 4096; cnt++; 988 } 989 info = usb_pipeout(pipe)? 990 TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; 991 td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 992 data_len, dev, cnt, urb); 993 cnt++; 994 995 if (!ohci->sleeping) { 996 /* start bulk list */ 997 ohci_writel(OHCI_BLF, &ohci->regs->cmdstatus); 998 } 999 break; 1000 1001 case PIPE_CONTROL: 1002 /* Setup phase */ 1003 info = TD_CC | TD_DP_SETUP | TD_T_DATA0; 1004 flush_dcache_buffer(setup, 8); 1005 td_fill(ohci, info, setup, 8, dev, cnt++, urb); 1006 1007 /* Optional Data phase */ 1008 if (data_len > 0) { 1009 info = usb_pipeout(pipe)? 1010 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : 1011 TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; 1012 /* NOTE: mishandles transfers >8K, some >4K */ 1013 td_fill(ohci, info, data, data_len, dev, cnt++, urb); 1014 } 1015 1016 /* Status phase */ 1017 info = (usb_pipeout(pipe) || data_len == 0) ? 1018 TD_CC | TD_DP_IN | TD_T_DATA1: 1019 TD_CC | TD_DP_OUT | TD_T_DATA1; 1020 td_fill(ohci, info, data, 0, dev, cnt++, urb); 1021 1022 if (!ohci->sleeping) { 1023 /* start Control list */ 1024 ohci_writel(OHCI_CLF, &ohci->regs->cmdstatus); 1025 } 1026 break; 1027 1028 case PIPE_INTERRUPT: 1029 info = usb_pipeout(urb->pipe)? 1030 TD_CC | TD_DP_OUT | toggle: 1031 TD_CC | TD_R | TD_DP_IN | toggle; 1032 td_fill(ohci, info, data, data_len, dev, cnt++, urb); 1033 break; 1034 } 1035 if (urb->length != cnt) 1036 dbg("TD LENGTH %d != CNT %d", urb->length, cnt); 1037 } 1038 1039 /*-------------------------------------------------------------------------* 1040 * Done List handling functions 1041 *-------------------------------------------------------------------------*/ 1042 1043 /* calculate the transfer length and update the urb */ 1044 1045 static void dl_transfer_length(td_t *td) 1046 { 1047 __u32 tdBE, tdCBP; 1048 urb_priv_t *lurb_priv = td->ed->purb; 1049 1050 tdBE = m32_swap(td->hwBE); 1051 tdCBP = m32_swap(td->hwCBP); 1052 1053 if (!(usb_pipecontrol(lurb_priv->pipe) && 1054 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { 1055 if (tdBE != 0) { 1056 if (td->hwCBP == 0) 1057 lurb_priv->actual_length += tdBE - td->data + 1; 1058 else 1059 lurb_priv->actual_length += tdCBP - td->data; 1060 } 1061 } 1062 } 1063 1064 /*-------------------------------------------------------------------------*/ 1065 static void check_status(td_t *td_list) 1066 { 1067 urb_priv_t *lurb_priv = td_list->ed->purb; 1068 int urb_len = lurb_priv->length; 1069 __u32 *phwHeadP = &td_list->ed->hwHeadP; 1070 int cc; 1071 1072 cc = TD_CC_GET(m32_swap(td_list->hwINFO)); 1073 if (cc) { 1074 err(" USB-error: %s (%x)", cc_to_string[cc], cc); 1075 1076 invalidate_dcache_ed(td_list->ed); 1077 if (*phwHeadP & m32_swap(0x1)) { 1078 if (lurb_priv && 1079 ((td_list->index + 1) < urb_len)) { 1080 *phwHeadP = 1081 (lurb_priv->td[urb_len - 1]->hwNextTD &\ 1082 m32_swap(0xfffffff0)) | 1083 (*phwHeadP & m32_swap(0x2)); 1084 1085 lurb_priv->td_cnt += urb_len - 1086 td_list->index - 1; 1087 } else 1088 *phwHeadP &= m32_swap(0xfffffff2); 1089 flush_dcache_ed(td_list->ed); 1090 } 1091 #ifdef CONFIG_MPC5200 1092 td_list->hwNextTD = 0; 1093 flush_dcache_td(td_list); 1094 #endif 1095 } 1096 } 1097 1098 /* replies to the request have to be on a FIFO basis so 1099 * we reverse the reversed done-list */ 1100 static td_t *dl_reverse_done_list(ohci_t *ohci) 1101 { 1102 __u32 td_list_hc; 1103 td_t *td_rev = NULL; 1104 td_t *td_list = NULL; 1105 1106 invalidate_dcache_hcca(ohci->hcca); 1107 td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0; 1108 ohci->hcca->done_head = 0; 1109 flush_dcache_hcca(ohci->hcca); 1110 1111 while (td_list_hc) { 1112 td_list = (td_t *)td_list_hc; 1113 invalidate_dcache_td(td_list); 1114 check_status(td_list); 1115 td_list->next_dl_td = td_rev; 1116 td_rev = td_list; 1117 td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0; 1118 } 1119 return td_list; 1120 } 1121 1122 /*-------------------------------------------------------------------------*/ 1123 /*-------------------------------------------------------------------------*/ 1124 1125 static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status) 1126 { 1127 if ((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL)) 1128 urb->finished = 1; 1129 else 1130 dbg("finish_urb: strange.., ED state %x, \n", status); 1131 } 1132 1133 /* 1134 * Used to take back a TD from the host controller. This would normally be 1135 * called from within dl_done_list, however it may be called directly if the 1136 * HC no longer sees the TD and it has not appeared on the donelist (after 1137 * two frames). This bug has been observed on ZF Micro systems. 1138 */ 1139 static int takeback_td(ohci_t *ohci, td_t *td_list) 1140 { 1141 ed_t *ed; 1142 int cc; 1143 int stat = 0; 1144 /* urb_t *urb; */ 1145 urb_priv_t *lurb_priv; 1146 __u32 tdINFO, edHeadP, edTailP; 1147 1148 invalidate_dcache_td(td_list); 1149 tdINFO = m32_swap(td_list->hwINFO); 1150 1151 ed = td_list->ed; 1152 lurb_priv = ed->purb; 1153 1154 dl_transfer_length(td_list); 1155 1156 lurb_priv->td_cnt++; 1157 1158 /* error code of transfer */ 1159 cc = TD_CC_GET(tdINFO); 1160 if (cc) { 1161 err("USB-error: %s (%x)", cc_to_string[cc], cc); 1162 stat = cc_to_error[cc]; 1163 } 1164 1165 /* see if this done list makes for all TD's of current URB, 1166 * and mark the URB finished if so */ 1167 if (lurb_priv->td_cnt == lurb_priv->length) 1168 finish_urb(ohci, lurb_priv, ed->state); 1169 1170 dbg("dl_done_list: processing TD %x, len %x\n", 1171 lurb_priv->td_cnt, lurb_priv->length); 1172 1173 if (ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) { 1174 invalidate_dcache_ed(ed); 1175 edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0; 1176 edTailP = m32_swap(ed->hwTailP); 1177 1178 /* unlink eds if they are not busy */ 1179 if ((edHeadP == edTailP) && (ed->state == ED_OPER)) 1180 ep_unlink(ohci, ed); 1181 } 1182 return stat; 1183 } 1184 1185 static int dl_done_list(ohci_t *ohci) 1186 { 1187 int stat = 0; 1188 td_t *td_list = dl_reverse_done_list(ohci); 1189 1190 while (td_list) { 1191 td_t *td_next = td_list->next_dl_td; 1192 stat = takeback_td(ohci, td_list); 1193 td_list = td_next; 1194 } 1195 return stat; 1196 } 1197 1198 /*-------------------------------------------------------------------------* 1199 * Virtual Root Hub 1200 *-------------------------------------------------------------------------*/ 1201 1202 #include <usbroothubdes.h> 1203 1204 /* Hub class-specific descriptor is constructed dynamically */ 1205 1206 /*-------------------------------------------------------------------------*/ 1207 1208 #define OK(x) len = (x); break 1209 #ifdef DEBUG 1210 #define WR_RH_STAT(x) {info("WR:status %#8x", (x)); ohci_writel((x), \ 1211 &ohci->regs->roothub.status); } 1212 #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, \ 1213 (x)); ohci_writel((x), &ohci->regs->roothub.portstatus[wIndex-1]); } 1214 #else 1215 #define WR_RH_STAT(x) ohci_writel((x), &ohci->regs->roothub.status) 1216 #define WR_RH_PORTSTAT(x) ohci_writel((x), \ 1217 &ohci->regs->roothub.portstatus[wIndex-1]) 1218 #endif 1219 #define RD_RH_STAT roothub_status(ohci) 1220 #define RD_RH_PORTSTAT roothub_portstatus(ohci, wIndex-1) 1221 1222 /* request to virtual root hub */ 1223 1224 int rh_check_port_status(ohci_t *controller) 1225 { 1226 __u32 temp, ndp, i; 1227 int res; 1228 1229 res = -1; 1230 temp = roothub_a(controller); 1231 ndp = (temp & RH_A_NDP); 1232 #ifdef CONFIG_AT91C_PQFP_UHPBUG 1233 ndp = (ndp == 2) ? 1:0; 1234 #endif 1235 for (i = 0; i < ndp; i++) { 1236 temp = roothub_portstatus(controller, i); 1237 /* check for a device disconnect */ 1238 if (((temp & (RH_PS_PESC | RH_PS_CSC)) == 1239 (RH_PS_PESC | RH_PS_CSC)) && 1240 ((temp & RH_PS_CCS) == 0)) { 1241 res = i; 1242 break; 1243 } 1244 } 1245 return res; 1246 } 1247 1248 static int ohci_submit_rh_msg(ohci_t *ohci, struct usb_device *dev, 1249 unsigned long pipe, void *buffer, int transfer_len, 1250 struct devrequest *cmd) 1251 { 1252 void *data = buffer; 1253 int leni = transfer_len; 1254 int len = 0; 1255 int stat = 0; 1256 __u16 bmRType_bReq; 1257 __u16 wValue; 1258 __u16 wIndex; 1259 __u16 wLength; 1260 ALLOC_ALIGN_BUFFER(__u8, databuf, 16, sizeof(u32)); 1261 1262 #ifdef DEBUG 1263 pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len, 1264 cmd, "SUB(rh)", usb_pipein(pipe)); 1265 #else 1266 ohci_mdelay(1); 1267 #endif 1268 if (usb_pipeint(pipe)) { 1269 info("Root-Hub submit IRQ: NOT implemented"); 1270 return 0; 1271 } 1272 1273 bmRType_bReq = cmd->requesttype | (cmd->request << 8); 1274 wValue = le16_to_cpu(cmd->value); 1275 wIndex = le16_to_cpu(cmd->index); 1276 wLength = le16_to_cpu(cmd->length); 1277 1278 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", 1279 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); 1280 1281 switch (bmRType_bReq) { 1282 /* Request Destination: 1283 without flags: Device, 1284 RH_INTERFACE: interface, 1285 RH_ENDPOINT: endpoint, 1286 RH_CLASS means HUB here, 1287 RH_OTHER | RH_CLASS almost ever means HUB_PORT here 1288 */ 1289 1290 case RH_GET_STATUS: 1291 *(u16 *)databuf = cpu_to_le16(1); 1292 OK(2); 1293 case RH_GET_STATUS | RH_INTERFACE: 1294 *(u16 *)databuf = cpu_to_le16(0); 1295 OK(2); 1296 case RH_GET_STATUS | RH_ENDPOINT: 1297 *(u16 *)databuf = cpu_to_le16(0); 1298 OK(2); 1299 case RH_GET_STATUS | RH_CLASS: 1300 *(u32 *)databuf = cpu_to_le32( 1301 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); 1302 OK(4); 1303 case RH_GET_STATUS | RH_OTHER | RH_CLASS: 1304 *(u32 *)databuf = cpu_to_le32(RD_RH_PORTSTAT); 1305 OK(4); 1306 1307 case RH_CLEAR_FEATURE | RH_ENDPOINT: 1308 switch (wValue) { 1309 case (RH_ENDPOINT_STALL): 1310 OK(0); 1311 } 1312 break; 1313 1314 case RH_CLEAR_FEATURE | RH_CLASS: 1315 switch (wValue) { 1316 case RH_C_HUB_LOCAL_POWER: 1317 OK(0); 1318 case (RH_C_HUB_OVER_CURRENT): 1319 WR_RH_STAT(RH_HS_OCIC); 1320 OK(0); 1321 } 1322 break; 1323 1324 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: 1325 switch (wValue) { 1326 case (RH_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_CCS); OK(0); 1327 case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_POCI); OK(0); 1328 case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_LSDA); OK(0); 1329 case (RH_C_PORT_CONNECTION): WR_RH_PORTSTAT(RH_PS_CSC); OK(0); 1330 case (RH_C_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_PESC); OK(0); 1331 case (RH_C_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSSC); OK(0); 1332 case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0); 1333 case (RH_C_PORT_RESET): WR_RH_PORTSTAT(RH_PS_PRSC); OK(0); 1334 } 1335 break; 1336 1337 case RH_SET_FEATURE | RH_OTHER | RH_CLASS: 1338 switch (wValue) { 1339 case (RH_PORT_SUSPEND): 1340 WR_RH_PORTSTAT(RH_PS_PSS); OK(0); 1341 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ 1342 if (RD_RH_PORTSTAT & RH_PS_CCS) 1343 WR_RH_PORTSTAT(RH_PS_PRS); 1344 OK(0); 1345 case (RH_PORT_POWER): 1346 WR_RH_PORTSTAT(RH_PS_PPS); 1347 OK(0); 1348 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ 1349 if (RD_RH_PORTSTAT & RH_PS_CCS) 1350 WR_RH_PORTSTAT(RH_PS_PES); 1351 OK(0); 1352 } 1353 break; 1354 1355 case RH_SET_ADDRESS: 1356 ohci->rh.devnum = wValue; 1357 OK(0); 1358 1359 case RH_GET_DESCRIPTOR: 1360 switch ((wValue & 0xff00) >> 8) { 1361 case (0x01): /* device descriptor */ 1362 len = min_t(unsigned int, 1363 leni, 1364 min_t(unsigned int, 1365 sizeof(root_hub_dev_des), 1366 wLength)); 1367 databuf = root_hub_dev_des; OK(len); 1368 case (0x02): /* configuration descriptor */ 1369 len = min_t(unsigned int, 1370 leni, 1371 min_t(unsigned int, 1372 sizeof(root_hub_config_des), 1373 wLength)); 1374 databuf = root_hub_config_des; OK(len); 1375 case (0x03): /* string descriptors */ 1376 if (wValue == 0x0300) { 1377 len = min_t(unsigned int, 1378 leni, 1379 min_t(unsigned int, 1380 sizeof(root_hub_str_index0), 1381 wLength)); 1382 databuf = root_hub_str_index0; 1383 OK(len); 1384 } 1385 if (wValue == 0x0301) { 1386 len = min_t(unsigned int, 1387 leni, 1388 min_t(unsigned int, 1389 sizeof(root_hub_str_index1), 1390 wLength)); 1391 databuf = root_hub_str_index1; 1392 OK(len); 1393 } 1394 default: 1395 stat = USB_ST_STALLED; 1396 } 1397 break; 1398 1399 case RH_GET_DESCRIPTOR | RH_CLASS: 1400 { 1401 __u32 temp = roothub_a(ohci); 1402 1403 databuf[0] = 9; /* min length; */ 1404 databuf[1] = 0x29; 1405 databuf[2] = temp & RH_A_NDP; 1406 #ifdef CONFIG_AT91C_PQFP_UHPBUG 1407 databuf[2] = (databuf[2] == 2) ? 1 : 0; 1408 #endif 1409 databuf[3] = 0; 1410 if (temp & RH_A_PSM) /* per-port power switching? */ 1411 databuf[3] |= 0x1; 1412 if (temp & RH_A_NOCP) /* no overcurrent reporting? */ 1413 databuf[3] |= 0x10; 1414 else if (temp & RH_A_OCPM)/* per-port overcurrent reporting? */ 1415 databuf[3] |= 0x8; 1416 1417 databuf[4] = 0; 1418 databuf[5] = (temp & RH_A_POTPGT) >> 24; 1419 databuf[6] = 0; 1420 temp = roothub_b(ohci); 1421 databuf[7] = temp & RH_B_DR; 1422 if (databuf[2] < 7) { 1423 databuf[8] = 0xff; 1424 } else { 1425 databuf[0] += 2; 1426 databuf[8] = (temp & RH_B_DR) >> 8; 1427 databuf[10] = databuf[9] = 0xff; 1428 } 1429 1430 len = min_t(unsigned int, leni, 1431 min_t(unsigned int, databuf[0], wLength)); 1432 OK(len); 1433 } 1434 1435 case RH_GET_CONFIGURATION: 1436 databuf[0] = 0x01; 1437 OK(1); 1438 1439 case RH_SET_CONFIGURATION: 1440 WR_RH_STAT(0x10000); 1441 OK(0); 1442 1443 default: 1444 dbg("unsupported root hub command"); 1445 stat = USB_ST_STALLED; 1446 } 1447 1448 #ifdef DEBUG 1449 ohci_dump_roothub(ohci, 1); 1450 #else 1451 ohci_mdelay(1); 1452 #endif 1453 1454 len = min_t(int, len, leni); 1455 if (data != databuf) 1456 memcpy(data, databuf, len); 1457 dev->act_len = len; 1458 dev->status = stat; 1459 1460 #ifdef DEBUG 1461 pkt_print(ohci, NULL, dev, pipe, buffer, 1462 transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); 1463 #else 1464 ohci_mdelay(1); 1465 #endif 1466 1467 return stat; 1468 } 1469 1470 /*-------------------------------------------------------------------------*/ 1471 1472 static ohci_dev_t *ohci_get_ohci_dev(ohci_t *ohci, int devnum, int intr) 1473 { 1474 int i; 1475 1476 if (!intr) 1477 return &ohci->ohci_dev; 1478 1479 /* First see if we already have an ohci_dev for this dev. */ 1480 for (i = 0; i < NUM_INT_DEVS; i++) { 1481 if (ohci->int_dev[i].devnum == devnum) 1482 return &ohci->int_dev[i]; 1483 } 1484 1485 /* If not then find a free one. */ 1486 for (i = 0; i < NUM_INT_DEVS; i++) { 1487 if (ohci->int_dev[i].devnum == -1) { 1488 ohci->int_dev[i].devnum = devnum; 1489 return &ohci->int_dev[i]; 1490 } 1491 } 1492 1493 printf("ohci: Error out of ohci_devs for interrupt endpoints\n"); 1494 return NULL; 1495 } 1496 1497 /* common code for handling submit messages - used for all but root hub */ 1498 /* accesses. */ 1499 static urb_priv_t *ohci_alloc_urb(struct usb_device *dev, unsigned long pipe, 1500 void *buffer, int transfer_len, int interval) 1501 { 1502 urb_priv_t *urb; 1503 1504 urb = calloc(1, sizeof(urb_priv_t)); 1505 if (!urb) { 1506 printf("ohci: Error out of memory allocating urb\n"); 1507 return NULL; 1508 } 1509 1510 urb->dev = dev; 1511 urb->pipe = pipe; 1512 urb->transfer_buffer = buffer; 1513 urb->transfer_buffer_length = transfer_len; 1514 urb->interval = interval; 1515 1516 return urb; 1517 } 1518 1519 static int submit_common_msg(ohci_t *ohci, struct usb_device *dev, 1520 unsigned long pipe, void *buffer, int transfer_len, 1521 struct devrequest *setup, int interval) 1522 { 1523 int stat = 0; 1524 int maxsize = usb_maxpacket(dev, pipe); 1525 int timeout; 1526 urb_priv_t *urb; 1527 ohci_dev_t *ohci_dev; 1528 1529 urb = ohci_alloc_urb(dev, pipe, buffer, transfer_len, interval); 1530 if (!urb) 1531 return -ENOMEM; 1532 1533 #ifdef DEBUG 1534 urb->actual_length = 0; 1535 pkt_print(ohci, urb, dev, pipe, buffer, transfer_len, 1536 setup, "SUB", usb_pipein(pipe)); 1537 #else 1538 ohci_mdelay(1); 1539 #endif 1540 if (!maxsize) { 1541 err("submit_common_message: pipesize for pipe %lx is zero", 1542 pipe); 1543 return -1; 1544 } 1545 1546 ohci_dev = ohci_get_ohci_dev(ohci, dev->devnum, usb_pipeint(pipe)); 1547 if (!ohci_dev) 1548 return -ENOMEM; 1549 1550 if (sohci_submit_job(ohci, ohci_dev, urb, setup) < 0) { 1551 err("sohci_submit_job failed"); 1552 return -1; 1553 } 1554 1555 #if 0 1556 mdelay(10); 1557 /* ohci_dump_status(ohci); */ 1558 #endif 1559 1560 timeout = USB_TIMEOUT_MS(pipe); 1561 1562 /* wait for it to complete */ 1563 for (;;) { 1564 /* check whether the controller is done */ 1565 stat = hc_interrupt(ohci); 1566 if (stat < 0) { 1567 stat = USB_ST_CRC_ERR; 1568 break; 1569 } 1570 1571 /* NOTE: since we are not interrupt driven in U-Boot and always 1572 * handle only one URB at a time, we cannot assume the 1573 * transaction finished on the first successful return from 1574 * hc_interrupt().. unless the flag for current URB is set, 1575 * meaning that all TD's to/from device got actually 1576 * transferred and processed. If the current URB is not 1577 * finished we need to re-iterate this loop so as 1578 * hc_interrupt() gets called again as there needs to be some 1579 * more TD's to process still */ 1580 if ((stat >= 0) && (stat != 0xff) && (urb->finished)) { 1581 /* 0xff is returned for an SF-interrupt */ 1582 break; 1583 } 1584 1585 if (--timeout) { 1586 mdelay(1); 1587 if (!urb->finished) 1588 dbg("*"); 1589 1590 } else { 1591 if (!usb_pipeint(pipe)) 1592 err("CTL:TIMEOUT "); 1593 dbg("submit_common_msg: TO status %x\n", stat); 1594 urb->finished = 1; 1595 stat = USB_ST_CRC_ERR; 1596 break; 1597 } 1598 } 1599 1600 dev->status = stat; 1601 dev->act_len = urb->actual_length; 1602 1603 if (usb_pipein(pipe) && dev->status == 0 && dev->act_len) 1604 invalidate_dcache_buffer(buffer, dev->act_len); 1605 1606 #ifdef DEBUG 1607 pkt_print(ohci, urb, dev, pipe, buffer, transfer_len, 1608 setup, "RET(ctlr)", usb_pipein(pipe)); 1609 #else 1610 ohci_mdelay(1); 1611 #endif 1612 urb_free_priv(urb); 1613 return 0; 1614 } 1615 1616 #define MAX_INT_QUEUESIZE 8 1617 1618 struct int_queue { 1619 int queuesize; 1620 int curr_urb; 1621 urb_priv_t *urb[MAX_INT_QUEUESIZE]; 1622 }; 1623 1624 static struct int_queue *_ohci_create_int_queue(ohci_t *ohci, 1625 struct usb_device *udev, unsigned long pipe, int queuesize, 1626 int elementsize, void *buffer, int interval) 1627 { 1628 struct int_queue *queue; 1629 ohci_dev_t *ohci_dev; 1630 int i; 1631 1632 if (queuesize > MAX_INT_QUEUESIZE) 1633 return NULL; 1634 1635 ohci_dev = ohci_get_ohci_dev(ohci, udev->devnum, 1); 1636 if (!ohci_dev) 1637 return NULL; 1638 1639 queue = malloc(sizeof(*queue)); 1640 if (!queue) { 1641 printf("ohci: Error out of memory allocating int queue\n"); 1642 return NULL; 1643 } 1644 1645 for (i = 0; i < queuesize; i++) { 1646 queue->urb[i] = ohci_alloc_urb(udev, pipe, 1647 buffer + i * elementsize, 1648 elementsize, interval); 1649 if (!queue->urb[i]) 1650 break; 1651 1652 if (sohci_submit_job(ohci, ohci_dev, queue->urb[i], NULL)) { 1653 printf("ohci: Error submitting int queue job\n"); 1654 urb_free_priv(queue->urb[i]); 1655 break; 1656 } 1657 } 1658 if (i == 0) { 1659 /* We did not succeed in submitting even 1 urb */ 1660 free(queue); 1661 return NULL; 1662 } 1663 1664 queue->queuesize = i; 1665 queue->curr_urb = 0; 1666 1667 return queue; 1668 } 1669 1670 static void *_ohci_poll_int_queue(ohci_t *ohci, struct usb_device *udev, 1671 struct int_queue *queue) 1672 { 1673 if (queue->curr_urb == queue->queuesize) 1674 return NULL; /* Queue depleted */ 1675 1676 if (hc_interrupt(ohci) < 0) 1677 return NULL; 1678 1679 if (queue->urb[queue->curr_urb]->finished) { 1680 void *ret = queue->urb[queue->curr_urb]->transfer_buffer; 1681 queue->curr_urb++; 1682 return ret; 1683 } 1684 1685 return NULL; 1686 } 1687 1688 static int _ohci_destroy_int_queue(ohci_t *ohci, struct usb_device *dev, 1689 struct int_queue *queue) 1690 { 1691 int i; 1692 1693 for (i = 0; i < queue->queuesize; i++) 1694 urb_free_priv(queue->urb[i]); 1695 1696 free(queue); 1697 1698 return 0; 1699 } 1700 1701 #ifndef CONFIG_DM_USB 1702 /* submit routines called from usb.c */ 1703 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1704 int transfer_len) 1705 { 1706 info("submit_bulk_msg"); 1707 return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, 1708 NULL, 0); 1709 } 1710 1711 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1712 int transfer_len, int interval) 1713 { 1714 info("submit_int_msg"); 1715 return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, NULL, 1716 interval); 1717 } 1718 1719 struct int_queue *create_int_queue(struct usb_device *dev, 1720 unsigned long pipe, int queuesize, int elementsize, 1721 void *buffer, int interval) 1722 { 1723 return _ohci_create_int_queue(&gohci, dev, pipe, queuesize, 1724 elementsize, buffer, interval); 1725 } 1726 1727 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue) 1728 { 1729 return _ohci_poll_int_queue(&gohci, dev, queue); 1730 } 1731 1732 int destroy_int_queue(struct usb_device *dev, struct int_queue *queue) 1733 { 1734 return _ohci_destroy_int_queue(&gohci, dev, queue); 1735 } 1736 #endif 1737 1738 static int _ohci_submit_control_msg(ohci_t *ohci, struct usb_device *dev, 1739 unsigned long pipe, void *buffer, int transfer_len, 1740 struct devrequest *setup) 1741 { 1742 int maxsize = usb_maxpacket(dev, pipe); 1743 1744 info("submit_control_msg"); 1745 #ifdef DEBUG 1746 pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len, 1747 setup, "SUB", usb_pipein(pipe)); 1748 #else 1749 ohci_mdelay(1); 1750 #endif 1751 if (!maxsize) { 1752 err("submit_control_message: pipesize for pipe %lx is zero", 1753 pipe); 1754 return -1; 1755 } 1756 if (((pipe >> 8) & 0x7f) == ohci->rh.devnum) { 1757 ohci->rh.dev = dev; 1758 /* root hub - redirect */ 1759 return ohci_submit_rh_msg(ohci, dev, pipe, buffer, 1760 transfer_len, setup); 1761 } 1762 1763 return submit_common_msg(ohci, dev, pipe, buffer, transfer_len, 1764 setup, 0); 1765 } 1766 1767 /*-------------------------------------------------------------------------* 1768 * HC functions 1769 *-------------------------------------------------------------------------*/ 1770 1771 /* reset the HC and BUS */ 1772 1773 static int hc_reset(ohci_t *ohci) 1774 { 1775 #ifdef CONFIG_PCI_EHCI_DEVNO 1776 pci_dev_t pdev; 1777 #endif 1778 int timeout = 30; 1779 int smm_timeout = 50; /* 0,5 sec */ 1780 1781 dbg("%s\n", __FUNCTION__); 1782 1783 #ifdef CONFIG_PCI_EHCI_DEVNO 1784 /* 1785 * Some multi-function controllers (e.g. ISP1562) allow root hub 1786 * resetting via EHCI registers only. 1787 */ 1788 pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO); 1789 if (pdev != -1) { 1790 u32 base; 1791 int timeout = 1000; 1792 1793 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); 1794 base += EHCI_USBCMD_OFF; 1795 ohci_writel(ohci_readl(base) | EHCI_USBCMD_HCRESET, base); 1796 1797 while (ohci_readl(base) & EHCI_USBCMD_HCRESET) { 1798 if (timeout-- <= 0) { 1799 printf("USB RootHub reset timed out!"); 1800 break; 1801 } 1802 udelay(1); 1803 } 1804 } else 1805 printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO); 1806 #endif 1807 if (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { 1808 /* SMM owns the HC, request ownership */ 1809 ohci_writel(OHCI_OCR, &ohci->regs->cmdstatus); 1810 info("USB HC TakeOver from SMM"); 1811 while (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { 1812 mdelay(10); 1813 if (--smm_timeout == 0) { 1814 err("USB HC TakeOver failed!"); 1815 return -1; 1816 } 1817 } 1818 } 1819 1820 /* Disable HC interrupts */ 1821 ohci_writel(OHCI_INTR_MIE, &ohci->regs->intrdisable); 1822 1823 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n", 1824 ohci->slot_name, 1825 ohci_readl(&ohci->regs->control)); 1826 1827 /* Reset USB (needed by some controllers) */ 1828 ohci->hc_control = 0; 1829 ohci_writel(ohci->hc_control, &ohci->regs->control); 1830 1831 /* HC Reset requires max 10 us delay */ 1832 ohci_writel(OHCI_HCR, &ohci->regs->cmdstatus); 1833 while ((ohci_readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { 1834 if (--timeout == 0) { 1835 err("USB HC reset timed out!"); 1836 return -1; 1837 } 1838 udelay(1); 1839 } 1840 return 0; 1841 } 1842 1843 /*-------------------------------------------------------------------------*/ 1844 1845 /* Start an OHCI controller, set the BUS operational 1846 * enable interrupts 1847 * connect the virtual root hub */ 1848 1849 static int hc_start(ohci_t *ohci) 1850 { 1851 __u32 mask; 1852 unsigned int fminterval; 1853 int i; 1854 1855 ohci->disabled = 1; 1856 for (i = 0; i < NUM_INT_DEVS; i++) 1857 ohci->int_dev[i].devnum = -1; 1858 1859 /* Tell the controller where the control and bulk lists are 1860 * The lists are empty now. */ 1861 1862 ohci_writel(0, &ohci->regs->ed_controlhead); 1863 ohci_writel(0, &ohci->regs->ed_bulkhead); 1864 1865 ohci_writel((__u32)ohci->hcca, 1866 &ohci->regs->hcca); /* reset clears this */ 1867 1868 fminterval = 0x2edf; 1869 ohci_writel((fminterval * 9) / 10, &ohci->regs->periodicstart); 1870 fminterval |= ((((fminterval - 210) * 6) / 7) << 16); 1871 ohci_writel(fminterval, &ohci->regs->fminterval); 1872 ohci_writel(0x628, &ohci->regs->lsthresh); 1873 1874 /* start controller operations */ 1875 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; 1876 ohci->disabled = 0; 1877 ohci_writel(ohci->hc_control, &ohci->regs->control); 1878 1879 /* disable all interrupts */ 1880 mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | 1881 OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | 1882 OHCI_INTR_OC | OHCI_INTR_MIE); 1883 ohci_writel(mask, &ohci->regs->intrdisable); 1884 /* clear all interrupts */ 1885 mask &= ~OHCI_INTR_MIE; 1886 ohci_writel(mask, &ohci->regs->intrstatus); 1887 /* Choose the interrupts we care about now - but w/o MIE */ 1888 mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; 1889 ohci_writel(mask, &ohci->regs->intrenable); 1890 1891 #ifdef OHCI_USE_NPS 1892 /* required for AMD-756 and some Mac platforms */ 1893 ohci_writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM, 1894 &ohci->regs->roothub.a); 1895 ohci_writel(RH_HS_LPSC, &ohci->regs->roothub.status); 1896 #endif /* OHCI_USE_NPS */ 1897 1898 /* connect the virtual root hub */ 1899 ohci->rh.devnum = 0; 1900 1901 return 0; 1902 } 1903 1904 /*-------------------------------------------------------------------------*/ 1905 1906 /* an interrupt happens */ 1907 1908 static int hc_interrupt(ohci_t *ohci) 1909 { 1910 struct ohci_regs *regs = ohci->regs; 1911 int ints; 1912 int stat = -1; 1913 1914 invalidate_dcache_hcca(ohci->hcca); 1915 1916 if ((ohci->hcca->done_head != 0) && 1917 !(m32_swap(ohci->hcca->done_head) & 0x01)) { 1918 ints = OHCI_INTR_WDH; 1919 } else { 1920 ints = ohci_readl(®s->intrstatus); 1921 if (ints == ~(u32)0) { 1922 ohci->disabled++; 1923 err("%s device removed!", ohci->slot_name); 1924 return -1; 1925 } else { 1926 ints &= ohci_readl(®s->intrenable); 1927 if (ints == 0) { 1928 dbg("hc_interrupt: returning..\n"); 1929 return 0xff; 1930 } 1931 } 1932 } 1933 1934 /* dbg("Interrupt: %x frame: %x", ints, 1935 le16_to_cpu(ohci->hcca->frame_no)); */ 1936 1937 if (ints & OHCI_INTR_RHSC) 1938 stat = 0xff; 1939 1940 if (ints & OHCI_INTR_UE) { 1941 ohci->disabled++; 1942 err("OHCI Unrecoverable Error, controller usb-%s disabled", 1943 ohci->slot_name); 1944 /* e.g. due to PCI Master/Target Abort */ 1945 1946 #ifdef DEBUG 1947 ohci_dump(ohci, 1); 1948 #else 1949 ohci_mdelay(1); 1950 #endif 1951 /* FIXME: be optimistic, hope that bug won't repeat often. */ 1952 /* Make some non-interrupt context restart the controller. */ 1953 /* Count and limit the retries though; either hardware or */ 1954 /* software errors can go forever... */ 1955 hc_reset(ohci); 1956 return -1; 1957 } 1958 1959 if (ints & OHCI_INTR_WDH) { 1960 ohci_mdelay(1); 1961 ohci_writel(OHCI_INTR_WDH, ®s->intrdisable); 1962 (void)ohci_readl(®s->intrdisable); /* flush */ 1963 stat = dl_done_list(ohci); 1964 ohci_writel(OHCI_INTR_WDH, ®s->intrenable); 1965 (void)ohci_readl(®s->intrdisable); /* flush */ 1966 } 1967 1968 if (ints & OHCI_INTR_SO) { 1969 dbg("USB Schedule overrun\n"); 1970 ohci_writel(OHCI_INTR_SO, ®s->intrenable); 1971 stat = -1; 1972 } 1973 1974 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ 1975 if (ints & OHCI_INTR_SF) { 1976 unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1; 1977 mdelay(1); 1978 ohci_writel(OHCI_INTR_SF, ®s->intrdisable); 1979 if (ohci->ed_rm_list[frame] != NULL) 1980 ohci_writel(OHCI_INTR_SF, ®s->intrenable); 1981 stat = 0xff; 1982 } 1983 1984 ohci_writel(ints, ®s->intrstatus); 1985 return stat; 1986 } 1987 1988 /*-------------------------------------------------------------------------*/ 1989 1990 #ifndef CONFIG_DM_USB 1991 1992 /*-------------------------------------------------------------------------*/ 1993 1994 /* De-allocate all resources.. */ 1995 1996 static void hc_release_ohci(ohci_t *ohci) 1997 { 1998 dbg("USB HC release ohci usb-%s", ohci->slot_name); 1999 2000 if (!ohci->disabled) 2001 hc_reset(ohci); 2002 } 2003 2004 /*-------------------------------------------------------------------------*/ 2005 2006 /* 2007 * low level initalisation routine, called from usb.c 2008 */ 2009 static char ohci_inited = 0; 2010 2011 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) 2012 { 2013 #ifdef CONFIG_PCI_OHCI 2014 pci_dev_t pdev; 2015 #endif 2016 2017 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT 2018 /* cpu dependant init */ 2019 if (usb_cpu_init()) 2020 return -1; 2021 #endif 2022 2023 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT 2024 /* board dependant init */ 2025 if (board_usb_init(index, USB_INIT_HOST)) 2026 return -1; 2027 #endif 2028 memset(&gohci, 0, sizeof(ohci_t)); 2029 2030 /* align the storage */ 2031 if ((__u32)&ghcca[0] & 0xff) { 2032 err("HCCA not aligned!!"); 2033 return -1; 2034 } 2035 gohci.hcca = &ghcca[0]; 2036 info("aligned ghcca %p", gohci.hcca); 2037 memset(gohci.hcca, 0, sizeof(struct ohci_hcca)); 2038 2039 gohci.disabled = 1; 2040 gohci.sleeping = 0; 2041 gohci.irq = -1; 2042 #ifdef CONFIG_PCI_OHCI 2043 pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO); 2044 2045 if (pdev != -1) { 2046 u16 vid, did; 2047 u32 base; 2048 pci_read_config_word(pdev, PCI_VENDOR_ID, &vid); 2049 pci_read_config_word(pdev, PCI_DEVICE_ID, &did); 2050 printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n", 2051 vid, did, (pdev >> 16) & 0xff, 2052 (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); 2053 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); 2054 printf("OHCI regs address 0x%08x\n", base); 2055 gohci.regs = (struct ohci_regs *)base; 2056 } else 2057 return -1; 2058 #else 2059 gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE; 2060 #endif 2061 2062 gohci.flags = 0; 2063 gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME; 2064 2065 if (hc_reset (&gohci) < 0) { 2066 hc_release_ohci (&gohci); 2067 err ("can't reset usb-%s", gohci.slot_name); 2068 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT 2069 /* board dependant cleanup */ 2070 board_usb_cleanup(index, USB_INIT_HOST); 2071 #endif 2072 2073 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT 2074 /* cpu dependant cleanup */ 2075 usb_cpu_init_fail(); 2076 #endif 2077 return -1; 2078 } 2079 2080 if (hc_start(&gohci) < 0) { 2081 err("can't start usb-%s", gohci.slot_name); 2082 hc_release_ohci(&gohci); 2083 /* Initialization failed */ 2084 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT 2085 /* board dependant cleanup */ 2086 usb_board_stop(); 2087 #endif 2088 2089 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT 2090 /* cpu dependant cleanup */ 2091 usb_cpu_stop(); 2092 #endif 2093 return -1; 2094 } 2095 2096 #ifdef DEBUG 2097 ohci_dump(&gohci, 1); 2098 #else 2099 ohci_mdelay(1); 2100 #endif 2101 ohci_inited = 1; 2102 return 0; 2103 } 2104 2105 int usb_lowlevel_stop(int index) 2106 { 2107 /* this gets called really early - before the controller has */ 2108 /* even been initialized! */ 2109 if (!ohci_inited) 2110 return 0; 2111 /* TODO release any interrupts, etc. */ 2112 /* call hc_release_ohci() here ? */ 2113 hc_reset(&gohci); 2114 2115 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT 2116 /* board dependant cleanup */ 2117 if (usb_board_stop()) 2118 return -1; 2119 #endif 2120 2121 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT 2122 /* cpu dependant cleanup */ 2123 if (usb_cpu_stop()) 2124 return -1; 2125 #endif 2126 /* This driver is no longer initialised. It needs a new low-level 2127 * init (board/cpu) before it can be used again. */ 2128 ohci_inited = 0; 2129 return 0; 2130 } 2131 2132 int submit_control_msg(struct usb_device *dev, unsigned long pipe, 2133 void *buffer, int transfer_len, struct devrequest *setup) 2134 { 2135 return _ohci_submit_control_msg(&gohci, dev, pipe, buffer, 2136 transfer_len, setup); 2137 } 2138 #endif 2139 2140 #ifdef CONFIG_DM_USB 2141 static int ohci_submit_control_msg(struct udevice *dev, struct usb_device *udev, 2142 unsigned long pipe, void *buffer, int length, 2143 struct devrequest *setup) 2144 { 2145 ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); 2146 2147 return _ohci_submit_control_msg(ohci, udev, pipe, buffer, 2148 length, setup); 2149 } 2150 2151 static int ohci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev, 2152 unsigned long pipe, void *buffer, int length) 2153 { 2154 ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); 2155 2156 return submit_common_msg(ohci, udev, pipe, buffer, length, NULL, 0); 2157 } 2158 2159 static int ohci_submit_int_msg(struct udevice *dev, struct usb_device *udev, 2160 unsigned long pipe, void *buffer, int length, 2161 int interval) 2162 { 2163 ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); 2164 2165 return submit_common_msg(ohci, udev, pipe, buffer, length, 2166 NULL, interval); 2167 } 2168 2169 static struct int_queue *ohci_create_int_queue(struct udevice *dev, 2170 struct usb_device *udev, unsigned long pipe, int queuesize, 2171 int elementsize, void *buffer, int interval) 2172 { 2173 ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); 2174 2175 return _ohci_create_int_queue(ohci, udev, pipe, queuesize, elementsize, 2176 buffer, interval); 2177 } 2178 2179 static void *ohci_poll_int_queue(struct udevice *dev, struct usb_device *udev, 2180 struct int_queue *queue) 2181 { 2182 ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); 2183 2184 return _ohci_poll_int_queue(ohci, udev, queue); 2185 } 2186 2187 static int ohci_destroy_int_queue(struct udevice *dev, struct usb_device *udev, 2188 struct int_queue *queue) 2189 { 2190 ohci_t *ohci = dev_get_priv(usb_get_bus(dev)); 2191 2192 return _ohci_destroy_int_queue(ohci, udev, queue); 2193 } 2194 2195 int ohci_register(struct udevice *dev, struct ohci_regs *regs) 2196 { 2197 struct usb_bus_priv *priv = dev_get_uclass_priv(dev); 2198 ohci_t *ohci = dev_get_priv(dev); 2199 u32 reg; 2200 2201 priv->desc_before_addr = true; 2202 2203 ohci->regs = regs; 2204 ohci->hcca = memalign(256, sizeof(struct ohci_hcca)); 2205 if (!ohci->hcca) 2206 return -ENOMEM; 2207 memset(ohci->hcca, 0, sizeof(struct ohci_hcca)); 2208 flush_dcache_hcca(ohci->hcca); 2209 2210 if (hc_reset(ohci) < 0) 2211 return -EIO; 2212 2213 if (hc_start(ohci) < 0) 2214 return -EIO; 2215 2216 reg = ohci_readl(®s->revision); 2217 printf("USB OHCI %x.%x\n", (reg >> 4) & 0xf, reg & 0xf); 2218 2219 return 0; 2220 } 2221 2222 int ohci_deregister(struct udevice *dev) 2223 { 2224 ohci_t *ohci = dev_get_priv(dev); 2225 2226 if (hc_reset(ohci) < 0) 2227 return -EIO; 2228 2229 free(ohci->hcca); 2230 2231 return 0; 2232 } 2233 2234 struct dm_usb_ops ohci_usb_ops = { 2235 .control = ohci_submit_control_msg, 2236 .bulk = ohci_submit_bulk_msg, 2237 .interrupt = ohci_submit_int_msg, 2238 .create_int_queue = ohci_create_int_queue, 2239 .poll_int_queue = ohci_poll_int_queue, 2240 .destroy_int_queue = ohci_destroy_int_queue, 2241 }; 2242 2243 #endif 2244