1 /* 2 * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus. 3 * 4 * Interrupt support is added. Now, it has been tested 5 * on ULI1575 chip and works well with USB keyboard. 6 * 7 * (C) Copyright 2007 8 * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com> 9 * 10 * (C) Copyright 2003 11 * Gary Jennejohn, DENX Software Engineering <garyj@denx.de> 12 * 13 * Note: Much of this code has been derived from Linux 2.4 14 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 15 * (C) Copyright 2000-2002 David Brownell 16 * 17 * Modified for the MP2USB by (C) Copyright 2005 Eric Benard 18 * ebenard@eukrea.com - based on s3c24x0's driver 19 * 20 * See file CREDITS for list of people who contributed to this 21 * project. 22 * 23 * This program is free software; you can redistribute it and/or 24 * modify it under the terms of the GNU General Public License as 25 * published by the Free Software Foundation; either version 2 of 26 * the License, or (at your option) any later version. 27 * 28 * This program is distributed in the hope that it will be useful, 29 * but WITHOUT ANY WARRANTY; without even the implied warranty of 30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 31 * GNU General Public License for more details. 32 * 33 * You should have received a copy of the GNU General Public License 34 * along with this program; if not, write to the Free Software 35 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 36 * MA 02111-1307 USA 37 * 38 */ 39 /* 40 * IMPORTANT NOTES 41 * 1 - Read doc/README.generic_usb_ohci 42 * 2 - this driver is intended for use with USB Mass Storage Devices 43 * (BBB) and USB keyboard. There is NO support for Isochronous pipes! 44 * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG 45 * to activate workaround for bug #41 or this driver will NOT work! 46 */ 47 48 #include <common.h> 49 #include <asm/byteorder.h> 50 51 #if defined(CONFIG_PCI_OHCI) 52 # include <pci.h> 53 #if !defined(CONFIG_PCI_OHCI_DEVNO) 54 #define CONFIG_PCI_OHCI_DEVNO 0 55 #endif 56 #endif 57 58 #include <malloc.h> 59 #include <usb.h> 60 61 #include "ohci.h" 62 63 #ifdef CONFIG_AT91RM9200 64 #include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */ 65 #endif 66 67 #if defined(CONFIG_ARM920T) || \ 68 defined(CONFIG_S3C24X0) || \ 69 defined(CONFIG_S3C6400) || \ 70 defined(CONFIG_440EP) || \ 71 defined(CONFIG_PCI_OHCI) || \ 72 defined(CONFIG_MPC5200) || \ 73 defined(CONFIG_SYS_OHCI_USE_NPS) 74 # define OHCI_USE_NPS /* force NoPowerSwitching mode */ 75 #endif 76 77 #undef OHCI_VERBOSE_DEBUG /* not always helpful */ 78 #undef DEBUG 79 #undef SHOW_INFO 80 #undef OHCI_FILL_TRACE 81 82 /* For initializing controller (mask in an HCFS mode too) */ 83 #define OHCI_CONTROL_INIT \ 84 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE 85 86 #define min_t(type, x, y) \ 87 ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) 88 89 #ifdef CONFIG_PCI_OHCI 90 static struct pci_device_id ohci_pci_ids[] = { 91 {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ 92 {0x1033, 0x0035}, /* NEC PCI OHCI module ids */ 93 {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */ 94 /* Please add supported PCI OHCI controller ids here */ 95 {0, 0} 96 }; 97 #endif 98 99 #ifdef CONFIG_PCI_EHCI_DEVNO 100 static struct pci_device_id ehci_pci_ids[] = { 101 {0x1131, 0x1562}, /* Philips 1562 PCI EHCI module ids */ 102 /* Please add supported PCI EHCI controller ids here */ 103 {0, 0} 104 }; 105 #endif 106 107 #ifdef DEBUG 108 #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) 109 #else 110 #define dbg(format, arg...) do {} while (0) 111 #endif /* DEBUG */ 112 #define err(format, arg...) printf("ERROR: " format "\n", ## arg) 113 #ifdef SHOW_INFO 114 #define info(format, arg...) printf("INFO: " format "\n", ## arg) 115 #else 116 #define info(format, arg...) do {} while (0) 117 #endif 118 119 #ifdef CONFIG_SYS_OHCI_BE_CONTROLLER 120 # define m16_swap(x) cpu_to_be16(x) 121 # define m32_swap(x) cpu_to_be32(x) 122 #else 123 # define m16_swap(x) cpu_to_le16(x) 124 # define m32_swap(x) cpu_to_le32(x) 125 #endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */ 126 127 /* global ohci_t */ 128 static ohci_t gohci; 129 /* this must be aligned to a 256 byte boundary */ 130 struct ohci_hcca ghcca[1]; 131 /* a pointer to the aligned storage */ 132 struct ohci_hcca *phcca; 133 /* this allocates EDs for all possible endpoints */ 134 struct ohci_device ohci_dev; 135 /* device which was disconnected */ 136 struct usb_device *devgone; 137 138 static inline u32 roothub_a(struct ohci *hc) 139 { return ohci_readl(&hc->regs->roothub.a); } 140 static inline u32 roothub_b(struct ohci *hc) 141 { return ohci_readl(&hc->regs->roothub.b); } 142 static inline u32 roothub_status(struct ohci *hc) 143 { return ohci_readl(&hc->regs->roothub.status); } 144 static inline u32 roothub_portstatus(struct ohci *hc, int i) 145 { return ohci_readl(&hc->regs->roothub.portstatus[i]); } 146 147 /* forward declaration */ 148 static int hc_interrupt(void); 149 static void td_submit_job(struct usb_device *dev, unsigned long pipe, 150 void *buffer, int transfer_len, 151 struct devrequest *setup, urb_priv_t *urb, 152 int interval); 153 154 /*-------------------------------------------------------------------------* 155 * URB support functions 156 *-------------------------------------------------------------------------*/ 157 158 /* free HCD-private data associated with this URB */ 159 160 static void urb_free_priv(urb_priv_t *urb) 161 { 162 int i; 163 int last; 164 struct td *td; 165 166 last = urb->length - 1; 167 if (last >= 0) { 168 for (i = 0; i <= last; i++) { 169 td = urb->td[i]; 170 if (td) { 171 td->usb_dev = NULL; 172 urb->td[i] = NULL; 173 } 174 } 175 } 176 free(urb); 177 } 178 179 /*-------------------------------------------------------------------------*/ 180 181 #ifdef DEBUG 182 static int sohci_get_current_frame_number(struct usb_device *dev); 183 184 /* debug| print the main components of an URB 185 * small: 0) header + data packets 1) just header */ 186 187 static void pkt_print(urb_priv_t *purb, struct usb_device *dev, 188 unsigned long pipe, void *buffer, int transfer_len, 189 struct devrequest *setup, char *str, int small) 190 { 191 dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx", 192 str, 193 sohci_get_current_frame_number(dev), 194 usb_pipedevice(pipe), 195 usb_pipeendpoint(pipe), 196 usb_pipeout(pipe)? 'O': 'I', 197 usb_pipetype(pipe) < 2 ? \ 198 (usb_pipeint(pipe)? "INTR": "ISOC"): \ 199 (usb_pipecontrol(pipe)? "CTRL": "BULK"), 200 (purb ? purb->actual_length : 0), 201 transfer_len, dev->status); 202 #ifdef OHCI_VERBOSE_DEBUG 203 if (!small) { 204 int i, len; 205 206 if (usb_pipecontrol(pipe)) { 207 printf(__FILE__ ": cmd(8):"); 208 for (i = 0; i < 8 ; i++) 209 printf(" %02x", ((__u8 *) setup) [i]); 210 printf("\n"); 211 } 212 if (transfer_len > 0 && buffer) { 213 printf(__FILE__ ": data(%d/%d):", 214 (purb ? purb->actual_length : 0), 215 transfer_len); 216 len = usb_pipeout(pipe)? transfer_len: 217 (purb ? purb->actual_length : 0); 218 for (i = 0; i < 16 && i < len; i++) 219 printf(" %02x", ((__u8 *) buffer) [i]); 220 printf("%s\n", i < len? "...": ""); 221 } 222 } 223 #endif 224 } 225 226 /* just for debugging; prints non-empty branches of the int ed tree 227 * inclusive iso eds */ 228 void ep_print_int_eds(ohci_t *ohci, char *str) 229 { 230 int i, j; 231 __u32 *ed_p; 232 for (i = 0; i < 32; i++) { 233 j = 5; 234 ed_p = &(ohci->hcca->int_table [i]); 235 if (*ed_p == 0) 236 continue; 237 printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i); 238 while (*ed_p != 0 && j--) { 239 ed_t *ed = (ed_t *)m32_swap(ed_p); 240 printf(" ed: %4x;", ed->hwINFO); 241 ed_p = &ed->hwNextED; 242 } 243 printf("\n"); 244 } 245 } 246 247 static void ohci_dump_intr_mask(char *label, __u32 mask) 248 { 249 dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s", 250 label, 251 mask, 252 (mask & OHCI_INTR_MIE) ? " MIE" : "", 253 (mask & OHCI_INTR_OC) ? " OC" : "", 254 (mask & OHCI_INTR_RHSC) ? " RHSC" : "", 255 (mask & OHCI_INTR_FNO) ? " FNO" : "", 256 (mask & OHCI_INTR_UE) ? " UE" : "", 257 (mask & OHCI_INTR_RD) ? " RD" : "", 258 (mask & OHCI_INTR_SF) ? " SF" : "", 259 (mask & OHCI_INTR_WDH) ? " WDH" : "", 260 (mask & OHCI_INTR_SO) ? " SO" : "" 261 ); 262 } 263 264 static void maybe_print_eds(char *label, __u32 value) 265 { 266 ed_t *edp = (ed_t *)value; 267 268 if (value) { 269 dbg("%s %08x", label, value); 270 dbg("%08x", edp->hwINFO); 271 dbg("%08x", edp->hwTailP); 272 dbg("%08x", edp->hwHeadP); 273 dbg("%08x", edp->hwNextED); 274 } 275 } 276 277 static char *hcfs2string(int state) 278 { 279 switch (state) { 280 case OHCI_USB_RESET: return "reset"; 281 case OHCI_USB_RESUME: return "resume"; 282 case OHCI_USB_OPER: return "operational"; 283 case OHCI_USB_SUSPEND: return "suspend"; 284 } 285 return "?"; 286 } 287 288 /* dump control and status registers */ 289 static void ohci_dump_status(ohci_t *controller) 290 { 291 struct ohci_regs *regs = controller->regs; 292 __u32 temp; 293 294 temp = ohci_readl(®s->revision) & 0xff; 295 if (temp != 0x10) 296 dbg("spec %d.%d", (temp >> 4), (temp & 0x0f)); 297 298 temp = ohci_readl(®s->control); 299 dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, 300 (temp & OHCI_CTRL_RWE) ? " RWE" : "", 301 (temp & OHCI_CTRL_RWC) ? " RWC" : "", 302 (temp & OHCI_CTRL_IR) ? " IR" : "", 303 hcfs2string(temp & OHCI_CTRL_HCFS), 304 (temp & OHCI_CTRL_BLE) ? " BLE" : "", 305 (temp & OHCI_CTRL_CLE) ? " CLE" : "", 306 (temp & OHCI_CTRL_IE) ? " IE" : "", 307 (temp & OHCI_CTRL_PLE) ? " PLE" : "", 308 temp & OHCI_CTRL_CBSR 309 ); 310 311 temp = ohci_readl(®s->cmdstatus); 312 dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, 313 (temp & OHCI_SOC) >> 16, 314 (temp & OHCI_OCR) ? " OCR" : "", 315 (temp & OHCI_BLF) ? " BLF" : "", 316 (temp & OHCI_CLF) ? " CLF" : "", 317 (temp & OHCI_HCR) ? " HCR" : "" 318 ); 319 320 ohci_dump_intr_mask("intrstatus", ohci_readl(®s->intrstatus)); 321 ohci_dump_intr_mask("intrenable", ohci_readl(®s->intrenable)); 322 323 maybe_print_eds("ed_periodcurrent", 324 ohci_readl(®s->ed_periodcurrent)); 325 326 maybe_print_eds("ed_controlhead", ohci_readl(®s->ed_controlhead)); 327 maybe_print_eds("ed_controlcurrent", 328 ohci_readl(®s->ed_controlcurrent)); 329 330 maybe_print_eds("ed_bulkhead", ohci_readl(®s->ed_bulkhead)); 331 maybe_print_eds("ed_bulkcurrent", ohci_readl(®s->ed_bulkcurrent)); 332 333 maybe_print_eds("donehead", ohci_readl(®s->donehead)); 334 } 335 336 static void ohci_dump_roothub(ohci_t *controller, int verbose) 337 { 338 __u32 temp, ndp, i; 339 340 temp = roothub_a(controller); 341 ndp = (temp & RH_A_NDP); 342 #ifdef CONFIG_AT91C_PQFP_UHPBUG 343 ndp = (ndp == 2) ? 1:0; 344 #endif 345 if (verbose) { 346 dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, 347 ((temp & RH_A_POTPGT) >> 24) & 0xff, 348 (temp & RH_A_NOCP) ? " NOCP" : "", 349 (temp & RH_A_OCPM) ? " OCPM" : "", 350 (temp & RH_A_DT) ? " DT" : "", 351 (temp & RH_A_NPS) ? " NPS" : "", 352 (temp & RH_A_PSM) ? " PSM" : "", 353 ndp 354 ); 355 temp = roothub_b(controller); 356 dbg("roothub.b: %08x PPCM=%04x DR=%04x", 357 temp, 358 (temp & RH_B_PPCM) >> 16, 359 (temp & RH_B_DR) 360 ); 361 temp = roothub_status(controller); 362 dbg("roothub.status: %08x%s%s%s%s%s%s", 363 temp, 364 (temp & RH_HS_CRWE) ? " CRWE" : "", 365 (temp & RH_HS_OCIC) ? " OCIC" : "", 366 (temp & RH_HS_LPSC) ? " LPSC" : "", 367 (temp & RH_HS_DRWE) ? " DRWE" : "", 368 (temp & RH_HS_OCI) ? " OCI" : "", 369 (temp & RH_HS_LPS) ? " LPS" : "" 370 ); 371 } 372 373 for (i = 0; i < ndp; i++) { 374 temp = roothub_portstatus(controller, i); 375 dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", 376 i, 377 temp, 378 (temp & RH_PS_PRSC) ? " PRSC" : "", 379 (temp & RH_PS_OCIC) ? " OCIC" : "", 380 (temp & RH_PS_PSSC) ? " PSSC" : "", 381 (temp & RH_PS_PESC) ? " PESC" : "", 382 (temp & RH_PS_CSC) ? " CSC" : "", 383 384 (temp & RH_PS_LSDA) ? " LSDA" : "", 385 (temp & RH_PS_PPS) ? " PPS" : "", 386 (temp & RH_PS_PRS) ? " PRS" : "", 387 (temp & RH_PS_POCI) ? " POCI" : "", 388 (temp & RH_PS_PSS) ? " PSS" : "", 389 390 (temp & RH_PS_PES) ? " PES" : "", 391 (temp & RH_PS_CCS) ? " CCS" : "" 392 ); 393 } 394 } 395 396 static void ohci_dump(ohci_t *controller, int verbose) 397 { 398 dbg("OHCI controller usb-%s state", controller->slot_name); 399 400 /* dumps some of the state we know about */ 401 ohci_dump_status(controller); 402 if (verbose) 403 ep_print_int_eds(controller, "hcca"); 404 dbg("hcca frame #%04x", controller->hcca->frame_no); 405 ohci_dump_roothub(controller, 1); 406 } 407 #endif /* DEBUG */ 408 409 /*-------------------------------------------------------------------------* 410 * Interface functions (URB) 411 *-------------------------------------------------------------------------*/ 412 413 /* get a transfer request */ 414 415 int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup) 416 { 417 ohci_t *ohci; 418 ed_t *ed; 419 urb_priv_t *purb_priv = urb; 420 int i, size = 0; 421 struct usb_device *dev = urb->dev; 422 unsigned long pipe = urb->pipe; 423 void *buffer = urb->transfer_buffer; 424 int transfer_len = urb->transfer_buffer_length; 425 int interval = urb->interval; 426 427 ohci = &gohci; 428 429 /* when controller's hung, permit only roothub cleanup attempts 430 * such as powering down ports */ 431 if (ohci->disabled) { 432 err("sohci_submit_job: EPIPE"); 433 return -1; 434 } 435 436 /* we're about to begin a new transaction here so mark the 437 * URB unfinished */ 438 urb->finished = 0; 439 440 /* every endpoint has a ed, locate and fill it */ 441 ed = ep_add_ed(dev, pipe, interval, 1); 442 if (!ed) { 443 err("sohci_submit_job: ENOMEM"); 444 return -1; 445 } 446 447 /* for the private part of the URB we need the number of TDs (size) */ 448 switch (usb_pipetype(pipe)) { 449 case PIPE_BULK: /* one TD for every 4096 Byte */ 450 size = (transfer_len - 1) / 4096 + 1; 451 break; 452 case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ 453 size = (transfer_len == 0)? 2: 454 (transfer_len - 1) / 4096 + 3; 455 break; 456 case PIPE_INTERRUPT: /* 1 TD */ 457 size = 1; 458 break; 459 } 460 461 ed->purb = urb; 462 463 if (size >= (N_URB_TD - 1)) { 464 err("need %d TDs, only have %d", size, N_URB_TD); 465 return -1; 466 } 467 purb_priv->pipe = pipe; 468 469 /* fill the private part of the URB */ 470 purb_priv->length = size; 471 purb_priv->ed = ed; 472 purb_priv->actual_length = 0; 473 474 /* allocate the TDs */ 475 /* note that td[0] was allocated in ep_add_ed */ 476 for (i = 0; i < size; i++) { 477 purb_priv->td[i] = td_alloc(dev); 478 if (!purb_priv->td[i]) { 479 purb_priv->length = i; 480 urb_free_priv(purb_priv); 481 err("sohci_submit_job: ENOMEM"); 482 return -1; 483 } 484 } 485 486 if (ed->state == ED_NEW || (ed->state & ED_DEL)) { 487 urb_free_priv(purb_priv); 488 err("sohci_submit_job: EINVAL"); 489 return -1; 490 } 491 492 /* link the ed into a chain if is not already */ 493 if (ed->state != ED_OPER) 494 ep_link(ohci, ed); 495 496 /* fill the TDs and link it to the ed */ 497 td_submit_job(dev, pipe, buffer, transfer_len, 498 setup, purb_priv, interval); 499 500 return 0; 501 } 502 503 static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb) 504 { 505 struct ohci_regs *regs = hc->regs; 506 507 switch (usb_pipetype(urb->pipe)) { 508 case PIPE_INTERRUPT: 509 /* implicitly requeued */ 510 if (urb->dev->irq_handle && 511 (urb->dev->irq_act_len = urb->actual_length)) { 512 ohci_writel(OHCI_INTR_WDH, ®s->intrenable); 513 ohci_readl(®s->intrenable); /* PCI posting flush */ 514 urb->dev->irq_handle(urb->dev); 515 ohci_writel(OHCI_INTR_WDH, ®s->intrdisable); 516 ohci_readl(®s->intrdisable); /* PCI posting flush */ 517 } 518 urb->actual_length = 0; 519 td_submit_job( 520 urb->dev, 521 urb->pipe, 522 urb->transfer_buffer, 523 urb->transfer_buffer_length, 524 NULL, 525 urb, 526 urb->interval); 527 break; 528 case PIPE_CONTROL: 529 case PIPE_BULK: 530 break; 531 default: 532 return 0; 533 } 534 return 1; 535 } 536 537 /*-------------------------------------------------------------------------*/ 538 539 #ifdef DEBUG 540 /* tell us the current USB frame number */ 541 542 static int sohci_get_current_frame_number(struct usb_device *usb_dev) 543 { 544 ohci_t *ohci = &gohci; 545 546 return m16_swap(ohci->hcca->frame_no); 547 } 548 #endif 549 550 /*-------------------------------------------------------------------------* 551 * ED handling functions 552 *-------------------------------------------------------------------------*/ 553 554 /* search for the right branch to insert an interrupt ed into the int tree 555 * do some load ballancing; 556 * returns the branch and 557 * sets the interval to interval = 2^integer (ld (interval)) */ 558 559 static int ep_int_ballance(ohci_t *ohci, int interval, int load) 560 { 561 int i, branch = 0; 562 563 /* search for the least loaded interrupt endpoint 564 * branch of all 32 branches 565 */ 566 for (i = 0; i < 32; i++) 567 if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i]) 568 branch = i; 569 570 branch = branch % interval; 571 for (i = branch; i < 32; i += interval) 572 ohci->ohci_int_load [i] += load; 573 574 return branch; 575 } 576 577 /*-------------------------------------------------------------------------*/ 578 579 /* 2^int( ld (inter)) */ 580 581 static int ep_2_n_interval(int inter) 582 { 583 int i; 584 for (i = 0; ((inter >> i) > 1) && (i < 5); i++); 585 return 1 << i; 586 } 587 588 /*-------------------------------------------------------------------------*/ 589 590 /* the int tree is a binary tree 591 * in order to process it sequentially the indexes of the branches have to 592 * be mapped the mapping reverses the bits of a word of num_bits length */ 593 static int ep_rev(int num_bits, int word) 594 { 595 int i, wout = 0; 596 597 for (i = 0; i < num_bits; i++) 598 wout |= (((word >> i) & 1) << (num_bits - i - 1)); 599 return wout; 600 } 601 602 /*-------------------------------------------------------------------------* 603 * ED handling functions 604 *-------------------------------------------------------------------------*/ 605 606 /* link an ed into one of the HC chains */ 607 608 static int ep_link(ohci_t *ohci, ed_t *edi) 609 { 610 volatile ed_t *ed = edi; 611 int int_branch; 612 int i; 613 int inter; 614 int interval; 615 int load; 616 __u32 *ed_p; 617 618 ed->state = ED_OPER; 619 ed->int_interval = 0; 620 621 switch (ed->type) { 622 case PIPE_CONTROL: 623 ed->hwNextED = 0; 624 if (ohci->ed_controltail == NULL) 625 ohci_writel(ed, &ohci->regs->ed_controlhead); 626 else 627 ohci->ed_controltail->hwNextED = 628 m32_swap((unsigned long)ed); 629 630 ed->ed_prev = ohci->ed_controltail; 631 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && 632 !ohci->ed_rm_list[1] && !ohci->sleeping) { 633 ohci->hc_control |= OHCI_CTRL_CLE; 634 ohci_writel(ohci->hc_control, &ohci->regs->control); 635 } 636 ohci->ed_controltail = edi; 637 break; 638 639 case PIPE_BULK: 640 ed->hwNextED = 0; 641 if (ohci->ed_bulktail == NULL) 642 ohci_writel(ed, &ohci->regs->ed_bulkhead); 643 else 644 ohci->ed_bulktail->hwNextED = 645 m32_swap((unsigned long)ed); 646 647 ed->ed_prev = ohci->ed_bulktail; 648 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && 649 !ohci->ed_rm_list[1] && !ohci->sleeping) { 650 ohci->hc_control |= OHCI_CTRL_BLE; 651 ohci_writel(ohci->hc_control, &ohci->regs->control); 652 } 653 ohci->ed_bulktail = edi; 654 break; 655 656 case PIPE_INTERRUPT: 657 load = ed->int_load; 658 interval = ep_2_n_interval(ed->int_period); 659 ed->int_interval = interval; 660 int_branch = ep_int_ballance(ohci, interval, load); 661 ed->int_branch = int_branch; 662 663 for (i = 0; i < ep_rev(6, interval); i += inter) { 664 inter = 1; 665 for (ed_p = &(ohci->hcca->int_table[\ 666 ep_rev(5, i) + int_branch]); 667 (*ed_p != 0) && 668 (((ed_t *)ed_p)->int_interval >= interval); 669 ed_p = &(((ed_t *)ed_p)->hwNextED)) 670 inter = ep_rev(6, 671 ((ed_t *)ed_p)->int_interval); 672 ed->hwNextED = *ed_p; 673 *ed_p = m32_swap((unsigned long)ed); 674 } 675 break; 676 } 677 return 0; 678 } 679 680 /*-------------------------------------------------------------------------*/ 681 682 /* scan the periodic table to find and unlink this ED */ 683 static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed, 684 unsigned index, unsigned period) 685 { 686 for (; index < NUM_INTS; index += period) { 687 __u32 *ed_p = &ohci->hcca->int_table [index]; 688 689 /* ED might have been unlinked through another path */ 690 while (*ed_p != 0) { 691 if (((struct ed *) 692 m32_swap((unsigned long)ed_p)) == ed) { 693 *ed_p = ed->hwNextED; 694 break; 695 } 696 ed_p = &(((struct ed *) 697 m32_swap((unsigned long)ed_p))->hwNextED); 698 } 699 } 700 } 701 702 /* unlink an ed from one of the HC chains. 703 * just the link to the ed is unlinked. 704 * the link from the ed still points to another operational ed or 0 705 * so the HC can eventually finish the processing of the unlinked ed */ 706 707 static int ep_unlink(ohci_t *ohci, ed_t *edi) 708 { 709 volatile ed_t *ed = edi; 710 int i; 711 712 ed->hwINFO |= m32_swap(OHCI_ED_SKIP); 713 714 switch (ed->type) { 715 case PIPE_CONTROL: 716 if (ed->ed_prev == NULL) { 717 if (!ed->hwNextED) { 718 ohci->hc_control &= ~OHCI_CTRL_CLE; 719 ohci_writel(ohci->hc_control, 720 &ohci->regs->control); 721 } 722 ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)), 723 &ohci->regs->ed_controlhead); 724 } else { 725 ed->ed_prev->hwNextED = ed->hwNextED; 726 } 727 if (ohci->ed_controltail == ed) { 728 ohci->ed_controltail = ed->ed_prev; 729 } else { 730 ((ed_t *)m32_swap( 731 *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; 732 } 733 break; 734 735 case PIPE_BULK: 736 if (ed->ed_prev == NULL) { 737 if (!ed->hwNextED) { 738 ohci->hc_control &= ~OHCI_CTRL_BLE; 739 ohci_writel(ohci->hc_control, 740 &ohci->regs->control); 741 } 742 ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)), 743 &ohci->regs->ed_bulkhead); 744 } else { 745 ed->ed_prev->hwNextED = ed->hwNextED; 746 } 747 if (ohci->ed_bulktail == ed) { 748 ohci->ed_bulktail = ed->ed_prev; 749 } else { 750 ((ed_t *)m32_swap( 751 *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; 752 } 753 break; 754 755 case PIPE_INTERRUPT: 756 periodic_unlink(ohci, ed, 0, 1); 757 for (i = ed->int_branch; i < 32; i += ed->int_interval) 758 ohci->ohci_int_load[i] -= ed->int_load; 759 break; 760 } 761 ed->state = ED_UNLINK; 762 return 0; 763 } 764 765 /*-------------------------------------------------------------------------*/ 766 767 /* add/reinit an endpoint; this should be done once at the 768 * usb_set_configuration command, but the USB stack is a little bit 769 * stateless so we do it at every transaction if the state of the ed 770 * is ED_NEW then a dummy td is added and the state is changed to 771 * ED_UNLINK in all other cases the state is left unchanged the ed 772 * info fields are setted anyway even though most of them should not 773 * change 774 */ 775 static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe, 776 int interval, int load) 777 { 778 td_t *td; 779 ed_t *ed_ret; 780 volatile ed_t *ed; 781 782 ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint(pipe) << 1) | 783 (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))]; 784 785 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { 786 err("ep_add_ed: pending delete"); 787 /* pending delete request */ 788 return NULL; 789 } 790 791 if (ed->state == ED_NEW) { 792 /* dummy td; end of td list for ed */ 793 td = td_alloc(usb_dev); 794 ed->hwTailP = m32_swap((unsigned long)td); 795 ed->hwHeadP = ed->hwTailP; 796 ed->state = ED_UNLINK; 797 ed->type = usb_pipetype(pipe); 798 ohci_dev.ed_cnt++; 799 } 800 801 ed->hwINFO = m32_swap(usb_pipedevice(pipe) 802 | usb_pipeendpoint(pipe) << 7 803 | (usb_pipeisoc(pipe)? 0x8000: 0) 804 | (usb_pipecontrol(pipe)? 0: \ 805 (usb_pipeout(pipe)? 0x800: 0x1000)) 806 | usb_pipeslow(pipe) << 13 807 | usb_maxpacket(usb_dev, pipe) << 16); 808 809 if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) { 810 ed->int_period = interval; 811 ed->int_load = load; 812 } 813 814 return ed_ret; 815 } 816 817 /*-------------------------------------------------------------------------* 818 * TD handling functions 819 *-------------------------------------------------------------------------*/ 820 821 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ 822 823 static void td_fill(ohci_t *ohci, unsigned int info, 824 void *data, int len, 825 struct usb_device *dev, int index, urb_priv_t *urb_priv) 826 { 827 volatile td_t *td, *td_pt; 828 #ifdef OHCI_FILL_TRACE 829 int i; 830 #endif 831 832 if (index > urb_priv->length) { 833 err("index > length"); 834 return; 835 } 836 /* use this td as the next dummy */ 837 td_pt = urb_priv->td [index]; 838 td_pt->hwNextTD = 0; 839 840 /* fill the old dummy TD */ 841 td = urb_priv->td [index] = 842 (td_t *)(m32_swap(urb_priv->ed->hwTailP) & ~0xf); 843 844 td->ed = urb_priv->ed; 845 td->next_dl_td = NULL; 846 td->index = index; 847 td->data = (__u32)data; 848 #ifdef OHCI_FILL_TRACE 849 if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) { 850 for (i = 0; i < len; i++) 851 printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]); 852 printf("\n"); 853 } 854 #endif 855 if (!len) 856 data = 0; 857 858 td->hwINFO = m32_swap(info); 859 td->hwCBP = m32_swap((unsigned long)data); 860 if (data) 861 td->hwBE = m32_swap((unsigned long)(data + len - 1)); 862 else 863 td->hwBE = 0; 864 865 td->hwNextTD = m32_swap((unsigned long)td_pt); 866 867 /* append to queue */ 868 td->ed->hwTailP = td->hwNextTD; 869 } 870 871 /*-------------------------------------------------------------------------*/ 872 873 /* prepare all TDs of a transfer */ 874 875 static void td_submit_job(struct usb_device *dev, unsigned long pipe, 876 void *buffer, int transfer_len, 877 struct devrequest *setup, urb_priv_t *urb, 878 int interval) 879 { 880 ohci_t *ohci = &gohci; 881 int data_len = transfer_len; 882 void *data; 883 int cnt = 0; 884 __u32 info = 0; 885 unsigned int toggle = 0; 886 887 /* OHCI handles the DATA-toggles itself, we just use the USB-toggle 888 * bits for reseting */ 889 if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { 890 toggle = TD_T_TOGGLE; 891 } else { 892 toggle = TD_T_DATA0; 893 usb_settoggle(dev, usb_pipeendpoint(pipe), 894 usb_pipeout(pipe), 1); 895 } 896 urb->td_cnt = 0; 897 if (data_len) 898 data = buffer; 899 else 900 data = 0; 901 902 switch (usb_pipetype(pipe)) { 903 case PIPE_BULK: 904 info = usb_pipeout(pipe)? 905 TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; 906 while (data_len > 4096) { 907 td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), 908 data, 4096, dev, cnt, urb); 909 data += 4096; data_len -= 4096; cnt++; 910 } 911 info = usb_pipeout(pipe)? 912 TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; 913 td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 914 data_len, dev, cnt, urb); 915 cnt++; 916 917 if (!ohci->sleeping) { 918 /* start bulk list */ 919 ohci_writel(OHCI_BLF, &ohci->regs->cmdstatus); 920 } 921 break; 922 923 case PIPE_CONTROL: 924 /* Setup phase */ 925 info = TD_CC | TD_DP_SETUP | TD_T_DATA0; 926 td_fill(ohci, info, setup, 8, dev, cnt++, urb); 927 928 /* Optional Data phase */ 929 if (data_len > 0) { 930 info = usb_pipeout(pipe)? 931 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : 932 TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; 933 /* NOTE: mishandles transfers >8K, some >4K */ 934 td_fill(ohci, info, data, data_len, dev, cnt++, urb); 935 } 936 937 /* Status phase */ 938 info = usb_pipeout(pipe)? 939 TD_CC | TD_DP_IN | TD_T_DATA1: 940 TD_CC | TD_DP_OUT | TD_T_DATA1; 941 td_fill(ohci, info, data, 0, dev, cnt++, urb); 942 943 if (!ohci->sleeping) { 944 /* start Control list */ 945 ohci_writel(OHCI_CLF, &ohci->regs->cmdstatus); 946 } 947 break; 948 949 case PIPE_INTERRUPT: 950 info = usb_pipeout(urb->pipe)? 951 TD_CC | TD_DP_OUT | toggle: 952 TD_CC | TD_R | TD_DP_IN | toggle; 953 td_fill(ohci, info, data, data_len, dev, cnt++, urb); 954 break; 955 } 956 if (urb->length != cnt) 957 dbg("TD LENGTH %d != CNT %d", urb->length, cnt); 958 } 959 960 /*-------------------------------------------------------------------------* 961 * Done List handling functions 962 *-------------------------------------------------------------------------*/ 963 964 /* calculate the transfer length and update the urb */ 965 966 static void dl_transfer_length(td_t *td) 967 { 968 __u32 tdBE, tdCBP; 969 urb_priv_t *lurb_priv = td->ed->purb; 970 971 tdBE = m32_swap(td->hwBE); 972 tdCBP = m32_swap(td->hwCBP); 973 974 if (!(usb_pipecontrol(lurb_priv->pipe) && 975 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { 976 if (tdBE != 0) { 977 if (td->hwCBP == 0) 978 lurb_priv->actual_length += tdBE - td->data + 1; 979 else 980 lurb_priv->actual_length += tdCBP - td->data; 981 } 982 } 983 } 984 985 /*-------------------------------------------------------------------------*/ 986 static void check_status(td_t *td_list) 987 { 988 urb_priv_t *lurb_priv = td_list->ed->purb; 989 int urb_len = lurb_priv->length; 990 __u32 *phwHeadP = &td_list->ed->hwHeadP; 991 int cc; 992 993 cc = TD_CC_GET(m32_swap(td_list->hwINFO)); 994 if (cc) { 995 err(" USB-error: %s (%x)", cc_to_string[cc], cc); 996 997 if (*phwHeadP & m32_swap(0x1)) { 998 if (lurb_priv && 999 ((td_list->index + 1) < urb_len)) { 1000 *phwHeadP = 1001 (lurb_priv->td[urb_len - 1]->hwNextTD &\ 1002 m32_swap(0xfffffff0)) | 1003 (*phwHeadP & m32_swap(0x2)); 1004 1005 lurb_priv->td_cnt += urb_len - 1006 td_list->index - 1; 1007 } else 1008 *phwHeadP &= m32_swap(0xfffffff2); 1009 } 1010 #ifdef CONFIG_MPC5200 1011 td_list->hwNextTD = 0; 1012 #endif 1013 } 1014 } 1015 1016 /* replies to the request have to be on a FIFO basis so 1017 * we reverse the reversed done-list */ 1018 static td_t *dl_reverse_done_list(ohci_t *ohci) 1019 { 1020 __u32 td_list_hc; 1021 td_t *td_rev = NULL; 1022 td_t *td_list = NULL; 1023 1024 td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0; 1025 ohci->hcca->done_head = 0; 1026 1027 while (td_list_hc) { 1028 td_list = (td_t *)td_list_hc; 1029 check_status(td_list); 1030 td_list->next_dl_td = td_rev; 1031 td_rev = td_list; 1032 td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0; 1033 } 1034 return td_list; 1035 } 1036 1037 /*-------------------------------------------------------------------------*/ 1038 /*-------------------------------------------------------------------------*/ 1039 1040 static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status) 1041 { 1042 if ((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL)) 1043 urb->finished = sohci_return_job(ohci, urb); 1044 else 1045 dbg("finish_urb: strange.., ED state %x, \n", status); 1046 } 1047 1048 /* 1049 * Used to take back a TD from the host controller. This would normally be 1050 * called from within dl_done_list, however it may be called directly if the 1051 * HC no longer sees the TD and it has not appeared on the donelist (after 1052 * two frames). This bug has been observed on ZF Micro systems. 1053 */ 1054 static int takeback_td(ohci_t *ohci, td_t *td_list) 1055 { 1056 ed_t *ed; 1057 int cc; 1058 int stat = 0; 1059 /* urb_t *urb; */ 1060 urb_priv_t *lurb_priv; 1061 __u32 tdINFO, edHeadP, edTailP; 1062 1063 tdINFO = m32_swap(td_list->hwINFO); 1064 1065 ed = td_list->ed; 1066 lurb_priv = ed->purb; 1067 1068 dl_transfer_length(td_list); 1069 1070 lurb_priv->td_cnt++; 1071 1072 /* error code of transfer */ 1073 cc = TD_CC_GET(tdINFO); 1074 if (cc) { 1075 err("USB-error: %s (%x)", cc_to_string[cc], cc); 1076 stat = cc_to_error[cc]; 1077 } 1078 1079 /* see if this done list makes for all TD's of current URB, 1080 * and mark the URB finished if so */ 1081 if (lurb_priv->td_cnt == lurb_priv->length) 1082 finish_urb(ohci, lurb_priv, ed->state); 1083 1084 dbg("dl_done_list: processing TD %x, len %x\n", 1085 lurb_priv->td_cnt, lurb_priv->length); 1086 1087 if (ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) { 1088 edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0; 1089 edTailP = m32_swap(ed->hwTailP); 1090 1091 /* unlink eds if they are not busy */ 1092 if ((edHeadP == edTailP) && (ed->state == ED_OPER)) 1093 ep_unlink(ohci, ed); 1094 } 1095 return stat; 1096 } 1097 1098 static int dl_done_list(ohci_t *ohci) 1099 { 1100 int stat = 0; 1101 td_t *td_list = dl_reverse_done_list(ohci); 1102 1103 while (td_list) { 1104 td_t *td_next = td_list->next_dl_td; 1105 stat = takeback_td(ohci, td_list); 1106 td_list = td_next; 1107 } 1108 return stat; 1109 } 1110 1111 /*-------------------------------------------------------------------------* 1112 * Virtual Root Hub 1113 *-------------------------------------------------------------------------*/ 1114 1115 /* Device descriptor */ 1116 static __u8 root_hub_dev_des[] = 1117 { 1118 0x12, /* __u8 bLength; */ 1119 0x01, /* __u8 bDescriptorType; Device */ 1120 0x10, /* __u16 bcdUSB; v1.1 */ 1121 0x01, 1122 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ 1123 0x00, /* __u8 bDeviceSubClass; */ 1124 0x00, /* __u8 bDeviceProtocol; */ 1125 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ 1126 0x00, /* __u16 idVendor; */ 1127 0x00, 1128 0x00, /* __u16 idProduct; */ 1129 0x00, 1130 0x00, /* __u16 bcdDevice; */ 1131 0x00, 1132 0x00, /* __u8 iManufacturer; */ 1133 0x01, /* __u8 iProduct; */ 1134 0x00, /* __u8 iSerialNumber; */ 1135 0x01 /* __u8 bNumConfigurations; */ 1136 }; 1137 1138 /* Configuration descriptor */ 1139 static __u8 root_hub_config_des[] = 1140 { 1141 0x09, /* __u8 bLength; */ 1142 0x02, /* __u8 bDescriptorType; Configuration */ 1143 0x19, /* __u16 wTotalLength; */ 1144 0x00, 1145 0x01, /* __u8 bNumInterfaces; */ 1146 0x01, /* __u8 bConfigurationValue; */ 1147 0x00, /* __u8 iConfiguration; */ 1148 0x40, /* __u8 bmAttributes; 1149 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ 1150 0x00, /* __u8 MaxPower; */ 1151 1152 /* interface */ 1153 0x09, /* __u8 if_bLength; */ 1154 0x04, /* __u8 if_bDescriptorType; Interface */ 1155 0x00, /* __u8 if_bInterfaceNumber; */ 1156 0x00, /* __u8 if_bAlternateSetting; */ 1157 0x01, /* __u8 if_bNumEndpoints; */ 1158 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ 1159 0x00, /* __u8 if_bInterfaceSubClass; */ 1160 0x00, /* __u8 if_bInterfaceProtocol; */ 1161 0x00, /* __u8 if_iInterface; */ 1162 1163 /* endpoint */ 1164 0x07, /* __u8 ep_bLength; */ 1165 0x05, /* __u8 ep_bDescriptorType; Endpoint */ 1166 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ 1167 0x03, /* __u8 ep_bmAttributes; Interrupt */ 1168 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ 1169 0x00, 1170 0xff /* __u8 ep_bInterval; 255 ms */ 1171 }; 1172 1173 static unsigned char root_hub_str_index0[] = 1174 { 1175 0x04, /* __u8 bLength; */ 1176 0x03, /* __u8 bDescriptorType; String-descriptor */ 1177 0x09, /* __u8 lang ID */ 1178 0x04, /* __u8 lang ID */ 1179 }; 1180 1181 static unsigned char root_hub_str_index1[] = 1182 { 1183 28, /* __u8 bLength; */ 1184 0x03, /* __u8 bDescriptorType; String-descriptor */ 1185 'O', /* __u8 Unicode */ 1186 0, /* __u8 Unicode */ 1187 'H', /* __u8 Unicode */ 1188 0, /* __u8 Unicode */ 1189 'C', /* __u8 Unicode */ 1190 0, /* __u8 Unicode */ 1191 'I', /* __u8 Unicode */ 1192 0, /* __u8 Unicode */ 1193 ' ', /* __u8 Unicode */ 1194 0, /* __u8 Unicode */ 1195 'R', /* __u8 Unicode */ 1196 0, /* __u8 Unicode */ 1197 'o', /* __u8 Unicode */ 1198 0, /* __u8 Unicode */ 1199 'o', /* __u8 Unicode */ 1200 0, /* __u8 Unicode */ 1201 't', /* __u8 Unicode */ 1202 0, /* __u8 Unicode */ 1203 ' ', /* __u8 Unicode */ 1204 0, /* __u8 Unicode */ 1205 'H', /* __u8 Unicode */ 1206 0, /* __u8 Unicode */ 1207 'u', /* __u8 Unicode */ 1208 0, /* __u8 Unicode */ 1209 'b', /* __u8 Unicode */ 1210 0, /* __u8 Unicode */ 1211 }; 1212 1213 /* Hub class-specific descriptor is constructed dynamically */ 1214 1215 /*-------------------------------------------------------------------------*/ 1216 1217 #define OK(x) len = (x); break 1218 #ifdef DEBUG 1219 #define WR_RH_STAT(x) {info("WR:status %#8x", (x)); ohci_writel((x), \ 1220 &gohci.regs->roothub.status); } 1221 #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, \ 1222 (x)); ohci_writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); } 1223 #else 1224 #define WR_RH_STAT(x) ohci_writel((x), &gohci.regs->roothub.status) 1225 #define WR_RH_PORTSTAT(x) ohci_writel((x), \ 1226 &gohci.regs->roothub.portstatus[wIndex-1]) 1227 #endif 1228 #define RD_RH_STAT roothub_status(&gohci) 1229 #define RD_RH_PORTSTAT roothub_portstatus(&gohci, wIndex-1) 1230 1231 /* request to virtual root hub */ 1232 1233 int rh_check_port_status(ohci_t *controller) 1234 { 1235 __u32 temp, ndp, i; 1236 int res; 1237 1238 res = -1; 1239 temp = roothub_a(controller); 1240 ndp = (temp & RH_A_NDP); 1241 #ifdef CONFIG_AT91C_PQFP_UHPBUG 1242 ndp = (ndp == 2) ? 1:0; 1243 #endif 1244 for (i = 0; i < ndp; i++) { 1245 temp = roothub_portstatus(controller, i); 1246 /* check for a device disconnect */ 1247 if (((temp & (RH_PS_PESC | RH_PS_CSC)) == 1248 (RH_PS_PESC | RH_PS_CSC)) && 1249 ((temp & RH_PS_CCS) == 0)) { 1250 res = i; 1251 break; 1252 } 1253 } 1254 return res; 1255 } 1256 1257 static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, 1258 void *buffer, int transfer_len, struct devrequest *cmd) 1259 { 1260 void *data = buffer; 1261 int leni = transfer_len; 1262 int len = 0; 1263 int stat = 0; 1264 __u16 bmRType_bReq; 1265 __u16 wValue; 1266 __u16 wIndex; 1267 __u16 wLength; 1268 ALLOC_ALIGN_BUFFER(__u8, databuf, 16, sizeof(u32)); 1269 1270 #ifdef DEBUG 1271 pkt_print(NULL, dev, pipe, buffer, transfer_len, 1272 cmd, "SUB(rh)", usb_pipein(pipe)); 1273 #else 1274 mdelay(1); 1275 #endif 1276 if (usb_pipeint(pipe)) { 1277 info("Root-Hub submit IRQ: NOT implemented"); 1278 return 0; 1279 } 1280 1281 bmRType_bReq = cmd->requesttype | (cmd->request << 8); 1282 wValue = le16_to_cpu(cmd->value); 1283 wIndex = le16_to_cpu(cmd->index); 1284 wLength = le16_to_cpu(cmd->length); 1285 1286 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", 1287 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); 1288 1289 switch (bmRType_bReq) { 1290 /* Request Destination: 1291 without flags: Device, 1292 RH_INTERFACE: interface, 1293 RH_ENDPOINT: endpoint, 1294 RH_CLASS means HUB here, 1295 RH_OTHER | RH_CLASS almost ever means HUB_PORT here 1296 */ 1297 1298 case RH_GET_STATUS: 1299 *(u16 *)databuf = cpu_to_le16(1); 1300 OK(2); 1301 case RH_GET_STATUS | RH_INTERFACE: 1302 *(u16 *)databuf = cpu_to_le16(0); 1303 OK(2); 1304 case RH_GET_STATUS | RH_ENDPOINT: 1305 *(u16 *)databuf = cpu_to_le16(0); 1306 OK(2); 1307 case RH_GET_STATUS | RH_CLASS: 1308 *(u32 *)databuf = cpu_to_le32( 1309 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); 1310 OK(4); 1311 case RH_GET_STATUS | RH_OTHER | RH_CLASS: 1312 *(u32 *)databuf = cpu_to_le32(RD_RH_PORTSTAT); 1313 OK(4); 1314 1315 case RH_CLEAR_FEATURE | RH_ENDPOINT: 1316 switch (wValue) { 1317 case (RH_ENDPOINT_STALL): 1318 OK(0); 1319 } 1320 break; 1321 1322 case RH_CLEAR_FEATURE | RH_CLASS: 1323 switch (wValue) { 1324 case RH_C_HUB_LOCAL_POWER: 1325 OK(0); 1326 case (RH_C_HUB_OVER_CURRENT): 1327 WR_RH_STAT(RH_HS_OCIC); 1328 OK(0); 1329 } 1330 break; 1331 1332 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: 1333 switch (wValue) { 1334 case (RH_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_CCS); OK(0); 1335 case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_POCI); OK(0); 1336 case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_LSDA); OK(0); 1337 case (RH_C_PORT_CONNECTION): WR_RH_PORTSTAT(RH_PS_CSC); OK(0); 1338 case (RH_C_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_PESC); OK(0); 1339 case (RH_C_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSSC); OK(0); 1340 case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0); 1341 case (RH_C_PORT_RESET): WR_RH_PORTSTAT(RH_PS_PRSC); OK(0); 1342 } 1343 break; 1344 1345 case RH_SET_FEATURE | RH_OTHER | RH_CLASS: 1346 switch (wValue) { 1347 case (RH_PORT_SUSPEND): 1348 WR_RH_PORTSTAT(RH_PS_PSS); OK(0); 1349 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ 1350 if (RD_RH_PORTSTAT & RH_PS_CCS) 1351 WR_RH_PORTSTAT(RH_PS_PRS); 1352 OK(0); 1353 case (RH_PORT_POWER): 1354 WR_RH_PORTSTAT(RH_PS_PPS); 1355 mdelay(100); 1356 OK(0); 1357 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ 1358 if (RD_RH_PORTSTAT & RH_PS_CCS) 1359 WR_RH_PORTSTAT(RH_PS_PES); 1360 OK(0); 1361 } 1362 break; 1363 1364 case RH_SET_ADDRESS: 1365 gohci.rh.devnum = wValue; 1366 OK(0); 1367 1368 case RH_GET_DESCRIPTOR: 1369 switch ((wValue & 0xff00) >> 8) { 1370 case (0x01): /* device descriptor */ 1371 len = min_t(unsigned int, 1372 leni, 1373 min_t(unsigned int, 1374 sizeof(root_hub_dev_des), 1375 wLength)); 1376 databuf = root_hub_dev_des; OK(len); 1377 case (0x02): /* configuration descriptor */ 1378 len = min_t(unsigned int, 1379 leni, 1380 min_t(unsigned int, 1381 sizeof(root_hub_config_des), 1382 wLength)); 1383 databuf = root_hub_config_des; OK(len); 1384 case (0x03): /* string descriptors */ 1385 if (wValue == 0x0300) { 1386 len = min_t(unsigned int, 1387 leni, 1388 min_t(unsigned int, 1389 sizeof(root_hub_str_index0), 1390 wLength)); 1391 databuf = root_hub_str_index0; 1392 OK(len); 1393 } 1394 if (wValue == 0x0301) { 1395 len = min_t(unsigned int, 1396 leni, 1397 min_t(unsigned int, 1398 sizeof(root_hub_str_index1), 1399 wLength)); 1400 databuf = root_hub_str_index1; 1401 OK(len); 1402 } 1403 default: 1404 stat = USB_ST_STALLED; 1405 } 1406 break; 1407 1408 case RH_GET_DESCRIPTOR | RH_CLASS: 1409 { 1410 __u32 temp = roothub_a(&gohci); 1411 1412 databuf[0] = 9; /* min length; */ 1413 databuf[1] = 0x29; 1414 databuf[2] = temp & RH_A_NDP; 1415 #ifdef CONFIG_AT91C_PQFP_UHPBUG 1416 databuf[2] = (databuf[2] == 2) ? 1 : 0; 1417 #endif 1418 databuf[3] = 0; 1419 if (temp & RH_A_PSM) /* per-port power switching? */ 1420 databuf[3] |= 0x1; 1421 if (temp & RH_A_NOCP) /* no overcurrent reporting? */ 1422 databuf[3] |= 0x10; 1423 else if (temp & RH_A_OCPM)/* per-port overcurrent reporting? */ 1424 databuf[3] |= 0x8; 1425 1426 databuf[4] = 0; 1427 databuf[5] = (temp & RH_A_POTPGT) >> 24; 1428 databuf[6] = 0; 1429 temp = roothub_b(&gohci); 1430 databuf[7] = temp & RH_B_DR; 1431 if (databuf[2] < 7) { 1432 databuf[8] = 0xff; 1433 } else { 1434 databuf[0] += 2; 1435 databuf[8] = (temp & RH_B_DR) >> 8; 1436 databuf[10] = databuf[9] = 0xff; 1437 } 1438 1439 len = min_t(unsigned int, leni, 1440 min_t(unsigned int, databuf[0], wLength)); 1441 OK(len); 1442 } 1443 1444 case RH_GET_CONFIGURATION: 1445 databuf[0] = 0x01; 1446 OK(1); 1447 1448 case RH_SET_CONFIGURATION: 1449 WR_RH_STAT(0x10000); 1450 OK(0); 1451 1452 default: 1453 dbg("unsupported root hub command"); 1454 stat = USB_ST_STALLED; 1455 } 1456 1457 #ifdef DEBUG 1458 ohci_dump_roothub(&gohci, 1); 1459 #else 1460 mdelay(1); 1461 #endif 1462 1463 len = min_t(int, len, leni); 1464 if (data != databuf) 1465 memcpy(data, databuf, len); 1466 dev->act_len = len; 1467 dev->status = stat; 1468 1469 #ifdef DEBUG 1470 pkt_print(NULL, dev, pipe, buffer, 1471 transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); 1472 #else 1473 mdelay(1); 1474 #endif 1475 1476 return stat; 1477 } 1478 1479 /*-------------------------------------------------------------------------*/ 1480 1481 /* common code for handling submit messages - used for all but root hub */ 1482 /* accesses. */ 1483 int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1484 int transfer_len, struct devrequest *setup, int interval) 1485 { 1486 int stat = 0; 1487 int maxsize = usb_maxpacket(dev, pipe); 1488 int timeout; 1489 urb_priv_t *urb; 1490 1491 urb = malloc(sizeof(urb_priv_t)); 1492 memset(urb, 0, sizeof(urb_priv_t)); 1493 1494 urb->dev = dev; 1495 urb->pipe = pipe; 1496 urb->transfer_buffer = buffer; 1497 urb->transfer_buffer_length = transfer_len; 1498 urb->interval = interval; 1499 1500 /* device pulled? Shortcut the action. */ 1501 if (devgone == dev) { 1502 dev->status = USB_ST_CRC_ERR; 1503 return 0; 1504 } 1505 1506 #ifdef DEBUG 1507 urb->actual_length = 0; 1508 pkt_print(urb, dev, pipe, buffer, transfer_len, 1509 setup, "SUB", usb_pipein(pipe)); 1510 #else 1511 mdelay(1); 1512 #endif 1513 if (!maxsize) { 1514 err("submit_common_message: pipesize for pipe %lx is zero", 1515 pipe); 1516 return -1; 1517 } 1518 1519 if (sohci_submit_job(urb, setup) < 0) { 1520 err("sohci_submit_job failed"); 1521 return -1; 1522 } 1523 1524 #if 0 1525 mdelay(10); 1526 /* ohci_dump_status(&gohci); */ 1527 #endif 1528 1529 timeout = USB_TIMEOUT_MS(pipe); 1530 1531 /* wait for it to complete */ 1532 for (;;) { 1533 /* check whether the controller is done */ 1534 stat = hc_interrupt(); 1535 if (stat < 0) { 1536 stat = USB_ST_CRC_ERR; 1537 break; 1538 } 1539 1540 /* NOTE: since we are not interrupt driven in U-Boot and always 1541 * handle only one URB at a time, we cannot assume the 1542 * transaction finished on the first successful return from 1543 * hc_interrupt().. unless the flag for current URB is set, 1544 * meaning that all TD's to/from device got actually 1545 * transferred and processed. If the current URB is not 1546 * finished we need to re-iterate this loop so as 1547 * hc_interrupt() gets called again as there needs to be some 1548 * more TD's to process still */ 1549 if ((stat >= 0) && (stat != 0xff) && (urb->finished)) { 1550 /* 0xff is returned for an SF-interrupt */ 1551 break; 1552 } 1553 1554 if (--timeout) { 1555 mdelay(1); 1556 if (!urb->finished) 1557 dbg("*"); 1558 1559 } else { 1560 err("CTL:TIMEOUT "); 1561 dbg("submit_common_msg: TO status %x\n", stat); 1562 urb->finished = 1; 1563 stat = USB_ST_CRC_ERR; 1564 break; 1565 } 1566 } 1567 1568 dev->status = stat; 1569 dev->act_len = transfer_len; 1570 1571 #ifdef DEBUG 1572 pkt_print(urb, dev, pipe, buffer, transfer_len, 1573 setup, "RET(ctlr)", usb_pipein(pipe)); 1574 #else 1575 mdelay(1); 1576 #endif 1577 1578 /* free TDs in urb_priv */ 1579 if (!usb_pipeint(pipe)) 1580 urb_free_priv(urb); 1581 return 0; 1582 } 1583 1584 /* submit routines called from usb.c */ 1585 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1586 int transfer_len) 1587 { 1588 info("submit_bulk_msg"); 1589 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); 1590 } 1591 1592 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1593 int transfer_len, struct devrequest *setup) 1594 { 1595 int maxsize = usb_maxpacket(dev, pipe); 1596 1597 info("submit_control_msg"); 1598 #ifdef DEBUG 1599 pkt_print(NULL, dev, pipe, buffer, transfer_len, 1600 setup, "SUB", usb_pipein(pipe)); 1601 #else 1602 mdelay(1); 1603 #endif 1604 if (!maxsize) { 1605 err("submit_control_message: pipesize for pipe %lx is zero", 1606 pipe); 1607 return -1; 1608 } 1609 if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { 1610 gohci.rh.dev = dev; 1611 /* root hub - redirect */ 1612 return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, 1613 setup); 1614 } 1615 1616 return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); 1617 } 1618 1619 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1620 int transfer_len, int interval) 1621 { 1622 info("submit_int_msg"); 1623 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 1624 interval); 1625 } 1626 1627 /*-------------------------------------------------------------------------* 1628 * HC functions 1629 *-------------------------------------------------------------------------*/ 1630 1631 /* reset the HC and BUS */ 1632 1633 static int hc_reset(ohci_t *ohci) 1634 { 1635 #ifdef CONFIG_PCI_EHCI_DEVNO 1636 pci_dev_t pdev; 1637 #endif 1638 int timeout = 30; 1639 int smm_timeout = 50; /* 0,5 sec */ 1640 1641 dbg("%s\n", __FUNCTION__); 1642 1643 #ifdef CONFIG_PCI_EHCI_DEVNO 1644 /* 1645 * Some multi-function controllers (e.g. ISP1562) allow root hub 1646 * resetting via EHCI registers only. 1647 */ 1648 pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO); 1649 if (pdev != -1) { 1650 u32 base; 1651 int timeout = 1000; 1652 1653 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); 1654 base += EHCI_USBCMD_OFF; 1655 ohci_writel(ohci_readl(base) | EHCI_USBCMD_HCRESET, base); 1656 1657 while (ohci_readl(base) & EHCI_USBCMD_HCRESET) { 1658 if (timeout-- <= 0) { 1659 printf("USB RootHub reset timed out!"); 1660 break; 1661 } 1662 udelay(1); 1663 } 1664 } else 1665 printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO); 1666 #endif 1667 if (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { 1668 /* SMM owns the HC, request ownership */ 1669 ohci_writel(OHCI_OCR, &ohci->regs->cmdstatus); 1670 info("USB HC TakeOver from SMM"); 1671 while (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { 1672 mdelay(10); 1673 if (--smm_timeout == 0) { 1674 err("USB HC TakeOver failed!"); 1675 return -1; 1676 } 1677 } 1678 } 1679 1680 /* Disable HC interrupts */ 1681 ohci_writel(OHCI_INTR_MIE, &ohci->regs->intrdisable); 1682 1683 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n", 1684 ohci->slot_name, 1685 ohci_readl(&ohci->regs->control)); 1686 1687 /* Reset USB (needed by some controllers) */ 1688 ohci->hc_control = 0; 1689 ohci_writel(ohci->hc_control, &ohci->regs->control); 1690 1691 /* HC Reset requires max 10 us delay */ 1692 ohci_writel(OHCI_HCR, &ohci->regs->cmdstatus); 1693 while ((ohci_readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { 1694 if (--timeout == 0) { 1695 err("USB HC reset timed out!"); 1696 return -1; 1697 } 1698 udelay(1); 1699 } 1700 return 0; 1701 } 1702 1703 /*-------------------------------------------------------------------------*/ 1704 1705 /* Start an OHCI controller, set the BUS operational 1706 * enable interrupts 1707 * connect the virtual root hub */ 1708 1709 static int hc_start(ohci_t *ohci) 1710 { 1711 __u32 mask; 1712 unsigned int fminterval; 1713 1714 ohci->disabled = 1; 1715 1716 /* Tell the controller where the control and bulk lists are 1717 * The lists are empty now. */ 1718 1719 ohci_writel(0, &ohci->regs->ed_controlhead); 1720 ohci_writel(0, &ohci->regs->ed_bulkhead); 1721 1722 ohci_writel((__u32)ohci->hcca, 1723 &ohci->regs->hcca); /* reset clears this */ 1724 1725 fminterval = 0x2edf; 1726 ohci_writel((fminterval * 9) / 10, &ohci->regs->periodicstart); 1727 fminterval |= ((((fminterval - 210) * 6) / 7) << 16); 1728 ohci_writel(fminterval, &ohci->regs->fminterval); 1729 ohci_writel(0x628, &ohci->regs->lsthresh); 1730 1731 /* start controller operations */ 1732 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; 1733 ohci->disabled = 0; 1734 ohci_writel(ohci->hc_control, &ohci->regs->control); 1735 1736 /* disable all interrupts */ 1737 mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | 1738 OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | 1739 OHCI_INTR_OC | OHCI_INTR_MIE); 1740 ohci_writel(mask, &ohci->regs->intrdisable); 1741 /* clear all interrupts */ 1742 mask &= ~OHCI_INTR_MIE; 1743 ohci_writel(mask, &ohci->regs->intrstatus); 1744 /* Choose the interrupts we care about now - but w/o MIE */ 1745 mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; 1746 ohci_writel(mask, &ohci->regs->intrenable); 1747 1748 #ifdef OHCI_USE_NPS 1749 /* required for AMD-756 and some Mac platforms */ 1750 ohci_writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM, 1751 &ohci->regs->roothub.a); 1752 ohci_writel(RH_HS_LPSC, &ohci->regs->roothub.status); 1753 #endif /* OHCI_USE_NPS */ 1754 1755 /* POTPGT delay is bits 24-31, in 2 ms units. */ 1756 mdelay((roothub_a(ohci) >> 23) & 0x1fe); 1757 1758 /* connect the virtual root hub */ 1759 ohci->rh.devnum = 0; 1760 1761 return 0; 1762 } 1763 1764 /*-------------------------------------------------------------------------*/ 1765 1766 /* an interrupt happens */ 1767 1768 static int hc_interrupt(void) 1769 { 1770 ohci_t *ohci = &gohci; 1771 struct ohci_regs *regs = ohci->regs; 1772 int ints; 1773 int stat = -1; 1774 1775 if ((ohci->hcca->done_head != 0) && 1776 !(m32_swap(ohci->hcca->done_head) & 0x01)) { 1777 ints = OHCI_INTR_WDH; 1778 } else { 1779 ints = ohci_readl(®s->intrstatus); 1780 if (ints == ~(u32)0) { 1781 ohci->disabled++; 1782 err("%s device removed!", ohci->slot_name); 1783 return -1; 1784 } else { 1785 ints &= ohci_readl(®s->intrenable); 1786 if (ints == 0) { 1787 dbg("hc_interrupt: returning..\n"); 1788 return 0xff; 1789 } 1790 } 1791 } 1792 1793 /* dbg("Interrupt: %x frame: %x", ints, 1794 le16_to_cpu(ohci->hcca->frame_no)); */ 1795 1796 if (ints & OHCI_INTR_RHSC) 1797 stat = 0xff; 1798 1799 if (ints & OHCI_INTR_UE) { 1800 ohci->disabled++; 1801 err("OHCI Unrecoverable Error, controller usb-%s disabled", 1802 ohci->slot_name); 1803 /* e.g. due to PCI Master/Target Abort */ 1804 1805 #ifdef DEBUG 1806 ohci_dump(ohci, 1); 1807 #else 1808 mdelay(1); 1809 #endif 1810 /* FIXME: be optimistic, hope that bug won't repeat often. */ 1811 /* Make some non-interrupt context restart the controller. */ 1812 /* Count and limit the retries though; either hardware or */ 1813 /* software errors can go forever... */ 1814 hc_reset(ohci); 1815 return -1; 1816 } 1817 1818 if (ints & OHCI_INTR_WDH) { 1819 mdelay(1); 1820 ohci_writel(OHCI_INTR_WDH, ®s->intrdisable); 1821 (void)ohci_readl(®s->intrdisable); /* flush */ 1822 stat = dl_done_list(&gohci); 1823 ohci_writel(OHCI_INTR_WDH, ®s->intrenable); 1824 (void)ohci_readl(®s->intrdisable); /* flush */ 1825 } 1826 1827 if (ints & OHCI_INTR_SO) { 1828 dbg("USB Schedule overrun\n"); 1829 ohci_writel(OHCI_INTR_SO, ®s->intrenable); 1830 stat = -1; 1831 } 1832 1833 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ 1834 if (ints & OHCI_INTR_SF) { 1835 unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1; 1836 mdelay(1); 1837 ohci_writel(OHCI_INTR_SF, ®s->intrdisable); 1838 if (ohci->ed_rm_list[frame] != NULL) 1839 ohci_writel(OHCI_INTR_SF, ®s->intrenable); 1840 stat = 0xff; 1841 } 1842 1843 ohci_writel(ints, ®s->intrstatus); 1844 return stat; 1845 } 1846 1847 /*-------------------------------------------------------------------------*/ 1848 1849 /*-------------------------------------------------------------------------*/ 1850 1851 /* De-allocate all resources.. */ 1852 1853 static void hc_release_ohci(ohci_t *ohci) 1854 { 1855 dbg("USB HC release ohci usb-%s", ohci->slot_name); 1856 1857 if (!ohci->disabled) 1858 hc_reset(ohci); 1859 } 1860 1861 /*-------------------------------------------------------------------------*/ 1862 1863 /* 1864 * low level initalisation routine, called from usb.c 1865 */ 1866 static char ohci_inited = 0; 1867 1868 int usb_lowlevel_init(void) 1869 { 1870 #ifdef CONFIG_PCI_OHCI 1871 pci_dev_t pdev; 1872 #endif 1873 1874 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT 1875 /* cpu dependant init */ 1876 if (usb_cpu_init()) 1877 return -1; 1878 #endif 1879 1880 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT 1881 /* board dependant init */ 1882 if (usb_board_init()) 1883 return -1; 1884 #endif 1885 memset(&gohci, 0, sizeof(ohci_t)); 1886 1887 /* align the storage */ 1888 if ((__u32)&ghcca[0] & 0xff) { 1889 err("HCCA not aligned!!"); 1890 return -1; 1891 } 1892 phcca = &ghcca[0]; 1893 info("aligned ghcca %p", phcca); 1894 memset(&ohci_dev, 0, sizeof(struct ohci_device)); 1895 if ((__u32)&ohci_dev.ed[0] & 0x7) { 1896 err("EDs not aligned!!"); 1897 return -1; 1898 } 1899 memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); 1900 if ((__u32)gtd & 0x7) { 1901 err("TDs not aligned!!"); 1902 return -1; 1903 } 1904 ptd = gtd; 1905 gohci.hcca = phcca; 1906 memset(phcca, 0, sizeof(struct ohci_hcca)); 1907 1908 gohci.disabled = 1; 1909 gohci.sleeping = 0; 1910 gohci.irq = -1; 1911 #ifdef CONFIG_PCI_OHCI 1912 pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO); 1913 1914 if (pdev != -1) { 1915 u16 vid, did; 1916 u32 base; 1917 pci_read_config_word(pdev, PCI_VENDOR_ID, &vid); 1918 pci_read_config_word(pdev, PCI_DEVICE_ID, &did); 1919 printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n", 1920 vid, did, (pdev >> 16) & 0xff, 1921 (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); 1922 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); 1923 printf("OHCI regs address 0x%08x\n", base); 1924 gohci.regs = (struct ohci_regs *)base; 1925 } else 1926 return -1; 1927 #else 1928 gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE; 1929 #endif 1930 1931 gohci.flags = 0; 1932 gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME; 1933 1934 if (hc_reset (&gohci) < 0) { 1935 hc_release_ohci (&gohci); 1936 err ("can't reset usb-%s", gohci.slot_name); 1937 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT 1938 /* board dependant cleanup */ 1939 usb_board_init_fail(); 1940 #endif 1941 1942 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT 1943 /* cpu dependant cleanup */ 1944 usb_cpu_init_fail(); 1945 #endif 1946 return -1; 1947 } 1948 1949 if (hc_start(&gohci) < 0) { 1950 err("can't start usb-%s", gohci.slot_name); 1951 hc_release_ohci(&gohci); 1952 /* Initialization failed */ 1953 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT 1954 /* board dependant cleanup */ 1955 usb_board_stop(); 1956 #endif 1957 1958 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT 1959 /* cpu dependant cleanup */ 1960 usb_cpu_stop(); 1961 #endif 1962 return -1; 1963 } 1964 1965 #ifdef DEBUG 1966 ohci_dump(&gohci, 1); 1967 #else 1968 mdelay(1); 1969 #endif 1970 ohci_inited = 1; 1971 return 0; 1972 } 1973 1974 int usb_lowlevel_stop(void) 1975 { 1976 /* this gets called really early - before the controller has */ 1977 /* even been initialized! */ 1978 if (!ohci_inited) 1979 return 0; 1980 /* TODO release any interrupts, etc. */ 1981 /* call hc_release_ohci() here ? */ 1982 hc_reset(&gohci); 1983 1984 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT 1985 /* board dependant cleanup */ 1986 if (usb_board_stop()) 1987 return -1; 1988 #endif 1989 1990 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT 1991 /* cpu dependant cleanup */ 1992 if (usb_cpu_stop()) 1993 return -1; 1994 #endif 1995 /* This driver is no longer initialised. It needs a new low-level 1996 * init (board/cpu) before it can be used again. */ 1997 ohci_inited = 0; 1998 return 0; 1999 } 2000