1 /* 2 * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus. 3 * 4 * Interrupt support is added. Now, it has been tested 5 * on ULI1575 chip and works well with USB keyboard. 6 * 7 * (C) Copyright 2007 8 * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com> 9 * 10 * (C) Copyright 2003 11 * Gary Jennejohn, DENX Software Engineering <garyj@denx.de> 12 * 13 * Note: Much of this code has been derived from Linux 2.4 14 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 15 * (C) Copyright 2000-2002 David Brownell 16 * 17 * Modified for the MP2USB by (C) Copyright 2005 Eric Benard 18 * ebenard@eukrea.com - based on s3c24x0's driver 19 * 20 * See file CREDITS for list of people who contributed to this 21 * project. 22 * 23 * This program is free software; you can redistribute it and/or 24 * modify it under the terms of the GNU General Public License as 25 * published by the Free Software Foundation; either version 2 of 26 * the License, or (at your option) any later version. 27 * 28 * This program is distributed in the hope that it will be useful, 29 * but WITHOUT ANY WARRANTY; without even the implied warranty of 30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 31 * GNU General Public License for more details. 32 * 33 * You should have received a copy of the GNU General Public License 34 * along with this program; if not, write to the Free Software 35 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 36 * MA 02111-1307 USA 37 * 38 */ 39 /* 40 * IMPORTANT NOTES 41 * 1 - Read doc/README.generic_usb_ohci 42 * 2 - this driver is intended for use with USB Mass Storage Devices 43 * (BBB) and USB keyboard. There is NO support for Isochronous pipes! 44 * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG 45 * to activate workaround for bug #41 or this driver will NOT work! 46 */ 47 48 #include <common.h> 49 #include <asm/byteorder.h> 50 51 #if defined(CONFIG_PCI_OHCI) 52 # include <pci.h> 53 #if !defined(CONFIG_PCI_OHCI_DEVNO) 54 #define CONFIG_PCI_OHCI_DEVNO 0 55 #endif 56 #endif 57 58 #include <malloc.h> 59 #include <usb.h> 60 61 #include "ohci.h" 62 63 #ifdef CONFIG_AT91RM9200 64 #include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */ 65 #endif 66 67 #if defined(CONFIG_ARM920T) || \ 68 defined(CONFIG_S3C24X0) || \ 69 defined(CONFIG_440EP) || \ 70 defined(CONFIG_PCI_OHCI) || \ 71 defined(CONFIG_MPC5200) || \ 72 defined(CONFIG_SYS_OHCI_USE_NPS) 73 # define OHCI_USE_NPS /* force NoPowerSwitching mode */ 74 #endif 75 76 #undef OHCI_VERBOSE_DEBUG /* not always helpful */ 77 #undef DEBUG 78 #undef SHOW_INFO 79 #undef OHCI_FILL_TRACE 80 81 /* For initializing controller (mask in an HCFS mode too) */ 82 #define OHCI_CONTROL_INIT \ 83 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE 84 85 #define min_t(type, x, y) \ 86 ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) 87 88 #ifdef CONFIG_PCI_OHCI 89 static struct pci_device_id ohci_pci_ids[] = { 90 {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ 91 {0x1033, 0x0035}, /* NEC PCI OHCI module ids */ 92 {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */ 93 /* Please add supported PCI OHCI controller ids here */ 94 {0, 0} 95 }; 96 #endif 97 98 #ifdef CONFIG_PCI_EHCI_DEVNO 99 static struct pci_device_id ehci_pci_ids[] = { 100 {0x1131, 0x1562}, /* Philips 1562 PCI EHCI module ids */ 101 /* Please add supported PCI EHCI controller ids here */ 102 {0, 0} 103 }; 104 #endif 105 106 #ifdef DEBUG 107 #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) 108 #else 109 #define dbg(format, arg...) do {} while (0) 110 #endif /* DEBUG */ 111 #define err(format, arg...) printf("ERROR: " format "\n", ## arg) 112 #ifdef SHOW_INFO 113 #define info(format, arg...) printf("INFO: " format "\n", ## arg) 114 #else 115 #define info(format, arg...) do {} while (0) 116 #endif 117 118 #ifdef CONFIG_SYS_OHCI_BE_CONTROLLER 119 # define m16_swap(x) cpu_to_be16(x) 120 # define m32_swap(x) cpu_to_be32(x) 121 #else 122 # define m16_swap(x) cpu_to_le16(x) 123 # define m32_swap(x) cpu_to_le32(x) 124 #endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */ 125 126 /* global ohci_t */ 127 static ohci_t gohci; 128 /* this must be aligned to a 256 byte boundary */ 129 struct ohci_hcca ghcca[1]; 130 /* a pointer to the aligned storage */ 131 struct ohci_hcca *phcca; 132 /* this allocates EDs for all possible endpoints */ 133 struct ohci_device ohci_dev; 134 /* device which was disconnected */ 135 struct usb_device *devgone; 136 137 static inline u32 roothub_a(struct ohci *hc) 138 { return ohci_readl(&hc->regs->roothub.a); } 139 static inline u32 roothub_b(struct ohci *hc) 140 { return ohci_readl(&hc->regs->roothub.b); } 141 static inline u32 roothub_status(struct ohci *hc) 142 { return ohci_readl(&hc->regs->roothub.status); } 143 static inline u32 roothub_portstatus(struct ohci *hc, int i) 144 { return ohci_readl(&hc->regs->roothub.portstatus[i]); } 145 146 /* forward declaration */ 147 static int hc_interrupt(void); 148 static void td_submit_job(struct usb_device *dev, unsigned long pipe, 149 void *buffer, int transfer_len, 150 struct devrequest *setup, urb_priv_t *urb, 151 int interval); 152 153 /*-------------------------------------------------------------------------* 154 * URB support functions 155 *-------------------------------------------------------------------------*/ 156 157 /* free HCD-private data associated with this URB */ 158 159 static void urb_free_priv(urb_priv_t *urb) 160 { 161 int i; 162 int last; 163 struct td *td; 164 165 last = urb->length - 1; 166 if (last >= 0) { 167 for (i = 0; i <= last; i++) { 168 td = urb->td[i]; 169 if (td) { 170 td->usb_dev = NULL; 171 urb->td[i] = NULL; 172 } 173 } 174 } 175 free(urb); 176 } 177 178 /*-------------------------------------------------------------------------*/ 179 180 #ifdef DEBUG 181 static int sohci_get_current_frame_number(struct usb_device *dev); 182 183 /* debug| print the main components of an URB 184 * small: 0) header + data packets 1) just header */ 185 186 static void pkt_print(urb_priv_t *purb, struct usb_device *dev, 187 unsigned long pipe, void *buffer, int transfer_len, 188 struct devrequest *setup, char *str, int small) 189 { 190 dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx", 191 str, 192 sohci_get_current_frame_number(dev), 193 usb_pipedevice(pipe), 194 usb_pipeendpoint(pipe), 195 usb_pipeout(pipe)? 'O': 'I', 196 usb_pipetype(pipe) < 2 ? \ 197 (usb_pipeint(pipe)? "INTR": "ISOC"): \ 198 (usb_pipecontrol(pipe)? "CTRL": "BULK"), 199 (purb ? purb->actual_length : 0), 200 transfer_len, dev->status); 201 #ifdef OHCI_VERBOSE_DEBUG 202 if (!small) { 203 int i, len; 204 205 if (usb_pipecontrol(pipe)) { 206 printf(__FILE__ ": cmd(8):"); 207 for (i = 0; i < 8 ; i++) 208 printf(" %02x", ((__u8 *) setup) [i]); 209 printf("\n"); 210 } 211 if (transfer_len > 0 && buffer) { 212 printf(__FILE__ ": data(%d/%d):", 213 (purb ? purb->actual_length : 0), 214 transfer_len); 215 len = usb_pipeout(pipe)? transfer_len: 216 (purb ? purb->actual_length : 0); 217 for (i = 0; i < 16 && i < len; i++) 218 printf(" %02x", ((__u8 *) buffer) [i]); 219 printf("%s\n", i < len? "...": ""); 220 } 221 } 222 #endif 223 } 224 225 /* just for debugging; prints non-empty branches of the int ed tree 226 * inclusive iso eds */ 227 void ep_print_int_eds(ohci_t *ohci, char *str) 228 { 229 int i, j; 230 __u32 *ed_p; 231 for (i = 0; i < 32; i++) { 232 j = 5; 233 ed_p = &(ohci->hcca->int_table [i]); 234 if (*ed_p == 0) 235 continue; 236 printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i); 237 while (*ed_p != 0 && j--) { 238 ed_t *ed = (ed_t *)m32_swap(ed_p); 239 printf(" ed: %4x;", ed->hwINFO); 240 ed_p = &ed->hwNextED; 241 } 242 printf("\n"); 243 } 244 } 245 246 static void ohci_dump_intr_mask(char *label, __u32 mask) 247 { 248 dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s", 249 label, 250 mask, 251 (mask & OHCI_INTR_MIE) ? " MIE" : "", 252 (mask & OHCI_INTR_OC) ? " OC" : "", 253 (mask & OHCI_INTR_RHSC) ? " RHSC" : "", 254 (mask & OHCI_INTR_FNO) ? " FNO" : "", 255 (mask & OHCI_INTR_UE) ? " UE" : "", 256 (mask & OHCI_INTR_RD) ? " RD" : "", 257 (mask & OHCI_INTR_SF) ? " SF" : "", 258 (mask & OHCI_INTR_WDH) ? " WDH" : "", 259 (mask & OHCI_INTR_SO) ? " SO" : "" 260 ); 261 } 262 263 static void maybe_print_eds(char *label, __u32 value) 264 { 265 ed_t *edp = (ed_t *)value; 266 267 if (value) { 268 dbg("%s %08x", label, value); 269 dbg("%08x", edp->hwINFO); 270 dbg("%08x", edp->hwTailP); 271 dbg("%08x", edp->hwHeadP); 272 dbg("%08x", edp->hwNextED); 273 } 274 } 275 276 static char *hcfs2string(int state) 277 { 278 switch (state) { 279 case OHCI_USB_RESET: return "reset"; 280 case OHCI_USB_RESUME: return "resume"; 281 case OHCI_USB_OPER: return "operational"; 282 case OHCI_USB_SUSPEND: return "suspend"; 283 } 284 return "?"; 285 } 286 287 /* dump control and status registers */ 288 static void ohci_dump_status(ohci_t *controller) 289 { 290 struct ohci_regs *regs = controller->regs; 291 __u32 temp; 292 293 temp = ohci_readl(®s->revision) & 0xff; 294 if (temp != 0x10) 295 dbg("spec %d.%d", (temp >> 4), (temp & 0x0f)); 296 297 temp = ohci_readl(®s->control); 298 dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, 299 (temp & OHCI_CTRL_RWE) ? " RWE" : "", 300 (temp & OHCI_CTRL_RWC) ? " RWC" : "", 301 (temp & OHCI_CTRL_IR) ? " IR" : "", 302 hcfs2string(temp & OHCI_CTRL_HCFS), 303 (temp & OHCI_CTRL_BLE) ? " BLE" : "", 304 (temp & OHCI_CTRL_CLE) ? " CLE" : "", 305 (temp & OHCI_CTRL_IE) ? " IE" : "", 306 (temp & OHCI_CTRL_PLE) ? " PLE" : "", 307 temp & OHCI_CTRL_CBSR 308 ); 309 310 temp = ohci_readl(®s->cmdstatus); 311 dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, 312 (temp & OHCI_SOC) >> 16, 313 (temp & OHCI_OCR) ? " OCR" : "", 314 (temp & OHCI_BLF) ? " BLF" : "", 315 (temp & OHCI_CLF) ? " CLF" : "", 316 (temp & OHCI_HCR) ? " HCR" : "" 317 ); 318 319 ohci_dump_intr_mask("intrstatus", ohci_readl(®s->intrstatus)); 320 ohci_dump_intr_mask("intrenable", ohci_readl(®s->intrenable)); 321 322 maybe_print_eds("ed_periodcurrent", 323 ohci_readl(®s->ed_periodcurrent)); 324 325 maybe_print_eds("ed_controlhead", ohci_readl(®s->ed_controlhead)); 326 maybe_print_eds("ed_controlcurrent", 327 ohci_readl(®s->ed_controlcurrent)); 328 329 maybe_print_eds("ed_bulkhead", ohci_readl(®s->ed_bulkhead)); 330 maybe_print_eds("ed_bulkcurrent", ohci_readl(®s->ed_bulkcurrent)); 331 332 maybe_print_eds("donehead", ohci_readl(®s->donehead)); 333 } 334 335 static void ohci_dump_roothub(ohci_t *controller, int verbose) 336 { 337 __u32 temp, ndp, i; 338 339 temp = roothub_a(controller); 340 ndp = (temp & RH_A_NDP); 341 #ifdef CONFIG_AT91C_PQFP_UHPBUG 342 ndp = (ndp == 2) ? 1:0; 343 #endif 344 if (verbose) { 345 dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, 346 ((temp & RH_A_POTPGT) >> 24) & 0xff, 347 (temp & RH_A_NOCP) ? " NOCP" : "", 348 (temp & RH_A_OCPM) ? " OCPM" : "", 349 (temp & RH_A_DT) ? " DT" : "", 350 (temp & RH_A_NPS) ? " NPS" : "", 351 (temp & RH_A_PSM) ? " PSM" : "", 352 ndp 353 ); 354 temp = roothub_b(controller); 355 dbg("roothub.b: %08x PPCM=%04x DR=%04x", 356 temp, 357 (temp & RH_B_PPCM) >> 16, 358 (temp & RH_B_DR) 359 ); 360 temp = roothub_status(controller); 361 dbg("roothub.status: %08x%s%s%s%s%s%s", 362 temp, 363 (temp & RH_HS_CRWE) ? " CRWE" : "", 364 (temp & RH_HS_OCIC) ? " OCIC" : "", 365 (temp & RH_HS_LPSC) ? " LPSC" : "", 366 (temp & RH_HS_DRWE) ? " DRWE" : "", 367 (temp & RH_HS_OCI) ? " OCI" : "", 368 (temp & RH_HS_LPS) ? " LPS" : "" 369 ); 370 } 371 372 for (i = 0; i < ndp; i++) { 373 temp = roothub_portstatus(controller, i); 374 dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", 375 i, 376 temp, 377 (temp & RH_PS_PRSC) ? " PRSC" : "", 378 (temp & RH_PS_OCIC) ? " OCIC" : "", 379 (temp & RH_PS_PSSC) ? " PSSC" : "", 380 (temp & RH_PS_PESC) ? " PESC" : "", 381 (temp & RH_PS_CSC) ? " CSC" : "", 382 383 (temp & RH_PS_LSDA) ? " LSDA" : "", 384 (temp & RH_PS_PPS) ? " PPS" : "", 385 (temp & RH_PS_PRS) ? " PRS" : "", 386 (temp & RH_PS_POCI) ? " POCI" : "", 387 (temp & RH_PS_PSS) ? " PSS" : "", 388 389 (temp & RH_PS_PES) ? " PES" : "", 390 (temp & RH_PS_CCS) ? " CCS" : "" 391 ); 392 } 393 } 394 395 static void ohci_dump(ohci_t *controller, int verbose) 396 { 397 dbg("OHCI controller usb-%s state", controller->slot_name); 398 399 /* dumps some of the state we know about */ 400 ohci_dump_status(controller); 401 if (verbose) 402 ep_print_int_eds(controller, "hcca"); 403 dbg("hcca frame #%04x", controller->hcca->frame_no); 404 ohci_dump_roothub(controller, 1); 405 } 406 #endif /* DEBUG */ 407 408 /*-------------------------------------------------------------------------* 409 * Interface functions (URB) 410 *-------------------------------------------------------------------------*/ 411 412 /* get a transfer request */ 413 414 int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup) 415 { 416 ohci_t *ohci; 417 ed_t *ed; 418 urb_priv_t *purb_priv = urb; 419 int i, size = 0; 420 struct usb_device *dev = urb->dev; 421 unsigned long pipe = urb->pipe; 422 void *buffer = urb->transfer_buffer; 423 int transfer_len = urb->transfer_buffer_length; 424 int interval = urb->interval; 425 426 ohci = &gohci; 427 428 /* when controller's hung, permit only roothub cleanup attempts 429 * such as powering down ports */ 430 if (ohci->disabled) { 431 err("sohci_submit_job: EPIPE"); 432 return -1; 433 } 434 435 /* we're about to begin a new transaction here so mark the 436 * URB unfinished */ 437 urb->finished = 0; 438 439 /* every endpoint has a ed, locate and fill it */ 440 ed = ep_add_ed(dev, pipe, interval, 1); 441 if (!ed) { 442 err("sohci_submit_job: ENOMEM"); 443 return -1; 444 } 445 446 /* for the private part of the URB we need the number of TDs (size) */ 447 switch (usb_pipetype(pipe)) { 448 case PIPE_BULK: /* one TD for every 4096 Byte */ 449 size = (transfer_len - 1) / 4096 + 1; 450 break; 451 case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ 452 size = (transfer_len == 0)? 2: 453 (transfer_len - 1) / 4096 + 3; 454 break; 455 case PIPE_INTERRUPT: /* 1 TD */ 456 size = 1; 457 break; 458 } 459 460 ed->purb = urb; 461 462 if (size >= (N_URB_TD - 1)) { 463 err("need %d TDs, only have %d", size, N_URB_TD); 464 return -1; 465 } 466 purb_priv->pipe = pipe; 467 468 /* fill the private part of the URB */ 469 purb_priv->length = size; 470 purb_priv->ed = ed; 471 purb_priv->actual_length = 0; 472 473 /* allocate the TDs */ 474 /* note that td[0] was allocated in ep_add_ed */ 475 for (i = 0; i < size; i++) { 476 purb_priv->td[i] = td_alloc(dev); 477 if (!purb_priv->td[i]) { 478 purb_priv->length = i; 479 urb_free_priv(purb_priv); 480 err("sohci_submit_job: ENOMEM"); 481 return -1; 482 } 483 } 484 485 if (ed->state == ED_NEW || (ed->state & ED_DEL)) { 486 urb_free_priv(purb_priv); 487 err("sohci_submit_job: EINVAL"); 488 return -1; 489 } 490 491 /* link the ed into a chain if is not already */ 492 if (ed->state != ED_OPER) 493 ep_link(ohci, ed); 494 495 /* fill the TDs and link it to the ed */ 496 td_submit_job(dev, pipe, buffer, transfer_len, 497 setup, purb_priv, interval); 498 499 return 0; 500 } 501 502 static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb) 503 { 504 struct ohci_regs *regs = hc->regs; 505 506 switch (usb_pipetype(urb->pipe)) { 507 case PIPE_INTERRUPT: 508 /* implicitly requeued */ 509 if (urb->dev->irq_handle && 510 (urb->dev->irq_act_len = urb->actual_length)) { 511 ohci_writel(OHCI_INTR_WDH, ®s->intrenable); 512 ohci_readl(®s->intrenable); /* PCI posting flush */ 513 urb->dev->irq_handle(urb->dev); 514 ohci_writel(OHCI_INTR_WDH, ®s->intrdisable); 515 ohci_readl(®s->intrdisable); /* PCI posting flush */ 516 } 517 urb->actual_length = 0; 518 td_submit_job( 519 urb->dev, 520 urb->pipe, 521 urb->transfer_buffer, 522 urb->transfer_buffer_length, 523 NULL, 524 urb, 525 urb->interval); 526 break; 527 case PIPE_CONTROL: 528 case PIPE_BULK: 529 break; 530 default: 531 return 0; 532 } 533 return 1; 534 } 535 536 /*-------------------------------------------------------------------------*/ 537 538 #ifdef DEBUG 539 /* tell us the current USB frame number */ 540 541 static int sohci_get_current_frame_number(struct usb_device *usb_dev) 542 { 543 ohci_t *ohci = &gohci; 544 545 return m16_swap(ohci->hcca->frame_no); 546 } 547 #endif 548 549 /*-------------------------------------------------------------------------* 550 * ED handling functions 551 *-------------------------------------------------------------------------*/ 552 553 /* search for the right branch to insert an interrupt ed into the int tree 554 * do some load ballancing; 555 * returns the branch and 556 * sets the interval to interval = 2^integer (ld (interval)) */ 557 558 static int ep_int_ballance(ohci_t *ohci, int interval, int load) 559 { 560 int i, branch = 0; 561 562 /* search for the least loaded interrupt endpoint 563 * branch of all 32 branches 564 */ 565 for (i = 0; i < 32; i++) 566 if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i]) 567 branch = i; 568 569 branch = branch % interval; 570 for (i = branch; i < 32; i += interval) 571 ohci->ohci_int_load [i] += load; 572 573 return branch; 574 } 575 576 /*-------------------------------------------------------------------------*/ 577 578 /* 2^int( ld (inter)) */ 579 580 static int ep_2_n_interval(int inter) 581 { 582 int i; 583 for (i = 0; ((inter >> i) > 1) && (i < 5); i++); 584 return 1 << i; 585 } 586 587 /*-------------------------------------------------------------------------*/ 588 589 /* the int tree is a binary tree 590 * in order to process it sequentially the indexes of the branches have to 591 * be mapped the mapping reverses the bits of a word of num_bits length */ 592 static int ep_rev(int num_bits, int word) 593 { 594 int i, wout = 0; 595 596 for (i = 0; i < num_bits; i++) 597 wout |= (((word >> i) & 1) << (num_bits - i - 1)); 598 return wout; 599 } 600 601 /*-------------------------------------------------------------------------* 602 * ED handling functions 603 *-------------------------------------------------------------------------*/ 604 605 /* link an ed into one of the HC chains */ 606 607 static int ep_link(ohci_t *ohci, ed_t *edi) 608 { 609 volatile ed_t *ed = edi; 610 int int_branch; 611 int i; 612 int inter; 613 int interval; 614 int load; 615 __u32 *ed_p; 616 617 ed->state = ED_OPER; 618 ed->int_interval = 0; 619 620 switch (ed->type) { 621 case PIPE_CONTROL: 622 ed->hwNextED = 0; 623 if (ohci->ed_controltail == NULL) 624 ohci_writel(ed, &ohci->regs->ed_controlhead); 625 else 626 ohci->ed_controltail->hwNextED = 627 m32_swap((unsigned long)ed); 628 629 ed->ed_prev = ohci->ed_controltail; 630 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && 631 !ohci->ed_rm_list[1] && !ohci->sleeping) { 632 ohci->hc_control |= OHCI_CTRL_CLE; 633 ohci_writel(ohci->hc_control, &ohci->regs->control); 634 } 635 ohci->ed_controltail = edi; 636 break; 637 638 case PIPE_BULK: 639 ed->hwNextED = 0; 640 if (ohci->ed_bulktail == NULL) 641 ohci_writel(ed, &ohci->regs->ed_bulkhead); 642 else 643 ohci->ed_bulktail->hwNextED = 644 m32_swap((unsigned long)ed); 645 646 ed->ed_prev = ohci->ed_bulktail; 647 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && 648 !ohci->ed_rm_list[1] && !ohci->sleeping) { 649 ohci->hc_control |= OHCI_CTRL_BLE; 650 ohci_writel(ohci->hc_control, &ohci->regs->control); 651 } 652 ohci->ed_bulktail = edi; 653 break; 654 655 case PIPE_INTERRUPT: 656 load = ed->int_load; 657 interval = ep_2_n_interval(ed->int_period); 658 ed->int_interval = interval; 659 int_branch = ep_int_ballance(ohci, interval, load); 660 ed->int_branch = int_branch; 661 662 for (i = 0; i < ep_rev(6, interval); i += inter) { 663 inter = 1; 664 for (ed_p = &(ohci->hcca->int_table[\ 665 ep_rev(5, i) + int_branch]); 666 (*ed_p != 0) && 667 (((ed_t *)ed_p)->int_interval >= interval); 668 ed_p = &(((ed_t *)ed_p)->hwNextED)) 669 inter = ep_rev(6, 670 ((ed_t *)ed_p)->int_interval); 671 ed->hwNextED = *ed_p; 672 *ed_p = m32_swap((unsigned long)ed); 673 } 674 break; 675 } 676 return 0; 677 } 678 679 /*-------------------------------------------------------------------------*/ 680 681 /* scan the periodic table to find and unlink this ED */ 682 static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed, 683 unsigned index, unsigned period) 684 { 685 for (; index < NUM_INTS; index += period) { 686 __u32 *ed_p = &ohci->hcca->int_table [index]; 687 688 /* ED might have been unlinked through another path */ 689 while (*ed_p != 0) { 690 if (((struct ed *) 691 m32_swap((unsigned long)ed_p)) == ed) { 692 *ed_p = ed->hwNextED; 693 break; 694 } 695 ed_p = &(((struct ed *) 696 m32_swap((unsigned long)ed_p))->hwNextED); 697 } 698 } 699 } 700 701 /* unlink an ed from one of the HC chains. 702 * just the link to the ed is unlinked. 703 * the link from the ed still points to another operational ed or 0 704 * so the HC can eventually finish the processing of the unlinked ed */ 705 706 static int ep_unlink(ohci_t *ohci, ed_t *edi) 707 { 708 volatile ed_t *ed = edi; 709 int i; 710 711 ed->hwINFO |= m32_swap(OHCI_ED_SKIP); 712 713 switch (ed->type) { 714 case PIPE_CONTROL: 715 if (ed->ed_prev == NULL) { 716 if (!ed->hwNextED) { 717 ohci->hc_control &= ~OHCI_CTRL_CLE; 718 ohci_writel(ohci->hc_control, 719 &ohci->regs->control); 720 } 721 ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)), 722 &ohci->regs->ed_controlhead); 723 } else { 724 ed->ed_prev->hwNextED = ed->hwNextED; 725 } 726 if (ohci->ed_controltail == ed) { 727 ohci->ed_controltail = ed->ed_prev; 728 } else { 729 ((ed_t *)m32_swap( 730 *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; 731 } 732 break; 733 734 case PIPE_BULK: 735 if (ed->ed_prev == NULL) { 736 if (!ed->hwNextED) { 737 ohci->hc_control &= ~OHCI_CTRL_BLE; 738 ohci_writel(ohci->hc_control, 739 &ohci->regs->control); 740 } 741 ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)), 742 &ohci->regs->ed_bulkhead); 743 } else { 744 ed->ed_prev->hwNextED = ed->hwNextED; 745 } 746 if (ohci->ed_bulktail == ed) { 747 ohci->ed_bulktail = ed->ed_prev; 748 } else { 749 ((ed_t *)m32_swap( 750 *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; 751 } 752 break; 753 754 case PIPE_INTERRUPT: 755 periodic_unlink(ohci, ed, 0, 1); 756 for (i = ed->int_branch; i < 32; i += ed->int_interval) 757 ohci->ohci_int_load[i] -= ed->int_load; 758 break; 759 } 760 ed->state = ED_UNLINK; 761 return 0; 762 } 763 764 /*-------------------------------------------------------------------------*/ 765 766 /* add/reinit an endpoint; this should be done once at the 767 * usb_set_configuration command, but the USB stack is a little bit 768 * stateless so we do it at every transaction if the state of the ed 769 * is ED_NEW then a dummy td is added and the state is changed to 770 * ED_UNLINK in all other cases the state is left unchanged the ed 771 * info fields are setted anyway even though most of them should not 772 * change 773 */ 774 static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe, 775 int interval, int load) 776 { 777 td_t *td; 778 ed_t *ed_ret; 779 volatile ed_t *ed; 780 781 ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint(pipe) << 1) | 782 (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))]; 783 784 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { 785 err("ep_add_ed: pending delete"); 786 /* pending delete request */ 787 return NULL; 788 } 789 790 if (ed->state == ED_NEW) { 791 /* dummy td; end of td list for ed */ 792 td = td_alloc(usb_dev); 793 ed->hwTailP = m32_swap((unsigned long)td); 794 ed->hwHeadP = ed->hwTailP; 795 ed->state = ED_UNLINK; 796 ed->type = usb_pipetype(pipe); 797 ohci_dev.ed_cnt++; 798 } 799 800 ed->hwINFO = m32_swap(usb_pipedevice(pipe) 801 | usb_pipeendpoint(pipe) << 7 802 | (usb_pipeisoc(pipe)? 0x8000: 0) 803 | (usb_pipecontrol(pipe)? 0: \ 804 (usb_pipeout(pipe)? 0x800: 0x1000)) 805 | (usb_dev->speed == USB_SPEED_LOW) << 13 806 | usb_maxpacket(usb_dev, pipe) << 16); 807 808 if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) { 809 ed->int_period = interval; 810 ed->int_load = load; 811 } 812 813 return ed_ret; 814 } 815 816 /*-------------------------------------------------------------------------* 817 * TD handling functions 818 *-------------------------------------------------------------------------*/ 819 820 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ 821 822 static void td_fill(ohci_t *ohci, unsigned int info, 823 void *data, int len, 824 struct usb_device *dev, int index, urb_priv_t *urb_priv) 825 { 826 volatile td_t *td, *td_pt; 827 #ifdef OHCI_FILL_TRACE 828 int i; 829 #endif 830 831 if (index > urb_priv->length) { 832 err("index > length"); 833 return; 834 } 835 /* use this td as the next dummy */ 836 td_pt = urb_priv->td [index]; 837 td_pt->hwNextTD = 0; 838 839 /* fill the old dummy TD */ 840 td = urb_priv->td [index] = 841 (td_t *)(m32_swap(urb_priv->ed->hwTailP) & ~0xf); 842 843 td->ed = urb_priv->ed; 844 td->next_dl_td = NULL; 845 td->index = index; 846 td->data = (__u32)data; 847 #ifdef OHCI_FILL_TRACE 848 if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) { 849 for (i = 0; i < len; i++) 850 printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]); 851 printf("\n"); 852 } 853 #endif 854 if (!len) 855 data = 0; 856 857 td->hwINFO = m32_swap(info); 858 td->hwCBP = m32_swap((unsigned long)data); 859 if (data) 860 td->hwBE = m32_swap((unsigned long)(data + len - 1)); 861 else 862 td->hwBE = 0; 863 864 td->hwNextTD = m32_swap((unsigned long)td_pt); 865 866 /* append to queue */ 867 td->ed->hwTailP = td->hwNextTD; 868 } 869 870 /*-------------------------------------------------------------------------*/ 871 872 /* prepare all TDs of a transfer */ 873 874 static void td_submit_job(struct usb_device *dev, unsigned long pipe, 875 void *buffer, int transfer_len, 876 struct devrequest *setup, urb_priv_t *urb, 877 int interval) 878 { 879 ohci_t *ohci = &gohci; 880 int data_len = transfer_len; 881 void *data; 882 int cnt = 0; 883 __u32 info = 0; 884 unsigned int toggle = 0; 885 886 /* OHCI handles the DATA-toggles itself, we just use the USB-toggle 887 * bits for reseting */ 888 if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { 889 toggle = TD_T_TOGGLE; 890 } else { 891 toggle = TD_T_DATA0; 892 usb_settoggle(dev, usb_pipeendpoint(pipe), 893 usb_pipeout(pipe), 1); 894 } 895 urb->td_cnt = 0; 896 if (data_len) 897 data = buffer; 898 else 899 data = 0; 900 901 switch (usb_pipetype(pipe)) { 902 case PIPE_BULK: 903 info = usb_pipeout(pipe)? 904 TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; 905 while (data_len > 4096) { 906 td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), 907 data, 4096, dev, cnt, urb); 908 data += 4096; data_len -= 4096; cnt++; 909 } 910 info = usb_pipeout(pipe)? 911 TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; 912 td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 913 data_len, dev, cnt, urb); 914 cnt++; 915 916 if (!ohci->sleeping) { 917 /* start bulk list */ 918 ohci_writel(OHCI_BLF, &ohci->regs->cmdstatus); 919 } 920 break; 921 922 case PIPE_CONTROL: 923 /* Setup phase */ 924 info = TD_CC | TD_DP_SETUP | TD_T_DATA0; 925 td_fill(ohci, info, setup, 8, dev, cnt++, urb); 926 927 /* Optional Data phase */ 928 if (data_len > 0) { 929 info = usb_pipeout(pipe)? 930 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : 931 TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; 932 /* NOTE: mishandles transfers >8K, some >4K */ 933 td_fill(ohci, info, data, data_len, dev, cnt++, urb); 934 } 935 936 /* Status phase */ 937 info = usb_pipeout(pipe)? 938 TD_CC | TD_DP_IN | TD_T_DATA1: 939 TD_CC | TD_DP_OUT | TD_T_DATA1; 940 td_fill(ohci, info, data, 0, dev, cnt++, urb); 941 942 if (!ohci->sleeping) { 943 /* start Control list */ 944 ohci_writel(OHCI_CLF, &ohci->regs->cmdstatus); 945 } 946 break; 947 948 case PIPE_INTERRUPT: 949 info = usb_pipeout(urb->pipe)? 950 TD_CC | TD_DP_OUT | toggle: 951 TD_CC | TD_R | TD_DP_IN | toggle; 952 td_fill(ohci, info, data, data_len, dev, cnt++, urb); 953 break; 954 } 955 if (urb->length != cnt) 956 dbg("TD LENGTH %d != CNT %d", urb->length, cnt); 957 } 958 959 /*-------------------------------------------------------------------------* 960 * Done List handling functions 961 *-------------------------------------------------------------------------*/ 962 963 /* calculate the transfer length and update the urb */ 964 965 static void dl_transfer_length(td_t *td) 966 { 967 __u32 tdBE, tdCBP; 968 urb_priv_t *lurb_priv = td->ed->purb; 969 970 tdBE = m32_swap(td->hwBE); 971 tdCBP = m32_swap(td->hwCBP); 972 973 if (!(usb_pipecontrol(lurb_priv->pipe) && 974 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { 975 if (tdBE != 0) { 976 if (td->hwCBP == 0) 977 lurb_priv->actual_length += tdBE - td->data + 1; 978 else 979 lurb_priv->actual_length += tdCBP - td->data; 980 } 981 } 982 } 983 984 /*-------------------------------------------------------------------------*/ 985 static void check_status(td_t *td_list) 986 { 987 urb_priv_t *lurb_priv = td_list->ed->purb; 988 int urb_len = lurb_priv->length; 989 __u32 *phwHeadP = &td_list->ed->hwHeadP; 990 int cc; 991 992 cc = TD_CC_GET(m32_swap(td_list->hwINFO)); 993 if (cc) { 994 err(" USB-error: %s (%x)", cc_to_string[cc], cc); 995 996 if (*phwHeadP & m32_swap(0x1)) { 997 if (lurb_priv && 998 ((td_list->index + 1) < urb_len)) { 999 *phwHeadP = 1000 (lurb_priv->td[urb_len - 1]->hwNextTD &\ 1001 m32_swap(0xfffffff0)) | 1002 (*phwHeadP & m32_swap(0x2)); 1003 1004 lurb_priv->td_cnt += urb_len - 1005 td_list->index - 1; 1006 } else 1007 *phwHeadP &= m32_swap(0xfffffff2); 1008 } 1009 #ifdef CONFIG_MPC5200 1010 td_list->hwNextTD = 0; 1011 #endif 1012 } 1013 } 1014 1015 /* replies to the request have to be on a FIFO basis so 1016 * we reverse the reversed done-list */ 1017 static td_t *dl_reverse_done_list(ohci_t *ohci) 1018 { 1019 __u32 td_list_hc; 1020 td_t *td_rev = NULL; 1021 td_t *td_list = NULL; 1022 1023 td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0; 1024 ohci->hcca->done_head = 0; 1025 1026 while (td_list_hc) { 1027 td_list = (td_t *)td_list_hc; 1028 check_status(td_list); 1029 td_list->next_dl_td = td_rev; 1030 td_rev = td_list; 1031 td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0; 1032 } 1033 return td_list; 1034 } 1035 1036 /*-------------------------------------------------------------------------*/ 1037 /*-------------------------------------------------------------------------*/ 1038 1039 static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status) 1040 { 1041 if ((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL)) 1042 urb->finished = sohci_return_job(ohci, urb); 1043 else 1044 dbg("finish_urb: strange.., ED state %x, \n", status); 1045 } 1046 1047 /* 1048 * Used to take back a TD from the host controller. This would normally be 1049 * called from within dl_done_list, however it may be called directly if the 1050 * HC no longer sees the TD and it has not appeared on the donelist (after 1051 * two frames). This bug has been observed on ZF Micro systems. 1052 */ 1053 static int takeback_td(ohci_t *ohci, td_t *td_list) 1054 { 1055 ed_t *ed; 1056 int cc; 1057 int stat = 0; 1058 /* urb_t *urb; */ 1059 urb_priv_t *lurb_priv; 1060 __u32 tdINFO, edHeadP, edTailP; 1061 1062 tdINFO = m32_swap(td_list->hwINFO); 1063 1064 ed = td_list->ed; 1065 lurb_priv = ed->purb; 1066 1067 dl_transfer_length(td_list); 1068 1069 lurb_priv->td_cnt++; 1070 1071 /* error code of transfer */ 1072 cc = TD_CC_GET(tdINFO); 1073 if (cc) { 1074 err("USB-error: %s (%x)", cc_to_string[cc], cc); 1075 stat = cc_to_error[cc]; 1076 } 1077 1078 /* see if this done list makes for all TD's of current URB, 1079 * and mark the URB finished if so */ 1080 if (lurb_priv->td_cnt == lurb_priv->length) 1081 finish_urb(ohci, lurb_priv, ed->state); 1082 1083 dbg("dl_done_list: processing TD %x, len %x\n", 1084 lurb_priv->td_cnt, lurb_priv->length); 1085 1086 if (ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) { 1087 edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0; 1088 edTailP = m32_swap(ed->hwTailP); 1089 1090 /* unlink eds if they are not busy */ 1091 if ((edHeadP == edTailP) && (ed->state == ED_OPER)) 1092 ep_unlink(ohci, ed); 1093 } 1094 return stat; 1095 } 1096 1097 static int dl_done_list(ohci_t *ohci) 1098 { 1099 int stat = 0; 1100 td_t *td_list = dl_reverse_done_list(ohci); 1101 1102 while (td_list) { 1103 td_t *td_next = td_list->next_dl_td; 1104 stat = takeback_td(ohci, td_list); 1105 td_list = td_next; 1106 } 1107 return stat; 1108 } 1109 1110 /*-------------------------------------------------------------------------* 1111 * Virtual Root Hub 1112 *-------------------------------------------------------------------------*/ 1113 1114 /* Device descriptor */ 1115 static __u8 root_hub_dev_des[] = 1116 { 1117 0x12, /* __u8 bLength; */ 1118 0x01, /* __u8 bDescriptorType; Device */ 1119 0x10, /* __u16 bcdUSB; v1.1 */ 1120 0x01, 1121 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ 1122 0x00, /* __u8 bDeviceSubClass; */ 1123 0x00, /* __u8 bDeviceProtocol; */ 1124 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ 1125 0x00, /* __u16 idVendor; */ 1126 0x00, 1127 0x00, /* __u16 idProduct; */ 1128 0x00, 1129 0x00, /* __u16 bcdDevice; */ 1130 0x00, 1131 0x00, /* __u8 iManufacturer; */ 1132 0x01, /* __u8 iProduct; */ 1133 0x00, /* __u8 iSerialNumber; */ 1134 0x01 /* __u8 bNumConfigurations; */ 1135 }; 1136 1137 /* Configuration descriptor */ 1138 static __u8 root_hub_config_des[] = 1139 { 1140 0x09, /* __u8 bLength; */ 1141 0x02, /* __u8 bDescriptorType; Configuration */ 1142 0x19, /* __u16 wTotalLength; */ 1143 0x00, 1144 0x01, /* __u8 bNumInterfaces; */ 1145 0x01, /* __u8 bConfigurationValue; */ 1146 0x00, /* __u8 iConfiguration; */ 1147 0x40, /* __u8 bmAttributes; 1148 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ 1149 0x00, /* __u8 MaxPower; */ 1150 1151 /* interface */ 1152 0x09, /* __u8 if_bLength; */ 1153 0x04, /* __u8 if_bDescriptorType; Interface */ 1154 0x00, /* __u8 if_bInterfaceNumber; */ 1155 0x00, /* __u8 if_bAlternateSetting; */ 1156 0x01, /* __u8 if_bNumEndpoints; */ 1157 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ 1158 0x00, /* __u8 if_bInterfaceSubClass; */ 1159 0x00, /* __u8 if_bInterfaceProtocol; */ 1160 0x00, /* __u8 if_iInterface; */ 1161 1162 /* endpoint */ 1163 0x07, /* __u8 ep_bLength; */ 1164 0x05, /* __u8 ep_bDescriptorType; Endpoint */ 1165 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ 1166 0x03, /* __u8 ep_bmAttributes; Interrupt */ 1167 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ 1168 0x00, 1169 0xff /* __u8 ep_bInterval; 255 ms */ 1170 }; 1171 1172 static unsigned char root_hub_str_index0[] = 1173 { 1174 0x04, /* __u8 bLength; */ 1175 0x03, /* __u8 bDescriptorType; String-descriptor */ 1176 0x09, /* __u8 lang ID */ 1177 0x04, /* __u8 lang ID */ 1178 }; 1179 1180 static unsigned char root_hub_str_index1[] = 1181 { 1182 28, /* __u8 bLength; */ 1183 0x03, /* __u8 bDescriptorType; String-descriptor */ 1184 'O', /* __u8 Unicode */ 1185 0, /* __u8 Unicode */ 1186 'H', /* __u8 Unicode */ 1187 0, /* __u8 Unicode */ 1188 'C', /* __u8 Unicode */ 1189 0, /* __u8 Unicode */ 1190 'I', /* __u8 Unicode */ 1191 0, /* __u8 Unicode */ 1192 ' ', /* __u8 Unicode */ 1193 0, /* __u8 Unicode */ 1194 'R', /* __u8 Unicode */ 1195 0, /* __u8 Unicode */ 1196 'o', /* __u8 Unicode */ 1197 0, /* __u8 Unicode */ 1198 'o', /* __u8 Unicode */ 1199 0, /* __u8 Unicode */ 1200 't', /* __u8 Unicode */ 1201 0, /* __u8 Unicode */ 1202 ' ', /* __u8 Unicode */ 1203 0, /* __u8 Unicode */ 1204 'H', /* __u8 Unicode */ 1205 0, /* __u8 Unicode */ 1206 'u', /* __u8 Unicode */ 1207 0, /* __u8 Unicode */ 1208 'b', /* __u8 Unicode */ 1209 0, /* __u8 Unicode */ 1210 }; 1211 1212 /* Hub class-specific descriptor is constructed dynamically */ 1213 1214 /*-------------------------------------------------------------------------*/ 1215 1216 #define OK(x) len = (x); break 1217 #ifdef DEBUG 1218 #define WR_RH_STAT(x) {info("WR:status %#8x", (x)); ohci_writel((x), \ 1219 &gohci.regs->roothub.status); } 1220 #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, \ 1221 (x)); ohci_writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); } 1222 #else 1223 #define WR_RH_STAT(x) ohci_writel((x), &gohci.regs->roothub.status) 1224 #define WR_RH_PORTSTAT(x) ohci_writel((x), \ 1225 &gohci.regs->roothub.portstatus[wIndex-1]) 1226 #endif 1227 #define RD_RH_STAT roothub_status(&gohci) 1228 #define RD_RH_PORTSTAT roothub_portstatus(&gohci, wIndex-1) 1229 1230 /* request to virtual root hub */ 1231 1232 int rh_check_port_status(ohci_t *controller) 1233 { 1234 __u32 temp, ndp, i; 1235 int res; 1236 1237 res = -1; 1238 temp = roothub_a(controller); 1239 ndp = (temp & RH_A_NDP); 1240 #ifdef CONFIG_AT91C_PQFP_UHPBUG 1241 ndp = (ndp == 2) ? 1:0; 1242 #endif 1243 for (i = 0; i < ndp; i++) { 1244 temp = roothub_portstatus(controller, i); 1245 /* check for a device disconnect */ 1246 if (((temp & (RH_PS_PESC | RH_PS_CSC)) == 1247 (RH_PS_PESC | RH_PS_CSC)) && 1248 ((temp & RH_PS_CCS) == 0)) { 1249 res = i; 1250 break; 1251 } 1252 } 1253 return res; 1254 } 1255 1256 static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, 1257 void *buffer, int transfer_len, struct devrequest *cmd) 1258 { 1259 void *data = buffer; 1260 int leni = transfer_len; 1261 int len = 0; 1262 int stat = 0; 1263 __u16 bmRType_bReq; 1264 __u16 wValue; 1265 __u16 wIndex; 1266 __u16 wLength; 1267 ALLOC_ALIGN_BUFFER(__u8, databuf, 16, sizeof(u32)); 1268 1269 #ifdef DEBUG 1270 pkt_print(NULL, dev, pipe, buffer, transfer_len, 1271 cmd, "SUB(rh)", usb_pipein(pipe)); 1272 #else 1273 mdelay(1); 1274 #endif 1275 if (usb_pipeint(pipe)) { 1276 info("Root-Hub submit IRQ: NOT implemented"); 1277 return 0; 1278 } 1279 1280 bmRType_bReq = cmd->requesttype | (cmd->request << 8); 1281 wValue = le16_to_cpu(cmd->value); 1282 wIndex = le16_to_cpu(cmd->index); 1283 wLength = le16_to_cpu(cmd->length); 1284 1285 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", 1286 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); 1287 1288 switch (bmRType_bReq) { 1289 /* Request Destination: 1290 without flags: Device, 1291 RH_INTERFACE: interface, 1292 RH_ENDPOINT: endpoint, 1293 RH_CLASS means HUB here, 1294 RH_OTHER | RH_CLASS almost ever means HUB_PORT here 1295 */ 1296 1297 case RH_GET_STATUS: 1298 *(u16 *)databuf = cpu_to_le16(1); 1299 OK(2); 1300 case RH_GET_STATUS | RH_INTERFACE: 1301 *(u16 *)databuf = cpu_to_le16(0); 1302 OK(2); 1303 case RH_GET_STATUS | RH_ENDPOINT: 1304 *(u16 *)databuf = cpu_to_le16(0); 1305 OK(2); 1306 case RH_GET_STATUS | RH_CLASS: 1307 *(u32 *)databuf = cpu_to_le32( 1308 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); 1309 OK(4); 1310 case RH_GET_STATUS | RH_OTHER | RH_CLASS: 1311 *(u32 *)databuf = cpu_to_le32(RD_RH_PORTSTAT); 1312 OK(4); 1313 1314 case RH_CLEAR_FEATURE | RH_ENDPOINT: 1315 switch (wValue) { 1316 case (RH_ENDPOINT_STALL): 1317 OK(0); 1318 } 1319 break; 1320 1321 case RH_CLEAR_FEATURE | RH_CLASS: 1322 switch (wValue) { 1323 case RH_C_HUB_LOCAL_POWER: 1324 OK(0); 1325 case (RH_C_HUB_OVER_CURRENT): 1326 WR_RH_STAT(RH_HS_OCIC); 1327 OK(0); 1328 } 1329 break; 1330 1331 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: 1332 switch (wValue) { 1333 case (RH_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_CCS); OK(0); 1334 case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_POCI); OK(0); 1335 case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_LSDA); OK(0); 1336 case (RH_C_PORT_CONNECTION): WR_RH_PORTSTAT(RH_PS_CSC); OK(0); 1337 case (RH_C_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_PESC); OK(0); 1338 case (RH_C_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSSC); OK(0); 1339 case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0); 1340 case (RH_C_PORT_RESET): WR_RH_PORTSTAT(RH_PS_PRSC); OK(0); 1341 } 1342 break; 1343 1344 case RH_SET_FEATURE | RH_OTHER | RH_CLASS: 1345 switch (wValue) { 1346 case (RH_PORT_SUSPEND): 1347 WR_RH_PORTSTAT(RH_PS_PSS); OK(0); 1348 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ 1349 if (RD_RH_PORTSTAT & RH_PS_CCS) 1350 WR_RH_PORTSTAT(RH_PS_PRS); 1351 OK(0); 1352 case (RH_PORT_POWER): 1353 WR_RH_PORTSTAT(RH_PS_PPS); 1354 mdelay(100); 1355 OK(0); 1356 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ 1357 if (RD_RH_PORTSTAT & RH_PS_CCS) 1358 WR_RH_PORTSTAT(RH_PS_PES); 1359 OK(0); 1360 } 1361 break; 1362 1363 case RH_SET_ADDRESS: 1364 gohci.rh.devnum = wValue; 1365 OK(0); 1366 1367 case RH_GET_DESCRIPTOR: 1368 switch ((wValue & 0xff00) >> 8) { 1369 case (0x01): /* device descriptor */ 1370 len = min_t(unsigned int, 1371 leni, 1372 min_t(unsigned int, 1373 sizeof(root_hub_dev_des), 1374 wLength)); 1375 databuf = root_hub_dev_des; OK(len); 1376 case (0x02): /* configuration descriptor */ 1377 len = min_t(unsigned int, 1378 leni, 1379 min_t(unsigned int, 1380 sizeof(root_hub_config_des), 1381 wLength)); 1382 databuf = root_hub_config_des; OK(len); 1383 case (0x03): /* string descriptors */ 1384 if (wValue == 0x0300) { 1385 len = min_t(unsigned int, 1386 leni, 1387 min_t(unsigned int, 1388 sizeof(root_hub_str_index0), 1389 wLength)); 1390 databuf = root_hub_str_index0; 1391 OK(len); 1392 } 1393 if (wValue == 0x0301) { 1394 len = min_t(unsigned int, 1395 leni, 1396 min_t(unsigned int, 1397 sizeof(root_hub_str_index1), 1398 wLength)); 1399 databuf = root_hub_str_index1; 1400 OK(len); 1401 } 1402 default: 1403 stat = USB_ST_STALLED; 1404 } 1405 break; 1406 1407 case RH_GET_DESCRIPTOR | RH_CLASS: 1408 { 1409 __u32 temp = roothub_a(&gohci); 1410 1411 databuf[0] = 9; /* min length; */ 1412 databuf[1] = 0x29; 1413 databuf[2] = temp & RH_A_NDP; 1414 #ifdef CONFIG_AT91C_PQFP_UHPBUG 1415 databuf[2] = (databuf[2] == 2) ? 1 : 0; 1416 #endif 1417 databuf[3] = 0; 1418 if (temp & RH_A_PSM) /* per-port power switching? */ 1419 databuf[3] |= 0x1; 1420 if (temp & RH_A_NOCP) /* no overcurrent reporting? */ 1421 databuf[3] |= 0x10; 1422 else if (temp & RH_A_OCPM)/* per-port overcurrent reporting? */ 1423 databuf[3] |= 0x8; 1424 1425 databuf[4] = 0; 1426 databuf[5] = (temp & RH_A_POTPGT) >> 24; 1427 databuf[6] = 0; 1428 temp = roothub_b(&gohci); 1429 databuf[7] = temp & RH_B_DR; 1430 if (databuf[2] < 7) { 1431 databuf[8] = 0xff; 1432 } else { 1433 databuf[0] += 2; 1434 databuf[8] = (temp & RH_B_DR) >> 8; 1435 databuf[10] = databuf[9] = 0xff; 1436 } 1437 1438 len = min_t(unsigned int, leni, 1439 min_t(unsigned int, databuf[0], wLength)); 1440 OK(len); 1441 } 1442 1443 case RH_GET_CONFIGURATION: 1444 databuf[0] = 0x01; 1445 OK(1); 1446 1447 case RH_SET_CONFIGURATION: 1448 WR_RH_STAT(0x10000); 1449 OK(0); 1450 1451 default: 1452 dbg("unsupported root hub command"); 1453 stat = USB_ST_STALLED; 1454 } 1455 1456 #ifdef DEBUG 1457 ohci_dump_roothub(&gohci, 1); 1458 #else 1459 mdelay(1); 1460 #endif 1461 1462 len = min_t(int, len, leni); 1463 if (data != databuf) 1464 memcpy(data, databuf, len); 1465 dev->act_len = len; 1466 dev->status = stat; 1467 1468 #ifdef DEBUG 1469 pkt_print(NULL, dev, pipe, buffer, 1470 transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); 1471 #else 1472 mdelay(1); 1473 #endif 1474 1475 return stat; 1476 } 1477 1478 /*-------------------------------------------------------------------------*/ 1479 1480 /* common code for handling submit messages - used for all but root hub */ 1481 /* accesses. */ 1482 int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1483 int transfer_len, struct devrequest *setup, int interval) 1484 { 1485 int stat = 0; 1486 int maxsize = usb_maxpacket(dev, pipe); 1487 int timeout; 1488 urb_priv_t *urb; 1489 1490 urb = malloc(sizeof(urb_priv_t)); 1491 memset(urb, 0, sizeof(urb_priv_t)); 1492 1493 urb->dev = dev; 1494 urb->pipe = pipe; 1495 urb->transfer_buffer = buffer; 1496 urb->transfer_buffer_length = transfer_len; 1497 urb->interval = interval; 1498 1499 /* device pulled? Shortcut the action. */ 1500 if (devgone == dev) { 1501 dev->status = USB_ST_CRC_ERR; 1502 return 0; 1503 } 1504 1505 #ifdef DEBUG 1506 urb->actual_length = 0; 1507 pkt_print(urb, dev, pipe, buffer, transfer_len, 1508 setup, "SUB", usb_pipein(pipe)); 1509 #else 1510 mdelay(1); 1511 #endif 1512 if (!maxsize) { 1513 err("submit_common_message: pipesize for pipe %lx is zero", 1514 pipe); 1515 return -1; 1516 } 1517 1518 if (sohci_submit_job(urb, setup) < 0) { 1519 err("sohci_submit_job failed"); 1520 return -1; 1521 } 1522 1523 #if 0 1524 mdelay(10); 1525 /* ohci_dump_status(&gohci); */ 1526 #endif 1527 1528 timeout = USB_TIMEOUT_MS(pipe); 1529 1530 /* wait for it to complete */ 1531 for (;;) { 1532 /* check whether the controller is done */ 1533 stat = hc_interrupt(); 1534 if (stat < 0) { 1535 stat = USB_ST_CRC_ERR; 1536 break; 1537 } 1538 1539 /* NOTE: since we are not interrupt driven in U-Boot and always 1540 * handle only one URB at a time, we cannot assume the 1541 * transaction finished on the first successful return from 1542 * hc_interrupt().. unless the flag for current URB is set, 1543 * meaning that all TD's to/from device got actually 1544 * transferred and processed. If the current URB is not 1545 * finished we need to re-iterate this loop so as 1546 * hc_interrupt() gets called again as there needs to be some 1547 * more TD's to process still */ 1548 if ((stat >= 0) && (stat != 0xff) && (urb->finished)) { 1549 /* 0xff is returned for an SF-interrupt */ 1550 break; 1551 } 1552 1553 if (--timeout) { 1554 mdelay(1); 1555 if (!urb->finished) 1556 dbg("*"); 1557 1558 } else { 1559 err("CTL:TIMEOUT "); 1560 dbg("submit_common_msg: TO status %x\n", stat); 1561 urb->finished = 1; 1562 stat = USB_ST_CRC_ERR; 1563 break; 1564 } 1565 } 1566 1567 dev->status = stat; 1568 dev->act_len = transfer_len; 1569 1570 #ifdef DEBUG 1571 pkt_print(urb, dev, pipe, buffer, transfer_len, 1572 setup, "RET(ctlr)", usb_pipein(pipe)); 1573 #else 1574 mdelay(1); 1575 #endif 1576 1577 /* free TDs in urb_priv */ 1578 if (!usb_pipeint(pipe)) 1579 urb_free_priv(urb); 1580 return 0; 1581 } 1582 1583 /* submit routines called from usb.c */ 1584 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1585 int transfer_len) 1586 { 1587 info("submit_bulk_msg"); 1588 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); 1589 } 1590 1591 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1592 int transfer_len, struct devrequest *setup) 1593 { 1594 int maxsize = usb_maxpacket(dev, pipe); 1595 1596 info("submit_control_msg"); 1597 #ifdef DEBUG 1598 pkt_print(NULL, dev, pipe, buffer, transfer_len, 1599 setup, "SUB", usb_pipein(pipe)); 1600 #else 1601 mdelay(1); 1602 #endif 1603 if (!maxsize) { 1604 err("submit_control_message: pipesize for pipe %lx is zero", 1605 pipe); 1606 return -1; 1607 } 1608 if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { 1609 gohci.rh.dev = dev; 1610 /* root hub - redirect */ 1611 return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, 1612 setup); 1613 } 1614 1615 return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); 1616 } 1617 1618 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 1619 int transfer_len, int interval) 1620 { 1621 info("submit_int_msg"); 1622 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 1623 interval); 1624 } 1625 1626 /*-------------------------------------------------------------------------* 1627 * HC functions 1628 *-------------------------------------------------------------------------*/ 1629 1630 /* reset the HC and BUS */ 1631 1632 static int hc_reset(ohci_t *ohci) 1633 { 1634 #ifdef CONFIG_PCI_EHCI_DEVNO 1635 pci_dev_t pdev; 1636 #endif 1637 int timeout = 30; 1638 int smm_timeout = 50; /* 0,5 sec */ 1639 1640 dbg("%s\n", __FUNCTION__); 1641 1642 #ifdef CONFIG_PCI_EHCI_DEVNO 1643 /* 1644 * Some multi-function controllers (e.g. ISP1562) allow root hub 1645 * resetting via EHCI registers only. 1646 */ 1647 pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO); 1648 if (pdev != -1) { 1649 u32 base; 1650 int timeout = 1000; 1651 1652 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); 1653 base += EHCI_USBCMD_OFF; 1654 ohci_writel(ohci_readl(base) | EHCI_USBCMD_HCRESET, base); 1655 1656 while (ohci_readl(base) & EHCI_USBCMD_HCRESET) { 1657 if (timeout-- <= 0) { 1658 printf("USB RootHub reset timed out!"); 1659 break; 1660 } 1661 udelay(1); 1662 } 1663 } else 1664 printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO); 1665 #endif 1666 if (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { 1667 /* SMM owns the HC, request ownership */ 1668 ohci_writel(OHCI_OCR, &ohci->regs->cmdstatus); 1669 info("USB HC TakeOver from SMM"); 1670 while (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { 1671 mdelay(10); 1672 if (--smm_timeout == 0) { 1673 err("USB HC TakeOver failed!"); 1674 return -1; 1675 } 1676 } 1677 } 1678 1679 /* Disable HC interrupts */ 1680 ohci_writel(OHCI_INTR_MIE, &ohci->regs->intrdisable); 1681 1682 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n", 1683 ohci->slot_name, 1684 ohci_readl(&ohci->regs->control)); 1685 1686 /* Reset USB (needed by some controllers) */ 1687 ohci->hc_control = 0; 1688 ohci_writel(ohci->hc_control, &ohci->regs->control); 1689 1690 /* HC Reset requires max 10 us delay */ 1691 ohci_writel(OHCI_HCR, &ohci->regs->cmdstatus); 1692 while ((ohci_readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { 1693 if (--timeout == 0) { 1694 err("USB HC reset timed out!"); 1695 return -1; 1696 } 1697 udelay(1); 1698 } 1699 return 0; 1700 } 1701 1702 /*-------------------------------------------------------------------------*/ 1703 1704 /* Start an OHCI controller, set the BUS operational 1705 * enable interrupts 1706 * connect the virtual root hub */ 1707 1708 static int hc_start(ohci_t *ohci) 1709 { 1710 __u32 mask; 1711 unsigned int fminterval; 1712 1713 ohci->disabled = 1; 1714 1715 /* Tell the controller where the control and bulk lists are 1716 * The lists are empty now. */ 1717 1718 ohci_writel(0, &ohci->regs->ed_controlhead); 1719 ohci_writel(0, &ohci->regs->ed_bulkhead); 1720 1721 ohci_writel((__u32)ohci->hcca, 1722 &ohci->regs->hcca); /* reset clears this */ 1723 1724 fminterval = 0x2edf; 1725 ohci_writel((fminterval * 9) / 10, &ohci->regs->periodicstart); 1726 fminterval |= ((((fminterval - 210) * 6) / 7) << 16); 1727 ohci_writel(fminterval, &ohci->regs->fminterval); 1728 ohci_writel(0x628, &ohci->regs->lsthresh); 1729 1730 /* start controller operations */ 1731 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; 1732 ohci->disabled = 0; 1733 ohci_writel(ohci->hc_control, &ohci->regs->control); 1734 1735 /* disable all interrupts */ 1736 mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | 1737 OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | 1738 OHCI_INTR_OC | OHCI_INTR_MIE); 1739 ohci_writel(mask, &ohci->regs->intrdisable); 1740 /* clear all interrupts */ 1741 mask &= ~OHCI_INTR_MIE; 1742 ohci_writel(mask, &ohci->regs->intrstatus); 1743 /* Choose the interrupts we care about now - but w/o MIE */ 1744 mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; 1745 ohci_writel(mask, &ohci->regs->intrenable); 1746 1747 #ifdef OHCI_USE_NPS 1748 /* required for AMD-756 and some Mac platforms */ 1749 ohci_writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM, 1750 &ohci->regs->roothub.a); 1751 ohci_writel(RH_HS_LPSC, &ohci->regs->roothub.status); 1752 #endif /* OHCI_USE_NPS */ 1753 1754 /* POTPGT delay is bits 24-31, in 2 ms units. */ 1755 mdelay((roothub_a(ohci) >> 23) & 0x1fe); 1756 1757 /* connect the virtual root hub */ 1758 ohci->rh.devnum = 0; 1759 1760 return 0; 1761 } 1762 1763 /*-------------------------------------------------------------------------*/ 1764 1765 /* an interrupt happens */ 1766 1767 static int hc_interrupt(void) 1768 { 1769 ohci_t *ohci = &gohci; 1770 struct ohci_regs *regs = ohci->regs; 1771 int ints; 1772 int stat = -1; 1773 1774 if ((ohci->hcca->done_head != 0) && 1775 !(m32_swap(ohci->hcca->done_head) & 0x01)) { 1776 ints = OHCI_INTR_WDH; 1777 } else { 1778 ints = ohci_readl(®s->intrstatus); 1779 if (ints == ~(u32)0) { 1780 ohci->disabled++; 1781 err("%s device removed!", ohci->slot_name); 1782 return -1; 1783 } else { 1784 ints &= ohci_readl(®s->intrenable); 1785 if (ints == 0) { 1786 dbg("hc_interrupt: returning..\n"); 1787 return 0xff; 1788 } 1789 } 1790 } 1791 1792 /* dbg("Interrupt: %x frame: %x", ints, 1793 le16_to_cpu(ohci->hcca->frame_no)); */ 1794 1795 if (ints & OHCI_INTR_RHSC) 1796 stat = 0xff; 1797 1798 if (ints & OHCI_INTR_UE) { 1799 ohci->disabled++; 1800 err("OHCI Unrecoverable Error, controller usb-%s disabled", 1801 ohci->slot_name); 1802 /* e.g. due to PCI Master/Target Abort */ 1803 1804 #ifdef DEBUG 1805 ohci_dump(ohci, 1); 1806 #else 1807 mdelay(1); 1808 #endif 1809 /* FIXME: be optimistic, hope that bug won't repeat often. */ 1810 /* Make some non-interrupt context restart the controller. */ 1811 /* Count and limit the retries though; either hardware or */ 1812 /* software errors can go forever... */ 1813 hc_reset(ohci); 1814 return -1; 1815 } 1816 1817 if (ints & OHCI_INTR_WDH) { 1818 mdelay(1); 1819 ohci_writel(OHCI_INTR_WDH, ®s->intrdisable); 1820 (void)ohci_readl(®s->intrdisable); /* flush */ 1821 stat = dl_done_list(&gohci); 1822 ohci_writel(OHCI_INTR_WDH, ®s->intrenable); 1823 (void)ohci_readl(®s->intrdisable); /* flush */ 1824 } 1825 1826 if (ints & OHCI_INTR_SO) { 1827 dbg("USB Schedule overrun\n"); 1828 ohci_writel(OHCI_INTR_SO, ®s->intrenable); 1829 stat = -1; 1830 } 1831 1832 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ 1833 if (ints & OHCI_INTR_SF) { 1834 unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1; 1835 mdelay(1); 1836 ohci_writel(OHCI_INTR_SF, ®s->intrdisable); 1837 if (ohci->ed_rm_list[frame] != NULL) 1838 ohci_writel(OHCI_INTR_SF, ®s->intrenable); 1839 stat = 0xff; 1840 } 1841 1842 ohci_writel(ints, ®s->intrstatus); 1843 return stat; 1844 } 1845 1846 /*-------------------------------------------------------------------------*/ 1847 1848 /*-------------------------------------------------------------------------*/ 1849 1850 /* De-allocate all resources.. */ 1851 1852 static void hc_release_ohci(ohci_t *ohci) 1853 { 1854 dbg("USB HC release ohci usb-%s", ohci->slot_name); 1855 1856 if (!ohci->disabled) 1857 hc_reset(ohci); 1858 } 1859 1860 /*-------------------------------------------------------------------------*/ 1861 1862 /* 1863 * low level initalisation routine, called from usb.c 1864 */ 1865 static char ohci_inited = 0; 1866 1867 int usb_lowlevel_init(int index, void **controller) 1868 { 1869 #ifdef CONFIG_PCI_OHCI 1870 pci_dev_t pdev; 1871 #endif 1872 1873 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT 1874 /* cpu dependant init */ 1875 if (usb_cpu_init()) 1876 return -1; 1877 #endif 1878 1879 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT 1880 /* board dependant init */ 1881 if (usb_board_init()) 1882 return -1; 1883 #endif 1884 memset(&gohci, 0, sizeof(ohci_t)); 1885 1886 /* align the storage */ 1887 if ((__u32)&ghcca[0] & 0xff) { 1888 err("HCCA not aligned!!"); 1889 return -1; 1890 } 1891 phcca = &ghcca[0]; 1892 info("aligned ghcca %p", phcca); 1893 memset(&ohci_dev, 0, sizeof(struct ohci_device)); 1894 if ((__u32)&ohci_dev.ed[0] & 0x7) { 1895 err("EDs not aligned!!"); 1896 return -1; 1897 } 1898 memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); 1899 if ((__u32)gtd & 0x7) { 1900 err("TDs not aligned!!"); 1901 return -1; 1902 } 1903 ptd = gtd; 1904 gohci.hcca = phcca; 1905 memset(phcca, 0, sizeof(struct ohci_hcca)); 1906 1907 gohci.disabled = 1; 1908 gohci.sleeping = 0; 1909 gohci.irq = -1; 1910 #ifdef CONFIG_PCI_OHCI 1911 pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO); 1912 1913 if (pdev != -1) { 1914 u16 vid, did; 1915 u32 base; 1916 pci_read_config_word(pdev, PCI_VENDOR_ID, &vid); 1917 pci_read_config_word(pdev, PCI_DEVICE_ID, &did); 1918 printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n", 1919 vid, did, (pdev >> 16) & 0xff, 1920 (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); 1921 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base); 1922 printf("OHCI regs address 0x%08x\n", base); 1923 gohci.regs = (struct ohci_regs *)base; 1924 } else 1925 return -1; 1926 #else 1927 gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE; 1928 #endif 1929 1930 gohci.flags = 0; 1931 gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME; 1932 1933 if (hc_reset (&gohci) < 0) { 1934 hc_release_ohci (&gohci); 1935 err ("can't reset usb-%s", gohci.slot_name); 1936 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT 1937 /* board dependant cleanup */ 1938 usb_board_init_fail(); 1939 #endif 1940 1941 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT 1942 /* cpu dependant cleanup */ 1943 usb_cpu_init_fail(); 1944 #endif 1945 return -1; 1946 } 1947 1948 if (hc_start(&gohci) < 0) { 1949 err("can't start usb-%s", gohci.slot_name); 1950 hc_release_ohci(&gohci); 1951 /* Initialization failed */ 1952 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT 1953 /* board dependant cleanup */ 1954 usb_board_stop(); 1955 #endif 1956 1957 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT 1958 /* cpu dependant cleanup */ 1959 usb_cpu_stop(); 1960 #endif 1961 return -1; 1962 } 1963 1964 #ifdef DEBUG 1965 ohci_dump(&gohci, 1); 1966 #else 1967 mdelay(1); 1968 #endif 1969 ohci_inited = 1; 1970 return 0; 1971 } 1972 1973 int usb_lowlevel_stop(int index) 1974 { 1975 /* this gets called really early - before the controller has */ 1976 /* even been initialized! */ 1977 if (!ohci_inited) 1978 return 0; 1979 /* TODO release any interrupts, etc. */ 1980 /* call hc_release_ohci() here ? */ 1981 hc_reset(&gohci); 1982 1983 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT 1984 /* board dependant cleanup */ 1985 if (usb_board_stop()) 1986 return -1; 1987 #endif 1988 1989 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT 1990 /* cpu dependant cleanup */ 1991 if (usb_cpu_stop()) 1992 return -1; 1993 #endif 1994 /* This driver is no longer initialised. It needs a new low-level 1995 * init (board/cpu) before it can be used again. */ 1996 ohci_inited = 0; 1997 return 0; 1998 } 1999