1 /*- 2 * Copyright (c) 2007-2008, Juniper Networks, Inc. 3 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it> 4 * All rights reserved. 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #ifndef USB_EHCI_H 10 #define USB_EHCI_H 11 12 #include <usb.h> 13 14 #if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) 15 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 16 #endif 17 18 /* 19 * Register Space. 20 */ 21 struct ehci_hccr { 22 uint32_t cr_capbase; 23 #define HC_LENGTH(p) (((p) >> 0) & 0x00ff) 24 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 25 uint32_t cr_hcsparams; 26 #define HCS_PPC(p) ((p) & (1 << 4)) 27 #define HCS_INDICATOR(p) ((p) & (1 << 16)) /* Port indicators */ 28 #define HCS_N_PORTS(p) (((p) >> 0) & 0xf) 29 uint32_t cr_hccparams; 30 uint8_t cr_hcsp_portrt[8]; 31 } __attribute__ ((packed, aligned(4))); 32 33 struct ehci_hcor { 34 uint32_t or_usbcmd; 35 #define CMD_PARK (1 << 11) /* enable "park" */ 36 #define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */ 37 #define CMD_LRESET (1 << 7) /* partial reset */ 38 #define CMD_IAAD (1 << 6) /* "doorbell" interrupt */ 39 #define CMD_ASE (1 << 5) /* async schedule enable */ 40 #define CMD_PSE (1 << 4) /* periodic schedule enable */ 41 #define CMD_RESET (1 << 1) /* reset HC not bus */ 42 #define CMD_RUN (1 << 0) /* start/stop HC */ 43 uint32_t or_usbsts; 44 #define STS_ASS (1 << 15) 45 #define STS_PSS (1 << 14) 46 #define STS_HALT (1 << 12) 47 uint32_t or_usbintr; 48 #define INTR_UE (1 << 0) /* USB interrupt enable */ 49 #define INTR_UEE (1 << 1) /* USB error interrupt enable */ 50 #define INTR_PCE (1 << 2) /* Port change detect enable */ 51 #define INTR_SEE (1 << 4) /* system error enable */ 52 #define INTR_AAE (1 << 5) /* Interrupt on async adavance enable */ 53 uint32_t or_frindex; 54 uint32_t or_ctrldssegment; 55 uint32_t or_periodiclistbase; 56 uint32_t or_asynclistaddr; 57 uint32_t _reserved_0_; 58 uint32_t or_burstsize; 59 uint32_t or_txfilltuning; 60 #define TXFIFO_THRESH_MASK (0x3f << 16) 61 #define TXFIFO_THRESH(p) ((p & 0x3f) << 16) 62 uint32_t _reserved_1_[6]; 63 uint32_t or_configflag; 64 #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */ 65 uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS]; 66 #define PORTSC_PSPD(x) (((x) >> 26) & 0x3) 67 #define PORTSC_PSPD_FS 0x0 68 #define PORTSC_PSPD_LS 0x1 69 #define PORTSC_PSPD_HS 0x2 70 uint32_t or_systune; 71 } __attribute__ ((packed, aligned(4))); 72 73 #define USBMODE 0x68 /* USB Device mode */ 74 #define USBMODE_SDIS (1 << 3) /* Stream disable */ 75 #define USBMODE_BE (1 << 2) /* BE/LE endiannes select */ 76 #define USBMODE_CM_HC (3 << 0) /* host controller mode */ 77 #define USBMODE_CM_IDLE (0 << 0) /* idle state */ 78 79 /* Interface descriptor */ 80 struct usb_linux_interface_descriptor { 81 unsigned char bLength; 82 unsigned char bDescriptorType; 83 unsigned char bInterfaceNumber; 84 unsigned char bAlternateSetting; 85 unsigned char bNumEndpoints; 86 unsigned char bInterfaceClass; 87 unsigned char bInterfaceSubClass; 88 unsigned char bInterfaceProtocol; 89 unsigned char iInterface; 90 } __attribute__ ((packed)); 91 92 /* Configuration descriptor information.. */ 93 struct usb_linux_config_descriptor { 94 unsigned char bLength; 95 unsigned char bDescriptorType; 96 unsigned short wTotalLength; 97 unsigned char bNumInterfaces; 98 unsigned char bConfigurationValue; 99 unsigned char iConfiguration; 100 unsigned char bmAttributes; 101 unsigned char MaxPower; 102 } __attribute__ ((packed)); 103 104 #if defined CONFIG_EHCI_DESC_BIG_ENDIAN 105 #define ehci_readl(x) cpu_to_be32((*((volatile u32 *)(x)))) 106 #define ehci_writel(a, b) (*((volatile u32 *)(a)) = \ 107 cpu_to_be32(((volatile u32)b))) 108 #else 109 #define ehci_readl(x) cpu_to_le32((*((volatile u32 *)(x)))) 110 #define ehci_writel(a, b) (*((volatile u32 *)(a)) = \ 111 cpu_to_le32(((volatile u32)b))) 112 #endif 113 114 #if defined CONFIG_EHCI_MMIO_BIG_ENDIAN 115 #define hc32_to_cpu(x) be32_to_cpu((x)) 116 #define cpu_to_hc32(x) cpu_to_be32((x)) 117 #else 118 #define hc32_to_cpu(x) le32_to_cpu((x)) 119 #define cpu_to_hc32(x) cpu_to_le32((x)) 120 #endif 121 122 #define EHCI_PS_WKOC_E (1 << 22) /* RW wake on over current */ 123 #define EHCI_PS_WKDSCNNT_E (1 << 21) /* RW wake on disconnect */ 124 #define EHCI_PS_WKCNNT_E (1 << 20) /* RW wake on connect */ 125 #define EHCI_PS_PO (1 << 13) /* RW port owner */ 126 #define EHCI_PS_PP (1 << 12) /* RW,RO port power */ 127 #define EHCI_PS_LS (3 << 10) /* RO line status */ 128 #define EHCI_PS_PR (1 << 8) /* RW port reset */ 129 #define EHCI_PS_SUSP (1 << 7) /* RW suspend */ 130 #define EHCI_PS_FPR (1 << 6) /* RW force port resume */ 131 #define EHCI_PS_OCC (1 << 5) /* RWC over current change */ 132 #define EHCI_PS_OCA (1 << 4) /* RO over current active */ 133 #define EHCI_PS_PEC (1 << 3) /* RWC port enable change */ 134 #define EHCI_PS_PE (1 << 2) /* RW port enable */ 135 #define EHCI_PS_CSC (1 << 1) /* RWC connect status change */ 136 #define EHCI_PS_CS (1 << 0) /* RO connect status */ 137 #define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC) 138 139 #define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == (1 << 10)) 140 141 /* 142 * Schedule Interface Space. 143 * 144 * IMPORTANT: Software must ensure that no interface data structure 145 * reachable by the EHCI host controller spans a 4K page boundary! 146 * 147 * Periodic transfers (i.e. isochronous and interrupt transfers) are 148 * not supported. 149 */ 150 151 /* Queue Element Transfer Descriptor (qTD). */ 152 struct qTD { 153 /* this part defined by EHCI spec */ 154 uint32_t qt_next; /* see EHCI 3.5.1 */ 155 #define QT_NEXT_TERMINATE 1 156 uint32_t qt_altnext; /* see EHCI 3.5.2 */ 157 uint32_t qt_token; /* see EHCI 3.5.3 */ 158 #define QT_TOKEN_DT(x) (((x) & 0x1) << 31) /* Data Toggle */ 159 #define QT_TOKEN_GET_DT(x) (((x) >> 31) & 0x1) 160 #define QT_TOKEN_TOTALBYTES(x) (((x) & 0x7fff) << 16) /* Total Bytes to Transfer */ 161 #define QT_TOKEN_GET_TOTALBYTES(x) (((x) >> 16) & 0x7fff) 162 #define QT_TOKEN_IOC(x) (((x) & 0x1) << 15) /* Interrupt On Complete */ 163 #define QT_TOKEN_CPAGE(x) (((x) & 0x7) << 12) /* Current Page */ 164 #define QT_TOKEN_CERR(x) (((x) & 0x3) << 10) /* Error Counter */ 165 #define QT_TOKEN_PID(x) (((x) & 0x3) << 8) /* PID Code */ 166 #define QT_TOKEN_PID_OUT 0x0 167 #define QT_TOKEN_PID_IN 0x1 168 #define QT_TOKEN_PID_SETUP 0x2 169 #define QT_TOKEN_STATUS(x) (((x) & 0xff) << 0) /* Status */ 170 #define QT_TOKEN_GET_STATUS(x) (((x) >> 0) & 0xff) 171 #define QT_TOKEN_STATUS_ACTIVE 0x80 172 #define QT_TOKEN_STATUS_HALTED 0x40 173 #define QT_TOKEN_STATUS_DATBUFERR 0x20 174 #define QT_TOKEN_STATUS_BABBLEDET 0x10 175 #define QT_TOKEN_STATUS_XACTERR 0x08 176 #define QT_TOKEN_STATUS_MISSEDUFRAME 0x04 177 #define QT_TOKEN_STATUS_SPLITXSTATE 0x02 178 #define QT_TOKEN_STATUS_PERR 0x01 179 #define QT_BUFFER_CNT 5 180 uint32_t qt_buffer[QT_BUFFER_CNT]; /* see EHCI 3.5.4 */ 181 uint32_t qt_buffer_hi[QT_BUFFER_CNT]; /* Appendix B */ 182 /* pad struct for 32 byte alignment */ 183 uint32_t unused[3]; 184 }; 185 186 #define EHCI_PAGE_SIZE 4096 187 188 /* Queue Head (QH). */ 189 struct QH { 190 uint32_t qh_link; 191 #define QH_LINK_TERMINATE 1 192 #define QH_LINK_TYPE_ITD 0 193 #define QH_LINK_TYPE_QH 2 194 #define QH_LINK_TYPE_SITD 4 195 #define QH_LINK_TYPE_FSTN 6 196 uint32_t qh_endpt1; 197 #define QH_ENDPT1_RL(x) (((x) & 0xf) << 28) /* NAK Count Reload */ 198 #define QH_ENDPT1_C(x) (((x) & 0x1) << 27) /* Control Endpoint Flag */ 199 #define QH_ENDPT1_MAXPKTLEN(x) (((x) & 0x7ff) << 16) /* Maximum Packet Length */ 200 #define QH_ENDPT1_H(x) (((x) & 0x1) << 15) /* Head of Reclamation List Flag */ 201 #define QH_ENDPT1_DTC(x) (((x) & 0x1) << 14) /* Data Toggle Control */ 202 #define QH_ENDPT1_DTC_IGNORE_QTD_TD 0x0 203 #define QH_ENDPT1_DTC_DT_FROM_QTD 0x1 204 #define QH_ENDPT1_EPS(x) (((x) & 0x3) << 12) /* Endpoint Speed */ 205 #define QH_ENDPT1_EPS_FS 0x0 206 #define QH_ENDPT1_EPS_LS 0x1 207 #define QH_ENDPT1_EPS_HS 0x2 208 #define QH_ENDPT1_ENDPT(x) (((x) & 0xf) << 8) /* Endpoint Number */ 209 #define QH_ENDPT1_I(x) (((x) & 0x1) << 7) /* Inactivate on Next Transaction */ 210 #define QH_ENDPT1_DEVADDR(x) (((x) & 0x7f) << 0) /* Device Address */ 211 uint32_t qh_endpt2; 212 #define QH_ENDPT2_MULT(x) (((x) & 0x3) << 30) /* High-Bandwidth Pipe Multiplier */ 213 #define QH_ENDPT2_PORTNUM(x) (((x) & 0x7f) << 23) /* Port Number */ 214 #define QH_ENDPT2_HUBADDR(x) (((x) & 0x7f) << 16) /* Hub Address */ 215 #define QH_ENDPT2_UFCMASK(x) (((x) & 0xff) << 8) /* Split Completion Mask */ 216 #define QH_ENDPT2_UFSMASK(x) (((x) & 0xff) << 0) /* Interrupt Schedule Mask */ 217 uint32_t qh_curtd; 218 struct qTD qh_overlay; 219 /* 220 * Add dummy fill value to make the size of this struct 221 * aligned to 32 bytes 222 */ 223 union { 224 uint32_t fill[4]; 225 void *buffer; 226 }; 227 }; 228 229 /* Tweak flags for EHCI, used to control operation */ 230 enum { 231 /* don't use or_configflag in init */ 232 EHCI_TWEAK_NO_INIT_CF = 1 << 0, 233 }; 234 235 struct ehci_ctrl; 236 237 struct ehci_ops { 238 void (*set_usb_mode)(struct ehci_ctrl *ctrl); 239 int (*get_port_speed)(struct ehci_ctrl *ctrl, uint32_t reg); 240 void (*powerup_fixup)(struct ehci_ctrl *ctrl, uint32_t *status_reg, 241 uint32_t *reg); 242 uint32_t *(*get_portsc_register)(struct ehci_ctrl *ctrl, int port); 243 int (*init_after_reset)(struct ehci_ctrl *ctrl); 244 }; 245 246 struct ehci_ctrl { 247 enum usb_init_type init; 248 struct ehci_hccr *hccr; /* R/O registers, not need for volatile */ 249 struct ehci_hcor *hcor; 250 int rootdev; 251 uint16_t portreset; 252 struct QH qh_list __aligned(USB_DMA_MINALIGN); 253 struct QH periodic_queue __aligned(USB_DMA_MINALIGN); 254 uint32_t *periodic_list; 255 int periodic_schedules; 256 int ntds; 257 struct ehci_ops ops; 258 void *priv; /* client's private data */ 259 }; 260 261 /** 262 * ehci_set_controller_info() - Set up private data for the controller 263 * 264 * This function can be called in ehci_hcd_init() to tell the EHCI layer 265 * about the controller's private data pointer. Then in the above functions 266 * this can be accessed given the struct ehci_ctrl pointer. Also special 267 * EHCI operation methods can be provided if required 268 * 269 * @index: Controller number to set 270 * @priv: Controller pointer 271 * @ops: Controller operations, or NULL to use default 272 */ 273 void ehci_set_controller_priv(int index, void *priv, 274 const struct ehci_ops *ops); 275 276 /** 277 * ehci_get_controller_priv() - Get controller private data 278 * 279 * @index Controller number to get 280 * @return controller pointer for this index 281 */ 282 void *ehci_get_controller_priv(int index); 283 284 /* Low level init functions */ 285 int ehci_hcd_init(int index, enum usb_init_type init, 286 struct ehci_hccr **hccr, struct ehci_hcor **hcor); 287 int ehci_hcd_stop(int index); 288 289 int ehci_register(struct udevice *dev, struct ehci_hccr *hccr, 290 struct ehci_hcor *hcor, const struct ehci_ops *ops, 291 uint tweaks, enum usb_init_type init); 292 int ehci_deregister(struct udevice *dev); 293 extern struct dm_usb_ops ehci_usb_ops; 294 295 #endif /* USB_EHCI_H */ 296