1 /*- 2 * Copyright (c) 2007-2008, Juniper Networks, Inc. 3 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it> 4 * All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2 of 9 * the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #ifndef USB_EHCI_H 23 #define USB_EHCI_H 24 25 #if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) 26 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 27 #endif 28 29 /* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */ 30 #define DeviceRequest \ 31 ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8) 32 33 #define DeviceOutRequest \ 34 ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8) 35 36 #define InterfaceRequest \ 37 ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8) 38 39 #define EndpointRequest \ 40 ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8) 41 42 #define EndpointOutRequest \ 43 ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8) 44 45 /* 46 * Register Space. 47 */ 48 struct ehci_hccr { 49 uint32_t cr_capbase; 50 #define HC_LENGTH(p) (((p) >> 0) & 0x00ff) 51 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 52 uint32_t cr_hcsparams; 53 #define HCS_PPC(p) ((p) & (1 << 4)) 54 #define HCS_INDICATOR(p) ((p) & (1 << 16)) /* Port indicators */ 55 #define HCS_N_PORTS(p) (((p) >> 0) & 0xf) 56 uint32_t cr_hccparams; 57 uint8_t cr_hcsp_portrt[8]; 58 } __attribute__ ((packed, aligned(4))); 59 60 struct ehci_hcor { 61 uint32_t or_usbcmd; 62 #define CMD_PARK (1 << 11) /* enable "park" */ 63 #define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */ 64 #define CMD_ASE (1 << 5) /* async schedule enable */ 65 #define CMD_LRESET (1 << 7) /* partial reset */ 66 #define CMD_IAAD (1 << 5) /* "doorbell" interrupt */ 67 #define CMD_PSE (1 << 4) /* periodic schedule enable */ 68 #define CMD_RESET (1 << 1) /* reset HC not bus */ 69 #define CMD_RUN (1 << 0) /* start/stop HC */ 70 uint32_t or_usbsts; 71 #define STS_ASS (1 << 15) 72 #define STS_HALT (1 << 12) 73 uint32_t or_usbintr; 74 #define INTR_UE (1 << 0) /* USB interrupt enable */ 75 #define INTR_UEE (1 << 1) /* USB error interrupt enable */ 76 #define INTR_PCE (1 << 2) /* Port change detect enable */ 77 #define INTR_SEE (1 << 4) /* system error enable */ 78 #define INTR_AAE (1 << 5) /* Interrupt on async adavance enable */ 79 uint32_t or_frindex; 80 uint32_t or_ctrldssegment; 81 uint32_t or_periodiclistbase; 82 uint32_t or_asynclistaddr; 83 uint32_t _reserved_0_; 84 uint32_t or_burstsize; 85 uint32_t or_txfilltuning; 86 #define TXFIFO_THRESH_MASK (0x3f << 16) 87 #define TXFIFO_THRESH(p) ((p & 0x3f) << 16) 88 uint32_t _reserved_1_[6]; 89 uint32_t or_configflag; 90 #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */ 91 uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS]; 92 #define PORTSC_PSPD(x) (((x) >> 26) & 0x3) 93 #define PORTSC_PSPD_FS 0x0 94 #define PORTSC_PSPD_LS 0x1 95 #define PORTSC_PSPD_HS 0x2 96 uint32_t or_systune; 97 } __attribute__ ((packed, aligned(4))); 98 99 #define USBMODE 0x68 /* USB Device mode */ 100 #define USBMODE_SDIS (1 << 3) /* Stream disable */ 101 #define USBMODE_BE (1 << 2) /* BE/LE endiannes select */ 102 #define USBMODE_CM_HC (3 << 0) /* host controller mode */ 103 #define USBMODE_CM_IDLE (0 << 0) /* idle state */ 104 105 /* Interface descriptor */ 106 struct usb_linux_interface_descriptor { 107 unsigned char bLength; 108 unsigned char bDescriptorType; 109 unsigned char bInterfaceNumber; 110 unsigned char bAlternateSetting; 111 unsigned char bNumEndpoints; 112 unsigned char bInterfaceClass; 113 unsigned char bInterfaceSubClass; 114 unsigned char bInterfaceProtocol; 115 unsigned char iInterface; 116 } __attribute__ ((packed)); 117 118 /* Configuration descriptor information.. */ 119 struct usb_linux_config_descriptor { 120 unsigned char bLength; 121 unsigned char bDescriptorType; 122 unsigned short wTotalLength; 123 unsigned char bNumInterfaces; 124 unsigned char bConfigurationValue; 125 unsigned char iConfiguration; 126 unsigned char bmAttributes; 127 unsigned char MaxPower; 128 } __attribute__ ((packed)); 129 130 #if defined CONFIG_EHCI_DESC_BIG_ENDIAN 131 #define ehci_readl(x) (*((volatile u32 *)(x))) 132 #define ehci_writel(a, b) (*((volatile u32 *)(a)) = ((volatile u32)b)) 133 #else 134 #define ehci_readl(x) cpu_to_le32((*((volatile u32 *)(x)))) 135 #define ehci_writel(a, b) (*((volatile u32 *)(a)) = \ 136 cpu_to_le32(((volatile u32)b))) 137 #endif 138 139 #if defined CONFIG_EHCI_MMIO_BIG_ENDIAN 140 #define hc32_to_cpu(x) be32_to_cpu((x)) 141 #define cpu_to_hc32(x) cpu_to_be32((x)) 142 #else 143 #define hc32_to_cpu(x) le32_to_cpu((x)) 144 #define cpu_to_hc32(x) cpu_to_le32((x)) 145 #endif 146 147 #define EHCI_PS_WKOC_E (1 << 22) /* RW wake on over current */ 148 #define EHCI_PS_WKDSCNNT_E (1 << 21) /* RW wake on disconnect */ 149 #define EHCI_PS_WKCNNT_E (1 << 20) /* RW wake on connect */ 150 #define EHCI_PS_PO (1 << 13) /* RW port owner */ 151 #define EHCI_PS_PP (1 << 12) /* RW,RO port power */ 152 #define EHCI_PS_LS (3 << 10) /* RO line status */ 153 #define EHCI_PS_PR (1 << 8) /* RW port reset */ 154 #define EHCI_PS_SUSP (1 << 7) /* RW suspend */ 155 #define EHCI_PS_FPR (1 << 6) /* RW force port resume */ 156 #define EHCI_PS_OCC (1 << 5) /* RWC over current change */ 157 #define EHCI_PS_OCA (1 << 4) /* RO over current active */ 158 #define EHCI_PS_PEC (1 << 3) /* RWC port enable change */ 159 #define EHCI_PS_PE (1 << 2) /* RW port enable */ 160 #define EHCI_PS_CSC (1 << 1) /* RWC connect status change */ 161 #define EHCI_PS_CS (1 << 0) /* RO connect status */ 162 #define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC) 163 164 #define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == (1 << 10)) 165 166 /* 167 * Schedule Interface Space. 168 * 169 * IMPORTANT: Software must ensure that no interface data structure 170 * reachable by the EHCI host controller spans a 4K page boundary! 171 * 172 * Periodic transfers (i.e. isochronous and interrupt transfers) are 173 * not supported. 174 */ 175 176 /* Queue Element Transfer Descriptor (qTD). */ 177 struct qTD { 178 /* this part defined by EHCI spec */ 179 uint32_t qt_next; /* see EHCI 3.5.1 */ 180 #define QT_NEXT_TERMINATE 1 181 uint32_t qt_altnext; /* see EHCI 3.5.2 */ 182 uint32_t qt_token; /* see EHCI 3.5.3 */ 183 #define QT_TOKEN_DT(x) (((x) & 0x1) << 31) /* Data Toggle */ 184 #define QT_TOKEN_GET_DT(x) (((x) >> 31) & 0x1) 185 #define QT_TOKEN_TOTALBYTES(x) (((x) & 0x7fff) << 16) /* Total Bytes to Transfer */ 186 #define QT_TOKEN_GET_TOTALBYTES(x) (((x) >> 16) & 0x7fff) 187 #define QT_TOKEN_IOC(x) (((x) & 0x1) << 15) /* Interrupt On Complete */ 188 #define QT_TOKEN_CPAGE(x) (((x) & 0x7) << 12) /* Current Page */ 189 #define QT_TOKEN_CERR(x) (((x) & 0x3) << 10) /* Error Counter */ 190 #define QT_TOKEN_PID(x) (((x) & 0x3) << 8) /* PID Code */ 191 #define QT_TOKEN_PID_OUT 0x0 192 #define QT_TOKEN_PID_IN 0x1 193 #define QT_TOKEN_PID_SETUP 0x2 194 #define QT_TOKEN_STATUS(x) (((x) & 0xff) << 0) /* Status */ 195 #define QT_TOKEN_GET_STATUS(x) (((x) >> 0) & 0xff) 196 #define QT_TOKEN_STATUS_ACTIVE 0x80 197 #define QT_TOKEN_STATUS_HALTED 0x40 198 #define QT_TOKEN_STATUS_DATBUFERR 0x20 199 #define QT_TOKEN_STATUS_BABBLEDET 0x10 200 #define QT_TOKEN_STATUS_XACTERR 0x08 201 #define QT_TOKEN_STATUS_MISSEDUFRAME 0x04 202 #define QT_TOKEN_STATUS_SPLITXSTATE 0x02 203 #define QT_TOKEN_STATUS_PERR 0x01 204 #define QT_BUFFER_CNT 5 205 uint32_t qt_buffer[QT_BUFFER_CNT]; /* see EHCI 3.5.4 */ 206 uint32_t qt_buffer_hi[QT_BUFFER_CNT]; /* Appendix B */ 207 /* pad struct for 32 byte alignment */ 208 uint32_t unused[3]; 209 }; 210 211 #define EHCI_PAGE_SIZE 4096 212 213 /* Queue Head (QH). */ 214 struct QH { 215 uint32_t qh_link; 216 #define QH_LINK_TERMINATE 1 217 #define QH_LINK_TYPE_ITD 0 218 #define QH_LINK_TYPE_QH 2 219 #define QH_LINK_TYPE_SITD 4 220 #define QH_LINK_TYPE_FSTN 6 221 uint32_t qh_endpt1; 222 #define QH_ENDPT1_RL(x) (((x) & 0xf) << 28) /* NAK Count Reload */ 223 #define QH_ENDPT1_C(x) (((x) & 0x1) << 27) /* Control Endpoint Flag */ 224 #define QH_ENDPT1_MAXPKTLEN(x) (((x) & 0x7ff) << 16) /* Maximum Packet Length */ 225 #define QH_ENDPT1_H(x) (((x) & 0x1) << 15) /* Head of Reclamation List Flag */ 226 #define QH_ENDPT1_DTC(x) (((x) & 0x1) << 14) /* Data Toggle Control */ 227 #define QH_ENDPT1_DTC_IGNORE_QTD_TD 0x0 228 #define QH_ENDPT1_DTC_DT_FROM_QTD 0x1 229 #define QH_ENDPT1_EPS(x) (((x) & 0x3) << 12) /* Endpoint Speed */ 230 #define QH_ENDPT1_EPS_FS 0x0 231 #define QH_ENDPT1_EPS_LS 0x1 232 #define QH_ENDPT1_EPS_HS 0x2 233 #define QH_ENDPT1_ENDPT(x) (((x) & 0xf) << 8) /* Endpoint Number */ 234 #define QH_ENDPT1_I(x) (((x) & 0x1) << 7) /* Inactivate on Next Transaction */ 235 #define QH_ENDPT1_DEVADDR(x) (((x) & 0x7f) << 0) /* Device Address */ 236 uint32_t qh_endpt2; 237 #define QH_ENDPT2_MULT(x) (((x) & 0x3) << 30) /* High-Bandwidth Pipe Multiplier */ 238 #define QH_ENDPT2_PORTNUM(x) (((x) & 0x7f) << 23) /* Port Number */ 239 #define QH_ENDPT2_HUBADDR(x) (((x) & 0x7f) << 16) /* Hub Address */ 240 #define QH_ENDPT2_UFCMASK(x) (((x) & 0xff) << 8) /* Split Completion Mask */ 241 #define QH_ENDPT2_UFSMASK(x) (((x) & 0xff) << 0) /* Interrupt Schedule Mask */ 242 uint32_t qh_curtd; 243 struct qTD qh_overlay; 244 /* 245 * Add dummy fill value to make the size of this struct 246 * aligned to 32 bytes 247 */ 248 uint8_t fill[16]; 249 }; 250 251 /* Low level init functions */ 252 int ehci_hcd_init(void); 253 int ehci_hcd_stop(void); 254 255 #endif /* USB_EHCI_H */ 256