1 /*- 2 * Copyright (c) 2007-2008, Juniper Networks, Inc. 3 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it> 4 * All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2 of 9 * the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #ifndef USB_EHCI_H 23 #define USB_EHCI_H 24 25 #if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) 26 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 27 #endif 28 29 /* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */ 30 #define DeviceRequest \ 31 ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8) 32 33 #define DeviceOutRequest \ 34 ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8) 35 36 #define InterfaceRequest \ 37 ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8) 38 39 #define EndpointRequest \ 40 ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8) 41 42 #define EndpointOutRequest \ 43 ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8) 44 45 /* 46 * Register Space. 47 */ 48 struct ehci_hccr { 49 uint32_t cr_capbase; 50 #define HC_LENGTH(p) (((p) >> 0) & 0x00ff) 51 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 52 uint32_t cr_hcsparams; 53 #define HCS_PPC(p) ((p) & (1 << 4)) 54 #define HCS_INDICATOR(p) ((p) & (1 << 16)) /* Port indicators */ 55 #define HCS_N_PORTS(p) (((p) >> 0) & 0xf) 56 uint32_t cr_hccparams; 57 uint8_t cr_hcsp_portrt[8]; 58 } __attribute__ ((packed, aligned(4))); 59 60 struct ehci_hcor { 61 uint32_t or_usbcmd; 62 #define CMD_PARK (1 << 11) /* enable "park" */ 63 #define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */ 64 #define CMD_ASE (1 << 5) /* async schedule enable */ 65 #define CMD_LRESET (1 << 7) /* partial reset */ 66 #define CMD_IAAD (1 << 5) /* "doorbell" interrupt */ 67 #define CMD_PSE (1 << 4) /* periodic schedule enable */ 68 #define CMD_RESET (1 << 1) /* reset HC not bus */ 69 #define CMD_RUN (1 << 0) /* start/stop HC */ 70 uint32_t or_usbsts; 71 #define STD_ASS (1 << 15) 72 #define STS_HALT (1 << 12) 73 uint32_t or_usbintr; 74 #define INTR_UE (1 << 0) /* USB interrupt enable */ 75 #define INTR_UEE (1 << 1) /* USB error interrupt enable */ 76 #define INTR_PCE (1 << 2) /* Port change detect enable */ 77 #define INTR_SEE (1 << 4) /* system error enable */ 78 #define INTR_AAE (1 << 5) /* Interrupt on async adavance enable */ 79 uint32_t or_frindex; 80 uint32_t or_ctrldssegment; 81 uint32_t or_periodiclistbase; 82 uint32_t or_asynclistaddr; 83 uint32_t _reserved_[9]; 84 uint32_t or_configflag; 85 #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */ 86 uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS]; 87 uint32_t or_systune; 88 } __attribute__ ((packed, aligned(4))); 89 90 #define USBMODE 0x68 /* USB Device mode */ 91 #define USBMODE_SDIS (1 << 3) /* Stream disable */ 92 #define USBMODE_BE (1 << 2) /* BE/LE endiannes select */ 93 #define USBMODE_CM_HC (3 << 0) /* host controller mode */ 94 #define USBMODE_CM_IDLE (0 << 0) /* idle state */ 95 96 /* Interface descriptor */ 97 struct usb_linux_interface_descriptor { 98 unsigned char bLength; 99 unsigned char bDescriptorType; 100 unsigned char bInterfaceNumber; 101 unsigned char bAlternateSetting; 102 unsigned char bNumEndpoints; 103 unsigned char bInterfaceClass; 104 unsigned char bInterfaceSubClass; 105 unsigned char bInterfaceProtocol; 106 unsigned char iInterface; 107 } __attribute__ ((packed)); 108 109 /* Configuration descriptor information.. */ 110 struct usb_linux_config_descriptor { 111 unsigned char bLength; 112 unsigned char bDescriptorType; 113 unsigned short wTotalLength; 114 unsigned char bNumInterfaces; 115 unsigned char bConfigurationValue; 116 unsigned char iConfiguration; 117 unsigned char bmAttributes; 118 unsigned char MaxPower; 119 } __attribute__ ((packed)); 120 121 #if defined CONFIG_EHCI_DESC_BIG_ENDIAN 122 #define ehci_readl(x) (*((volatile u32 *)(x))) 123 #define ehci_writel(a, b) (*((volatile u32 *)(a)) = ((volatile u32)b)) 124 #else 125 #define ehci_readl(x) cpu_to_le32((*((volatile u32 *)(x)))) 126 #define ehci_writel(a, b) (*((volatile u32 *)(a)) = \ 127 cpu_to_le32(((volatile u32)b))) 128 #endif 129 130 #if defined CONFIG_EHCI_MMIO_BIG_ENDIAN 131 #define hc32_to_cpu(x) be32_to_cpu((x)) 132 #define cpu_to_hc32(x) cpu_to_be32((x)) 133 #else 134 #define hc32_to_cpu(x) le32_to_cpu((x)) 135 #define cpu_to_hc32(x) cpu_to_le32((x)) 136 #endif 137 138 #define EHCI_PS_WKOC_E (1 << 22) /* RW wake on over current */ 139 #define EHCI_PS_WKDSCNNT_E (1 << 21) /* RW wake on disconnect */ 140 #define EHCI_PS_WKCNNT_E (1 << 20) /* RW wake on connect */ 141 #define EHCI_PS_PO (1 << 13) /* RW port owner */ 142 #define EHCI_PS_PP (1 << 12) /* RW,RO port power */ 143 #define EHCI_PS_LS (3 << 10) /* RO line status */ 144 #define EHCI_PS_PR (1 << 8) /* RW port reset */ 145 #define EHCI_PS_SUSP (1 << 7) /* RW suspend */ 146 #define EHCI_PS_FPR (1 << 6) /* RW force port resume */ 147 #define EHCI_PS_OCC (1 << 5) /* RWC over current change */ 148 #define EHCI_PS_OCA (1 << 4) /* RO over current active */ 149 #define EHCI_PS_PEC (1 << 3) /* RWC port enable change */ 150 #define EHCI_PS_PE (1 << 2) /* RW port enable */ 151 #define EHCI_PS_CSC (1 << 1) /* RWC connect status change */ 152 #define EHCI_PS_CS (1 << 0) /* RO connect status */ 153 #define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC) 154 155 #define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == (1 << 10)) 156 157 /* 158 * Schedule Interface Space. 159 * 160 * IMPORTANT: Software must ensure that no interface data structure 161 * reachable by the EHCI host controller spans a 4K page boundary! 162 * 163 * Periodic transfers (i.e. isochronous and interrupt transfers) are 164 * not supported. 165 */ 166 167 /* Queue Element Transfer Descriptor (qTD). */ 168 struct qTD { 169 /* this part defined by EHCI spec */ 170 uint32_t qt_next; /* see EHCI 3.5.1 */ 171 #define QT_NEXT_TERMINATE 1 172 uint32_t qt_altnext; /* see EHCI 3.5.2 */ 173 uint32_t qt_token; /* see EHCI 3.5.3 */ 174 uint32_t qt_buffer[5]; /* see EHCI 3.5.4 */ 175 uint32_t qt_buffer_hi[5]; /* Appendix B */ 176 /* pad struct for 32 byte alignment */ 177 uint32_t unused[3]; 178 }; 179 180 /* Queue Head (QH). */ 181 struct QH { 182 uint32_t qh_link; 183 #define QH_LINK_TERMINATE 1 184 #define QH_LINK_TYPE_ITD 0 185 #define QH_LINK_TYPE_QH 2 186 #define QH_LINK_TYPE_SITD 4 187 #define QH_LINK_TYPE_FSTN 6 188 uint32_t qh_endpt1; 189 uint32_t qh_endpt2; 190 uint32_t qh_curtd; 191 struct qTD qh_overlay; 192 /* 193 * Add dummy fill value to make the size of this struct 194 * aligned to 32 bytes 195 */ 196 uint8_t fill[16]; 197 }; 198 199 /* Low level init functions */ 200 int ehci_hcd_init(void); 201 int ehci_hcd_stop(void); 202 203 #endif /* USB_EHCI_H */ 204