1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * Copyright (c) 2009-2013 NVIDIA Corporation 4 * Copyright (c) 2013 Lucas Stach 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <asm/errno.h> 12 #include <asm/io.h> 13 #include <asm-generic/gpio.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch-tegra/usb.h> 16 #include <asm/arch-tegra/clk_rst.h> 17 #include <usb.h> 18 #include <usb/ulpi.h> 19 #include <libfdt.h> 20 #include <fdtdec.h> 21 22 #include "ehci.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define USB1_ADDR_MASK 0xFFFF0000 27 28 #define HOSTPC1_DEVLC 0x84 29 #define HOSTPC1_PSPD(x) (((x) >> 25) & 0x3) 30 31 #ifdef CONFIG_USB_ULPI 32 #ifndef CONFIG_USB_ULPI_VIEWPORT 33 #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \ 34 define CONFIG_USB_ULPI_VIEWPORT" 35 #endif 36 #endif 37 38 #ifndef CONFIG_DM_USB 39 enum { 40 USB_PORTS_MAX = 3, /* Maximum ports we allow */ 41 }; 42 #endif 43 44 /* Parameters we need for USB */ 45 enum { 46 PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ 47 PARAM_DIVM, /* PLL INPUT DIVIDER */ 48 PARAM_DIVP, /* POST DIVIDER (2^N) */ 49 PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ 50 PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ 51 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ 52 PARAM_STABLE_COUNT, /* PLL-U STABLE count */ 53 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ 54 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ 55 PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ 56 PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ 57 58 PARAM_COUNT 59 }; 60 61 /* Possible port types (dual role mode) */ 62 enum dr_mode { 63 DR_MODE_NONE = 0, 64 DR_MODE_HOST, /* supports host operation */ 65 DR_MODE_DEVICE, /* supports device operation */ 66 DR_MODE_OTG, /* supports both */ 67 }; 68 69 enum usb_ctlr_type { 70 USB_CTLR_T20, 71 USB_CTLR_T30, 72 USB_CTLR_T114, 73 74 USB_CTRL_COUNT, 75 }; 76 77 /* Information about a USB port */ 78 struct fdt_usb { 79 struct ehci_ctrl ehci; 80 struct usb_ctlr *reg; /* address of registers in physical memory */ 81 unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ 82 unsigned ulpi:1; /* 1 if port has external ULPI transceiver */ 83 unsigned enabled:1; /* 1 to enable, 0 to disable */ 84 unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ 85 #ifndef CONFIG_DM_USB 86 unsigned initialized:1; /* has this port already been initialized? */ 87 #endif 88 enum usb_ctlr_type type; 89 enum usb_init_type init_type; 90 enum dr_mode dr_mode; /* dual role mode */ 91 enum periph_id periph_id;/* peripheral id */ 92 struct gpio_desc vbus_gpio; /* GPIO for vbus enable */ 93 struct gpio_desc phy_reset_gpio; /* GPIO to reset ULPI phy */ 94 }; 95 96 #ifndef CONFIG_DM_USB 97 static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */ 98 static unsigned port_count; /* Number of available ports */ 99 #endif 100 101 /* 102 * This table has USB timing parameters for each Oscillator frequency we 103 * support. There are four sets of values: 104 * 105 * 1. PLLU configuration information (reference clock is osc/clk_m and 106 * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). 107 * 108 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 109 * ---------------------------------------------------------------------- 110 * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) 111 * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) 112 * Filter frequency (MHz) 1 4.8 6 2 113 * CPCON 1100b 0011b 1100b 1100b 114 * LFCON0 0 0 0 0 115 * 116 * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: 117 * 118 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 119 * --------------------------------------------------------------------------- 120 * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) 121 * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) 122 * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) 123 * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) 124 * 125 * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and 126 * SessEnd. Each of these signals have their own debouncer and for each of 127 * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or 128 * BIAS_DEBOUNCE_B). 129 * 130 * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: 131 * 0xffff -> No debouncing at all 132 * <n> ms = <n> *1000 / (1/19.2MHz) / 4 133 * 134 * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: 135 * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 136 * 137 * We need to use only DebounceA for BOOTROM. We don't need the DebounceB 138 * values, so we can keep those to default. 139 * 140 * 4. The 20 microsecond delay after bias cell operation. 141 */ 142 static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 143 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 144 { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, 145 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, 146 { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, 147 { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 148 }; 149 150 static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 151 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 152 { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 }, 153 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 }, 154 { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 155 { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 156 }; 157 158 static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 159 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 160 { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 }, 161 { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 }, 162 { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 163 { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB } 164 }; 165 166 /* UTMIP Idle Wait Delay */ 167 static const u8 utmip_idle_wait_delay = 17; 168 169 /* UTMIP Elastic limit */ 170 static const u8 utmip_elastic_limit = 16; 171 172 /* UTMIP High Speed Sync Start Delay */ 173 static const u8 utmip_hs_sync_start_delay = 9; 174 175 struct fdt_usb_controller { 176 /* TODO(sjg@chromium.org): Remove when we only use driver model */ 177 int compat; 178 /* flag to determine whether controller supports hostpc register */ 179 u32 has_hostpc:1; 180 const unsigned *pll_parameter; 181 }; 182 183 static struct fdt_usb_controller fdt_usb_controllers[USB_CTRL_COUNT] = { 184 { 185 .compat = COMPAT_NVIDIA_TEGRA20_USB, 186 .has_hostpc = 0, 187 .pll_parameter = (const unsigned *)T20_usb_pll, 188 }, 189 { 190 .compat = COMPAT_NVIDIA_TEGRA30_USB, 191 .has_hostpc = 1, 192 .pll_parameter = (const unsigned *)T30_usb_pll, 193 }, 194 { 195 .compat = COMPAT_NVIDIA_TEGRA114_USB, 196 .has_hostpc = 1, 197 .pll_parameter = (const unsigned *)T114_usb_pll, 198 }, 199 }; 200 201 /* 202 * A known hardware issue where Connect Status Change bit of PORTSC register 203 * of USB1 controller will be set after Port Reset. 204 * We have to clear it in order for later device enumeration to proceed. 205 */ 206 static void tegra_ehci_powerup_fixup(struct ehci_ctrl *ctrl, 207 uint32_t *status_reg, uint32_t *reg) 208 { 209 struct fdt_usb *config = ctrl->priv; 210 struct fdt_usb_controller *controller; 211 212 controller = &fdt_usb_controllers[config->type]; 213 mdelay(50); 214 /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */ 215 if (controller->has_hostpc) 216 *reg |= EHCI_PS_PE; 217 218 if (!config->has_legacy_mode) 219 return; 220 /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */ 221 if (ehci_readl(status_reg) & EHCI_PS_CSC) 222 *reg |= EHCI_PS_CSC; 223 } 224 225 static void tegra_ehci_set_usbmode(struct ehci_ctrl *ctrl) 226 { 227 struct fdt_usb *config = ctrl->priv; 228 struct usb_ctlr *usbctlr; 229 uint32_t tmp; 230 231 usbctlr = config->reg; 232 233 tmp = ehci_readl(&usbctlr->usb_mode); 234 tmp |= USBMODE_CM_HC; 235 ehci_writel(&usbctlr->usb_mode, tmp); 236 } 237 238 static int tegra_ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg) 239 { 240 struct fdt_usb *config = ctrl->priv; 241 struct fdt_usb_controller *controller; 242 uint32_t tmp; 243 uint32_t *reg_ptr; 244 245 controller = &fdt_usb_controllers[config->type]; 246 if (controller->has_hostpc) { 247 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + 248 HOSTPC1_DEVLC); 249 tmp = ehci_readl(reg_ptr); 250 return HOSTPC1_PSPD(tmp); 251 } else 252 return PORTSC_PSPD(reg); 253 } 254 255 /* Set up VBUS for host/device mode */ 256 static void set_up_vbus(struct fdt_usb *config, enum usb_init_type init) 257 { 258 /* 259 * If we are an OTG port initializing in host mode, 260 * check if remote host is driving VBus and bail out in this case. 261 */ 262 if (init == USB_INIT_HOST && 263 config->dr_mode == DR_MODE_OTG && 264 (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) { 265 printf("tegrausb: VBUS input active; not enabling as host\n"); 266 return; 267 } 268 269 if (dm_gpio_is_valid(&config->vbus_gpio)) { 270 int vbus_value; 271 272 vbus_value = (init == USB_INIT_HOST); 273 dm_gpio_set_value(&config->vbus_gpio, vbus_value); 274 275 debug("set_up_vbus: GPIO %d %d\n", 276 gpio_get_number(&config->vbus_gpio), vbus_value); 277 } 278 } 279 280 static void usbf_reset_controller(struct fdt_usb *config, 281 struct usb_ctlr *usbctlr) 282 { 283 /* Reset the USB controller with 2us delay */ 284 reset_periph(config->periph_id, 2); 285 286 /* 287 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under 288 * base address 289 */ 290 if (config->has_legacy_mode) 291 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); 292 293 /* Put UTMIP1/3 in reset */ 294 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 295 296 /* Enable the UTMIP PHY */ 297 if (config->utmi) 298 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); 299 } 300 301 static const unsigned *get_pll_timing(struct fdt_usb_controller *controller) 302 { 303 const unsigned *timing; 304 305 timing = controller->pll_parameter + 306 clock_get_osc_freq() * PARAM_COUNT; 307 308 return timing; 309 } 310 311 /* select the PHY to use with a USB controller */ 312 static void init_phy_mux(struct fdt_usb *config, uint pts, 313 enum usb_init_type init) 314 { 315 struct usb_ctlr *usbctlr = config->reg; 316 317 #if defined(CONFIG_TEGRA20) 318 if (config->periph_id == PERIPH_ID_USBD) { 319 clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, 320 pts << PTS1_SHIFT); 321 clrbits_le32(&usbctlr->port_sc1, STS1); 322 } else { 323 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, 324 pts << PTS_SHIFT); 325 clrbits_le32(&usbctlr->port_sc1, STS); 326 } 327 #else 328 /* Set to Host mode (if applicable) after Controller Reset was done */ 329 clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, 330 (init == USB_INIT_HOST) ? USBMODE_CM_HC : 0); 331 /* 332 * Select PHY interface after setting host mode. 333 * For device mode, the ordering requirement is not an issue, since 334 * only the first USB controller supports device mode, and that USB 335 * controller can only talk to a UTMI PHY, so the PHY selection is 336 * already made at reset time, so this write is a no-op. 337 */ 338 clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, 339 pts << PTS_SHIFT); 340 clrbits_le32(&usbctlr->hostpc1_devlc, STS); 341 #endif 342 } 343 344 /* set up the UTMI USB controller with the parameters provided */ 345 static int init_utmi_usb_controller(struct fdt_usb *config, 346 enum usb_init_type init) 347 { 348 struct fdt_usb_controller *controller; 349 u32 b_sess_valid_mask, val; 350 int loop_count; 351 const unsigned *timing; 352 struct usb_ctlr *usbctlr = config->reg; 353 struct clk_rst_ctlr *clkrst; 354 struct usb_ctlr *usb1ctlr; 355 356 clock_enable(config->periph_id); 357 358 /* Reset the usb controller */ 359 usbf_reset_controller(config, usbctlr); 360 361 /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ 362 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 363 364 /* Follow the crystal clock disable by >100ns delay */ 365 udelay(1); 366 367 b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN); 368 clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask, 369 (init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0); 370 371 /* 372 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP 373 * mux must be switched to actually use a_sess_vld threshold. 374 */ 375 if (config->dr_mode == DR_MODE_OTG && 376 dm_gpio_is_valid(&config->vbus_gpio)) 377 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, 378 VBUS_SENSE_CTL_MASK, 379 VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); 380 381 controller = &fdt_usb_controllers[config->type]; 382 debug("controller=%p, type=%d\n", controller, config->type); 383 384 /* 385 * PLL Delay CONFIGURATION settings. The following parameters control 386 * the bring up of the plls. 387 */ 388 timing = get_pll_timing(controller); 389 390 if (!controller->has_hostpc) { 391 val = readl(&usbctlr->utmip_misc_cfg1); 392 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 393 timing[PARAM_STABLE_COUNT] << 394 UTMIP_PLLU_STABLE_COUNT_SHIFT); 395 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 396 timing[PARAM_ACTIVE_DELAY_COUNT] << 397 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 398 writel(val, &usbctlr->utmip_misc_cfg1); 399 400 /* Set PLL enable delay count and crystal frequency count */ 401 val = readl(&usbctlr->utmip_pll_cfg1); 402 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 403 timing[PARAM_ENABLE_DELAY_COUNT] << 404 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 405 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 406 timing[PARAM_XTAL_FREQ_COUNT] << 407 UTMIP_XTAL_FREQ_COUNT_SHIFT); 408 writel(val, &usbctlr->utmip_pll_cfg1); 409 } else { 410 clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 411 412 val = readl(&clkrst->crc_utmip_pll_cfg2); 413 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 414 timing[PARAM_STABLE_COUNT] << 415 UTMIP_PLLU_STABLE_COUNT_SHIFT); 416 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 417 timing[PARAM_ACTIVE_DELAY_COUNT] << 418 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 419 writel(val, &clkrst->crc_utmip_pll_cfg2); 420 421 /* Set PLL enable delay count and crystal frequency count */ 422 val = readl(&clkrst->crc_utmip_pll_cfg1); 423 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 424 timing[PARAM_ENABLE_DELAY_COUNT] << 425 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 426 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 427 timing[PARAM_XTAL_FREQ_COUNT] << 428 UTMIP_XTAL_FREQ_COUNT_SHIFT); 429 writel(val, &clkrst->crc_utmip_pll_cfg1); 430 431 /* Disable Power Down state for PLL */ 432 clrbits_le32(&clkrst->crc_utmip_pll_cfg1, 433 PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN | 434 PLL_ACTIVE_POWERDOWN); 435 436 /* Recommended PHY settings for EYE diagram */ 437 val = readl(&usbctlr->utmip_xcvr_cfg0); 438 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK, 439 0x4 << UTMIP_XCVR_SETUP_SHIFT); 440 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK, 441 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT); 442 clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK, 443 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT); 444 writel(val, &usbctlr->utmip_xcvr_cfg0); 445 clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1, 446 UTMIP_XCVR_TERM_RANGE_ADJ_MASK, 447 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT); 448 449 /* Some registers can be controlled from USB1 only. */ 450 if (config->periph_id != PERIPH_ID_USBD) { 451 clock_enable(PERIPH_ID_USBD); 452 /* Disable Reset if in Reset state */ 453 reset_set_enable(PERIPH_ID_USBD, 0); 454 } 455 usb1ctlr = (struct usb_ctlr *) 456 ((unsigned long)config->reg & USB1_ADDR_MASK); 457 val = readl(&usb1ctlr->utmip_bias_cfg0); 458 setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB); 459 clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK, 460 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT); 461 clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK, 462 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT); 463 writel(val, &usb1ctlr->utmip_bias_cfg0); 464 465 /* Miscellaneous setting mentioned in Programming Guide */ 466 clrbits_le32(&usbctlr->utmip_misc_cfg0, 467 UTMIP_SUSPEND_EXIT_ON_EDGE); 468 } 469 470 /* Setting the tracking length time */ 471 clrsetbits_le32(&usbctlr->utmip_bias_cfg1, 472 UTMIP_BIAS_PDTRK_COUNT_MASK, 473 timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); 474 475 /* Program debounce time for VBUS to become valid */ 476 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, 477 UTMIP_DEBOUNCE_CFG0_MASK, 478 timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); 479 480 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); 481 482 /* Disable battery charge enabling bit */ 483 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); 484 485 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); 486 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); 487 488 /* 489 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT 490 * Setting these fields, together with default values of the 491 * other fields, results in programming the registers below as 492 * follows: 493 * UTMIP_HSRX_CFG0 = 0x9168c000 494 * UTMIP_HSRX_CFG1 = 0x13 495 */ 496 497 /* Set PLL enable delay count and Crystal frequency count */ 498 val = readl(&usbctlr->utmip_hsrx_cfg0); 499 clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, 500 utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); 501 clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, 502 utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); 503 writel(val, &usbctlr->utmip_hsrx_cfg0); 504 505 /* Configure the UTMIP_HS_SYNC_START_DLY */ 506 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, 507 UTMIP_HS_SYNC_START_DLY_MASK, 508 utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); 509 510 /* Preceed the crystal clock disable by >100ns delay. */ 511 udelay(1); 512 513 /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ 514 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 515 516 if (controller->has_hostpc) { 517 if (config->periph_id == PERIPH_ID_USBD) 518 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 519 UTMIP_FORCE_PD_SAMP_A_POWERDOWN); 520 if (config->periph_id == PERIPH_ID_USB2) 521 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 522 UTMIP_FORCE_PD_SAMP_B_POWERDOWN); 523 if (config->periph_id == PERIPH_ID_USB3) 524 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 525 UTMIP_FORCE_PD_SAMP_C_POWERDOWN); 526 } 527 /* Finished the per-controller init. */ 528 529 /* De-assert UTMIP_RESET to bring out of reset. */ 530 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 531 532 /* Wait for the phy clock to become valid in 100 ms */ 533 for (loop_count = 100000; loop_count != 0; loop_count--) { 534 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 535 break; 536 udelay(1); 537 } 538 if (!loop_count) 539 return -ETIMEDOUT; 540 541 /* Disable ICUSB FS/LS transceiver */ 542 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); 543 544 /* Select UTMI parallel interface */ 545 init_phy_mux(config, PTS_UTMI, init); 546 547 /* Deassert power down state */ 548 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | 549 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); 550 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | 551 UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); 552 553 if (controller->has_hostpc) { 554 /* 555 * BIAS Pad Power Down is common among all 3 USB 556 * controllers and can be controlled from USB1 only. 557 */ 558 usb1ctlr = (struct usb_ctlr *) 559 ((unsigned long)config->reg & USB1_ADDR_MASK); 560 clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD); 561 udelay(25); 562 clrbits_le32(&usb1ctlr->utmip_bias_cfg1, 563 UTMIP_FORCE_PDTRK_POWERDOWN); 564 } 565 return 0; 566 } 567 568 #ifdef CONFIG_USB_ULPI 569 /* if board file does not set a ULPI reference frequency we default to 24MHz */ 570 #ifndef CONFIG_ULPI_REF_CLK 571 #define CONFIG_ULPI_REF_CLK 24000000 572 #endif 573 574 /* set up the ULPI USB controller with the parameters provided */ 575 static int init_ulpi_usb_controller(struct fdt_usb *config, 576 enum usb_init_type init) 577 { 578 u32 val; 579 int loop_count; 580 struct ulpi_viewport ulpi_vp; 581 struct usb_ctlr *usbctlr = config->reg; 582 int ret; 583 584 /* set up ULPI reference clock on pllp_out4 */ 585 clock_enable(PERIPH_ID_DEV2_OUT); 586 clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK); 587 588 /* reset ULPI phy */ 589 if (dm_gpio_is_valid(&config->phy_reset_gpio)) { 590 dm_gpio_set_value(&config->phy_reset_gpio, 0); 591 mdelay(5); 592 dm_gpio_set_value(&config->phy_reset_gpio, 1); 593 } 594 595 /* Reset the usb controller */ 596 clock_enable(config->periph_id); 597 usbf_reset_controller(config, usbctlr); 598 599 /* enable pinmux bypass */ 600 setbits_le32(&usbctlr->ulpi_timing_ctrl_0, 601 ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); 602 603 /* Select ULPI parallel interface */ 604 init_phy_mux(config, PTS_ULPI, init); 605 606 /* enable ULPI transceiver */ 607 setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); 608 609 /* configure ULPI transceiver timings */ 610 val = 0; 611 writel(val, &usbctlr->ulpi_timing_ctrl_1); 612 613 val |= ULPI_DATA_TRIMMER_SEL(4); 614 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); 615 val |= ULPI_DIR_TRIMMER_SEL(4); 616 writel(val, &usbctlr->ulpi_timing_ctrl_1); 617 udelay(10); 618 619 val |= ULPI_DATA_TRIMMER_LOAD; 620 val |= ULPI_STPDIRNXT_TRIMMER_LOAD; 621 val |= ULPI_DIR_TRIMMER_LOAD; 622 writel(val, &usbctlr->ulpi_timing_ctrl_1); 623 624 /* set up phy for host operation with external vbus supply */ 625 ulpi_vp.port_num = 0; 626 ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport; 627 628 ret = ulpi_init(&ulpi_vp); 629 if (ret) { 630 printf("Tegra ULPI viewport init failed\n"); 631 return ret; 632 } 633 634 ulpi_set_vbus(&ulpi_vp, 1, 1); 635 ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0); 636 637 /* enable wakeup events */ 638 setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC); 639 640 /* Enable and wait for the phy clock to become valid in 100 ms */ 641 setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 642 for (loop_count = 100000; loop_count != 0; loop_count--) { 643 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 644 break; 645 udelay(1); 646 } 647 if (!loop_count) 648 return -ETIMEDOUT; 649 clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 650 651 return 0; 652 } 653 #else 654 static int init_ulpi_usb_controller(struct fdt_usb *config, 655 enum usb_init_type init) 656 { 657 printf("No code to set up ULPI controller, please enable" 658 "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT"); 659 return -ENOSYS; 660 } 661 #endif 662 663 static void config_clock(const u32 timing[]) 664 { 665 clock_start_pll(CLOCK_ID_USB, 666 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], 667 timing[PARAM_CPCON], timing[PARAM_LFCON]); 668 } 669 670 static int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config) 671 { 672 const char *phy, *mode; 673 674 config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg"); 675 mode = fdt_getprop(blob, node, "dr_mode", NULL); 676 if (mode) { 677 if (0 == strcmp(mode, "host")) 678 config->dr_mode = DR_MODE_HOST; 679 else if (0 == strcmp(mode, "peripheral")) 680 config->dr_mode = DR_MODE_DEVICE; 681 else if (0 == strcmp(mode, "otg")) 682 config->dr_mode = DR_MODE_OTG; 683 else { 684 debug("%s: Cannot decode dr_mode '%s'\n", __func__, 685 mode); 686 return -EINVAL; 687 } 688 } else { 689 config->dr_mode = DR_MODE_HOST; 690 } 691 692 phy = fdt_getprop(blob, node, "phy_type", NULL); 693 config->utmi = phy && 0 == strcmp("utmi", phy); 694 config->ulpi = phy && 0 == strcmp("ulpi", phy); 695 config->enabled = fdtdec_get_is_enabled(blob, node); 696 config->has_legacy_mode = fdtdec_get_bool(blob, node, 697 "nvidia,has-legacy-mode"); 698 config->periph_id = clock_decode_periph_id(blob, node); 699 if (config->periph_id == PERIPH_ID_NONE) { 700 debug("%s: Missing/invalid peripheral ID\n", __func__); 701 return -EINVAL; 702 } 703 gpio_request_by_name_nodev(blob, node, "nvidia,vbus-gpio", 0, 704 &config->vbus_gpio, GPIOD_IS_OUT); 705 gpio_request_by_name_nodev(blob, node, "nvidia,phy-reset-gpio", 0, 706 &config->phy_reset_gpio, GPIOD_IS_OUT); 707 debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, " 708 "vbus=%d, phy_reset=%d, dr_mode=%d\n", 709 config->enabled, config->has_legacy_mode, config->utmi, 710 config->ulpi, config->periph_id, 711 gpio_get_number(&config->vbus_gpio), 712 gpio_get_number(&config->phy_reset_gpio), config->dr_mode); 713 714 return 0; 715 } 716 717 int usb_common_init(struct fdt_usb *config, enum usb_init_type init) 718 { 719 int ret = 0; 720 721 switch (init) { 722 case USB_INIT_HOST: 723 switch (config->dr_mode) { 724 case DR_MODE_HOST: 725 case DR_MODE_OTG: 726 break; 727 default: 728 printf("tegrausb: Invalid dr_mode %d for host mode\n", 729 config->dr_mode); 730 return -1; 731 } 732 break; 733 case USB_INIT_DEVICE: 734 if (config->periph_id != PERIPH_ID_USBD) { 735 printf("tegrausb: Device mode only supported on first USB controller\n"); 736 return -1; 737 } 738 if (!config->utmi) { 739 printf("tegrausb: Device mode only supported with UTMI PHY\n"); 740 return -1; 741 } 742 switch (config->dr_mode) { 743 case DR_MODE_DEVICE: 744 case DR_MODE_OTG: 745 break; 746 default: 747 printf("tegrausb: Invalid dr_mode %d for device mode\n", 748 config->dr_mode); 749 return -1; 750 } 751 break; 752 default: 753 printf("tegrausb: Unknown USB_INIT_* %d\n", init); 754 return -1; 755 } 756 757 #ifndef CONFIG_DM_USB 758 /* skip init, if the port is already initialized */ 759 if (config->initialized && config->init_type == init) 760 return 0; 761 #endif 762 763 debug("%d, %d\n", config->utmi, config->ulpi); 764 if (config->utmi) 765 ret = init_utmi_usb_controller(config, init); 766 else if (config->ulpi) 767 ret = init_ulpi_usb_controller(config, init); 768 if (ret) 769 return ret; 770 771 set_up_vbus(config, init); 772 773 config->init_type = init; 774 775 return 0; 776 } 777 778 void usb_common_uninit(struct fdt_usb *priv) 779 { 780 struct usb_ctlr *usbctlr; 781 782 usbctlr = priv->reg; 783 784 /* Stop controller */ 785 writel(0, &usbctlr->usb_cmd); 786 udelay(1000); 787 788 /* Initiate controller reset */ 789 writel(2, &usbctlr->usb_cmd); 790 udelay(1000); 791 } 792 793 static const struct ehci_ops tegra_ehci_ops = { 794 .set_usb_mode = tegra_ehci_set_usbmode, 795 .get_port_speed = tegra_ehci_get_port_speed, 796 .powerup_fixup = tegra_ehci_powerup_fixup, 797 }; 798 799 #ifndef CONFIG_DM_USB 800 /* 801 * process_usb_nodes() - Process a list of USB nodes, adding them to our list 802 * of USB ports. 803 * @blob: fdt blob 804 * @node_list: list of nodes to process (any <=0 are ignored) 805 * @count: number of nodes to process 806 * @id: controller type (enum usb_ctlr_type) 807 * 808 * Return: 0 - ok, -1 - error 809 */ 810 static int process_usb_nodes(const void *blob, int node_list[], int count, 811 enum usb_ctlr_type id) 812 { 813 struct fdt_usb config; 814 int node, i; 815 int clk_done = 0; 816 817 port_count = 0; 818 for (i = 0; i < count; i++) { 819 if (port_count == USB_PORTS_MAX) { 820 printf("tegrausb: Cannot register more than %d ports\n", 821 USB_PORTS_MAX); 822 return -1; 823 } 824 825 debug("USB %d: ", i); 826 node = node_list[i]; 827 if (!node) 828 continue; 829 if (fdt_decode_usb(blob, node, &config)) { 830 debug("Cannot decode USB node %s\n", 831 fdt_get_name(blob, node, NULL)); 832 return -1; 833 } 834 if (!clk_done) { 835 config_clock(get_pll_timing( 836 &fdt_usb_controllers[id])); 837 clk_done = 1; 838 } 839 config.type = id; 840 config.initialized = 0; 841 842 /* add new USB port to the list of available ports */ 843 port[port_count++] = config; 844 } 845 846 return 0; 847 } 848 849 int usb_process_devicetree(const void *blob) 850 { 851 int node_list[USB_PORTS_MAX]; 852 int count, err = 0; 853 int i; 854 855 for (i = 0; i < ARRAY_SIZE(fdt_usb_controllers); i++) { 856 count = fdtdec_find_aliases_for_id(blob, "usb", 857 fdt_usb_controllers[i].compat, node_list, 858 USB_PORTS_MAX); 859 if (count) { 860 err = process_usb_nodes(blob, node_list, count, i); 861 if (err) 862 printf("%s: Error processing USB node!\n", 863 __func__); 864 return err; 865 } 866 } 867 868 return err; 869 } 870 871 /** 872 * Start up the given port number (ports are numbered from 0 on each board). 873 * This returns values for the appropriate hccr and hcor addresses to use for 874 * USB EHCI operations. 875 * 876 * @param index port number to start 877 * @param hccr returns start address of EHCI HCCR registers 878 * @param hcor returns start address of EHCI HCOR registers 879 * @return 0 if ok, -1 on error (generally invalid port number) 880 */ 881 int ehci_hcd_init(int index, enum usb_init_type init, 882 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 883 { 884 struct fdt_usb *config; 885 struct usb_ctlr *usbctlr; 886 int ret; 887 888 if (index >= port_count) 889 return -1; 890 891 config = &port[index]; 892 ehci_set_controller_priv(index, config, &tegra_ehci_ops); 893 894 ret = usb_common_init(config, init); 895 if (ret) { 896 printf("tegrausb: Cannot init port %d\n", index); 897 return ret; 898 } 899 900 config->initialized = 1; 901 902 usbctlr = config->reg; 903 *hccr = (struct ehci_hccr *)&usbctlr->cap_length; 904 *hcor = (struct ehci_hcor *)&usbctlr->usb_cmd; 905 906 return 0; 907 } 908 909 /* 910 * Bring down the specified USB controller 911 */ 912 int ehci_hcd_stop(int index) 913 { 914 usb_common_uninit(&port[index]); 915 916 port[index].initialized = 0; 917 918 return 0; 919 } 920 #endif /* !CONFIG_DM_USB */ 921 922 #ifdef CONFIG_DM_USB 923 static int ehci_usb_ofdata_to_platdata(struct udevice *dev) 924 { 925 struct fdt_usb *priv = dev_get_priv(dev); 926 int ret; 927 928 ret = fdt_decode_usb(gd->fdt_blob, dev->of_offset, priv); 929 if (ret) 930 return ret; 931 932 priv->type = dev_get_driver_data(dev); 933 934 return 0; 935 } 936 937 static int ehci_usb_probe(struct udevice *dev) 938 { 939 struct usb_platdata *plat = dev_get_platdata(dev); 940 struct fdt_usb *priv = dev_get_priv(dev); 941 struct ehci_hccr *hccr; 942 struct ehci_hcor *hcor; 943 static bool clk_done; 944 int ret; 945 946 ret = usb_common_init(priv, plat->init_type); 947 if (ret) 948 return ret; 949 hccr = (struct ehci_hccr *)&priv->reg->cap_length; 950 hcor = (struct ehci_hcor *)&priv->reg->usb_cmd; 951 if (!clk_done) { 952 config_clock(get_pll_timing(&fdt_usb_controllers[priv->type])); 953 clk_done = true; 954 } 955 956 return ehci_register(dev, hccr, hcor, &tegra_ehci_ops, 0, 957 plat->init_type); 958 } 959 960 static int ehci_usb_remove(struct udevice *dev) 961 { 962 int ret; 963 964 ret = ehci_deregister(dev); 965 if (ret) 966 return ret; 967 968 return 0; 969 } 970 971 static const struct udevice_id ehci_usb_ids[] = { 972 { .compatible = "nvidia,tegra20-ehci", .data = USB_CTLR_T20 }, 973 { .compatible = "nvidia,tegra30-ehci", .data = USB_CTLR_T30 }, 974 { .compatible = "nvidia,tegra114-ehci", .data = USB_CTLR_T114 }, 975 { } 976 }; 977 978 U_BOOT_DRIVER(usb_ehci) = { 979 .name = "ehci_tegra", 980 .id = UCLASS_USB, 981 .of_match = ehci_usb_ids, 982 .ofdata_to_platdata = ehci_usb_ofdata_to_platdata, 983 .probe = ehci_usb_probe, 984 .remove = ehci_usb_remove, 985 .ops = &ehci_usb_ops, 986 .platdata_auto_alloc_size = sizeof(struct usb_platdata), 987 .priv_auto_alloc_size = sizeof(struct fdt_usb), 988 .flags = DM_FLAG_ALLOC_PRIV_DMA, 989 }; 990 #endif 991