1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * Copyright (c) 2009-2013 NVIDIA Corporation 4 * Copyright (c) 2013 Lucas Stach 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/errno.h> 27 #include <asm/io.h> 28 #include <asm-generic/gpio.h> 29 #include <asm/arch/clock.h> 30 #include <asm/arch-tegra/usb.h> 31 #include <asm/arch-tegra/clk_rst.h> 32 #include <asm/arch/usb.h> 33 #include <usb.h> 34 #include <usb/ulpi.h> 35 #include <libfdt.h> 36 #include <fdtdec.h> 37 38 #include "ehci.h" 39 40 #define USB1_ADDR_MASK 0xFFFF0000 41 42 #define HOSTPC1_DEVLC 0x84 43 #define HOSTPC1_PSPD(x) (((x) >> 25) & 0x3) 44 45 #ifdef CONFIG_USB_ULPI 46 #ifndef CONFIG_USB_ULPI_VIEWPORT 47 #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \ 48 define CONFIG_USB_ULPI_VIEWPORT" 49 #endif 50 #endif 51 52 enum { 53 USB_PORTS_MAX = 3, /* Maximum ports we allow */ 54 }; 55 56 /* Parameters we need for USB */ 57 enum { 58 PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ 59 PARAM_DIVM, /* PLL INPUT DIVIDER */ 60 PARAM_DIVP, /* POST DIVIDER (2^N) */ 61 PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ 62 PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ 63 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ 64 PARAM_STABLE_COUNT, /* PLL-U STABLE count */ 65 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ 66 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ 67 PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ 68 PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ 69 70 PARAM_COUNT 71 }; 72 73 /* Possible port types (dual role mode) */ 74 enum dr_mode { 75 DR_MODE_NONE = 0, 76 DR_MODE_HOST, /* supports host operation */ 77 DR_MODE_DEVICE, /* supports device operation */ 78 DR_MODE_OTG, /* supports both */ 79 }; 80 81 /* Information about a USB port */ 82 struct fdt_usb { 83 struct usb_ctlr *reg; /* address of registers in physical memory */ 84 unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ 85 unsigned ulpi:1; /* 1 if port has external ULPI transceiver */ 86 unsigned enabled:1; /* 1 to enable, 0 to disable */ 87 unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ 88 unsigned initialized:1; /* has this port already been initialized? */ 89 enum dr_mode dr_mode; /* dual role mode */ 90 enum periph_id periph_id;/* peripheral id */ 91 struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */ 92 struct fdt_gpio_state phy_reset_gpio; /* GPIO to reset ULPI phy */ 93 }; 94 95 static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */ 96 static unsigned port_count; /* Number of available ports */ 97 /* Port that needs to clear CSC after Port Reset */ 98 static u32 port_addr_clear_csc; 99 100 /* 101 * This table has USB timing parameters for each Oscillator frequency we 102 * support. There are four sets of values: 103 * 104 * 1. PLLU configuration information (reference clock is osc/clk_m and 105 * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). 106 * 107 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 108 * ---------------------------------------------------------------------- 109 * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) 110 * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) 111 * Filter frequency (MHz) 1 4.8 6 2 112 * CPCON 1100b 0011b 1100b 1100b 113 * LFCON0 0 0 0 0 114 * 115 * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: 116 * 117 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 118 * --------------------------------------------------------------------------- 119 * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) 120 * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) 121 * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) 122 * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) 123 * 124 * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and 125 * SessEnd. Each of these signals have their own debouncer and for each of 126 * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or 127 * BIAS_DEBOUNCE_B). 128 * 129 * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: 130 * 0xffff -> No debouncing at all 131 * <n> ms = <n> *1000 / (1/19.2MHz) / 4 132 * 133 * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: 134 * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 135 * 136 * We need to use only DebounceA for BOOTROM. We don't need the DebounceB 137 * values, so we can keep those to default. 138 * 139 * 4. The 20 microsecond delay after bias cell operation. 140 */ 141 static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 142 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 143 { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, 144 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, 145 { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, 146 { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 147 }; 148 149 static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 150 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 151 { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 }, 152 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 }, 153 { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 154 { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 155 }; 156 157 static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 158 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 159 { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 }, 160 { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 }, 161 { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 162 { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB } 163 }; 164 165 /* UTMIP Idle Wait Delay */ 166 static const u8 utmip_idle_wait_delay = 17; 167 168 /* UTMIP Elastic limit */ 169 static const u8 utmip_elastic_limit = 16; 170 171 /* UTMIP High Speed Sync Start Delay */ 172 static const u8 utmip_hs_sync_start_delay = 9; 173 174 struct fdt_usb_controller { 175 int compat; 176 /* flag to determine whether controller supports hostpc register */ 177 u32 has_hostpc:1; 178 const unsigned *pll_parameter; 179 }; 180 181 static struct fdt_usb_controller fdt_usb_controllers[] = { 182 { 183 .compat = COMPAT_NVIDIA_TEGRA20_USB, 184 .has_hostpc = 0, 185 .pll_parameter = (const unsigned *)T20_usb_pll, 186 }, 187 { 188 .compat = COMPAT_NVIDIA_TEGRA30_USB, 189 .has_hostpc = 1, 190 .pll_parameter = (const unsigned *)T30_usb_pll, 191 }, 192 { 193 .compat = COMPAT_NVIDIA_TEGRA114_USB, 194 .has_hostpc = 1, 195 .pll_parameter = (const unsigned *)T114_usb_pll, 196 }, 197 }; 198 199 static struct fdt_usb_controller *controller; 200 201 /* 202 * A known hardware issue where Connect Status Change bit of PORTSC register 203 * of USB1 controller will be set after Port Reset. 204 * We have to clear it in order for later device enumeration to proceed. 205 * This ehci_powerup_fixup overrides the weak function ehci_powerup_fixup 206 * in "ehci-hcd.c". 207 */ 208 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) 209 { 210 mdelay(50); 211 /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */ 212 if (controller->has_hostpc) 213 *reg |= EHCI_PS_PE; 214 215 if (((u32)status_reg & TEGRA_USB_ADDR_MASK) != port_addr_clear_csc) 216 return; 217 /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */ 218 if (ehci_readl(status_reg) & EHCI_PS_CSC) 219 *reg |= EHCI_PS_CSC; 220 } 221 222 /* 223 * This ehci_set_usbmode overrides the weak function ehci_set_usbmode 224 * in "ehci-hcd.c". 225 */ 226 void ehci_set_usbmode(int index) 227 { 228 struct fdt_usb *config; 229 struct usb_ctlr *usbctlr; 230 uint32_t tmp; 231 232 config = &port[index]; 233 usbctlr = config->reg; 234 235 tmp = ehci_readl(&usbctlr->usb_mode); 236 tmp |= USBMODE_CM_HC; 237 ehci_writel(&usbctlr->usb_mode, tmp); 238 } 239 240 /* 241 * This ehci_get_port_speed overrides the weak function ehci_get_port_speed 242 * in "ehci-hcd.c". 243 */ 244 int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg) 245 { 246 uint32_t tmp; 247 uint32_t *reg_ptr; 248 249 if (controller->has_hostpc) { 250 reg_ptr = (uint32_t *)((u8 *)&hcor->or_usbcmd + HOSTPC1_DEVLC); 251 tmp = ehci_readl(reg_ptr); 252 return HOSTPC1_PSPD(tmp); 253 } else 254 return PORTSC_PSPD(reg); 255 } 256 257 /* Put the port into host mode */ 258 static void set_host_mode(struct fdt_usb *config) 259 { 260 /* 261 * If we are an OTG port, check if remote host is driving VBus and 262 * bail out in this case. 263 */ 264 if (config->dr_mode == DR_MODE_OTG && 265 (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) 266 return; 267 268 /* 269 * If not driving, we set the GPIO to enable VBUS. We assume 270 * that the pinmux is set up correctly for this. 271 */ 272 if (fdt_gpio_isvalid(&config->vbus_gpio)) { 273 fdtdec_setup_gpio(&config->vbus_gpio); 274 gpio_direction_output(config->vbus_gpio.gpio, 275 (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? 276 0 : 1); 277 debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio, 278 (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? 279 "low" : "high"); 280 } 281 } 282 283 void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr) 284 { 285 /* Reset the USB controller with 2us delay */ 286 reset_periph(config->periph_id, 2); 287 288 /* 289 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under 290 * base address 291 */ 292 if (config->has_legacy_mode) 293 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); 294 295 /* Put UTMIP1/3 in reset */ 296 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 297 298 /* Enable the UTMIP PHY */ 299 if (config->utmi) 300 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); 301 } 302 303 static const unsigned *get_pll_timing(void) 304 { 305 const unsigned *timing; 306 307 timing = controller->pll_parameter + 308 clock_get_osc_freq() * PARAM_COUNT; 309 310 return timing; 311 } 312 313 /* set up the UTMI USB controller with the parameters provided */ 314 static int init_utmi_usb_controller(struct fdt_usb *config) 315 { 316 u32 val; 317 int loop_count; 318 const unsigned *timing; 319 struct usb_ctlr *usbctlr = config->reg; 320 struct clk_rst_ctlr *clkrst; 321 struct usb_ctlr *usb1ctlr; 322 323 clock_enable(config->periph_id); 324 325 /* Reset the usb controller */ 326 usbf_reset_controller(config, usbctlr); 327 328 /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ 329 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 330 331 /* Follow the crystal clock disable by >100ns delay */ 332 udelay(1); 333 334 /* 335 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP 336 * mux must be switched to actually use a_sess_vld threshold. 337 */ 338 if (config->dr_mode == DR_MODE_OTG && 339 fdt_gpio_isvalid(&config->vbus_gpio)) 340 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, 341 VBUS_SENSE_CTL_MASK, 342 VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); 343 344 /* 345 * PLL Delay CONFIGURATION settings. The following parameters control 346 * the bring up of the plls. 347 */ 348 timing = get_pll_timing(); 349 350 if (!controller->has_hostpc) { 351 val = readl(&usbctlr->utmip_misc_cfg1); 352 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 353 timing[PARAM_STABLE_COUNT] << 354 UTMIP_PLLU_STABLE_COUNT_SHIFT); 355 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 356 timing[PARAM_ACTIVE_DELAY_COUNT] << 357 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 358 writel(val, &usbctlr->utmip_misc_cfg1); 359 360 /* Set PLL enable delay count and crystal frequency count */ 361 val = readl(&usbctlr->utmip_pll_cfg1); 362 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 363 timing[PARAM_ENABLE_DELAY_COUNT] << 364 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 365 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 366 timing[PARAM_XTAL_FREQ_COUNT] << 367 UTMIP_XTAL_FREQ_COUNT_SHIFT); 368 writel(val, &usbctlr->utmip_pll_cfg1); 369 } else { 370 clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 371 372 val = readl(&clkrst->crc_utmip_pll_cfg2); 373 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 374 timing[PARAM_STABLE_COUNT] << 375 UTMIP_PLLU_STABLE_COUNT_SHIFT); 376 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 377 timing[PARAM_ACTIVE_DELAY_COUNT] << 378 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 379 writel(val, &clkrst->crc_utmip_pll_cfg2); 380 381 /* Set PLL enable delay count and crystal frequency count */ 382 val = readl(&clkrst->crc_utmip_pll_cfg1); 383 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 384 timing[PARAM_ENABLE_DELAY_COUNT] << 385 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 386 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 387 timing[PARAM_XTAL_FREQ_COUNT] << 388 UTMIP_XTAL_FREQ_COUNT_SHIFT); 389 writel(val, &clkrst->crc_utmip_pll_cfg1); 390 391 /* Disable Power Down state for PLL */ 392 clrbits_le32(&clkrst->crc_utmip_pll_cfg1, 393 PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN | 394 PLL_ACTIVE_POWERDOWN); 395 396 /* Recommended PHY settings for EYE diagram */ 397 val = readl(&usbctlr->utmip_xcvr_cfg0); 398 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK, 399 0x4 << UTMIP_XCVR_SETUP_SHIFT); 400 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK, 401 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT); 402 clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK, 403 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT); 404 writel(val, &usbctlr->utmip_xcvr_cfg0); 405 clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1, 406 UTMIP_XCVR_TERM_RANGE_ADJ_MASK, 407 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT); 408 409 /* Some registers can be controlled from USB1 only. */ 410 if (config->periph_id != PERIPH_ID_USBD) { 411 clock_enable(PERIPH_ID_USBD); 412 /* Disable Reset if in Reset state */ 413 reset_set_enable(PERIPH_ID_USBD, 0); 414 } 415 usb1ctlr = (struct usb_ctlr *) 416 ((u32)config->reg & USB1_ADDR_MASK); 417 val = readl(&usb1ctlr->utmip_bias_cfg0); 418 setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB); 419 clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK, 420 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT); 421 clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK, 422 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT); 423 writel(val, &usb1ctlr->utmip_bias_cfg0); 424 425 /* Miscellaneous setting mentioned in Programming Guide */ 426 clrbits_le32(&usbctlr->utmip_misc_cfg0, 427 UTMIP_SUSPEND_EXIT_ON_EDGE); 428 } 429 430 /* Setting the tracking length time */ 431 clrsetbits_le32(&usbctlr->utmip_bias_cfg1, 432 UTMIP_BIAS_PDTRK_COUNT_MASK, 433 timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); 434 435 /* Program debounce time for VBUS to become valid */ 436 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, 437 UTMIP_DEBOUNCE_CFG0_MASK, 438 timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); 439 440 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); 441 442 /* Disable battery charge enabling bit */ 443 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); 444 445 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); 446 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); 447 448 /* 449 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT 450 * Setting these fields, together with default values of the 451 * other fields, results in programming the registers below as 452 * follows: 453 * UTMIP_HSRX_CFG0 = 0x9168c000 454 * UTMIP_HSRX_CFG1 = 0x13 455 */ 456 457 /* Set PLL enable delay count and Crystal frequency count */ 458 val = readl(&usbctlr->utmip_hsrx_cfg0); 459 clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, 460 utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); 461 clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, 462 utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); 463 writel(val, &usbctlr->utmip_hsrx_cfg0); 464 465 /* Configure the UTMIP_HS_SYNC_START_DLY */ 466 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, 467 UTMIP_HS_SYNC_START_DLY_MASK, 468 utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); 469 470 /* Preceed the crystal clock disable by >100ns delay. */ 471 udelay(1); 472 473 /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ 474 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 475 476 if (controller->has_hostpc) { 477 if (config->periph_id == PERIPH_ID_USBD) 478 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 479 UTMIP_FORCE_PD_SAMP_A_POWERDOWN); 480 if (config->periph_id == PERIPH_ID_USB3) 481 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 482 UTMIP_FORCE_PD_SAMP_C_POWERDOWN); 483 } 484 /* Finished the per-controller init. */ 485 486 /* De-assert UTMIP_RESET to bring out of reset. */ 487 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 488 489 /* Wait for the phy clock to become valid in 100 ms */ 490 for (loop_count = 100000; loop_count != 0; loop_count--) { 491 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 492 break; 493 udelay(1); 494 } 495 if (!loop_count) 496 return -1; 497 498 /* Disable ICUSB FS/LS transceiver */ 499 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); 500 501 /* Select UTMI parallel interface */ 502 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, 503 PTS_UTMI << PTS_SHIFT); 504 clrbits_le32(&usbctlr->port_sc1, STS); 505 506 /* Deassert power down state */ 507 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | 508 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); 509 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | 510 UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); 511 512 if (controller->has_hostpc) { 513 /* 514 * BIAS Pad Power Down is common among all 3 USB 515 * controllers and can be controlled from USB1 only. 516 */ 517 usb1ctlr = (struct usb_ctlr *) 518 ((u32)config->reg & USB1_ADDR_MASK); 519 clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD); 520 udelay(25); 521 clrbits_le32(&usb1ctlr->utmip_bias_cfg1, 522 UTMIP_FORCE_PDTRK_POWERDOWN); 523 } 524 return 0; 525 } 526 527 #ifdef CONFIG_USB_ULPI 528 /* if board file does not set a ULPI reference frequency we default to 24MHz */ 529 #ifndef CONFIG_ULPI_REF_CLK 530 #define CONFIG_ULPI_REF_CLK 24000000 531 #endif 532 533 /* set up the ULPI USB controller with the parameters provided */ 534 static int init_ulpi_usb_controller(struct fdt_usb *config) 535 { 536 u32 val; 537 int loop_count; 538 struct ulpi_viewport ulpi_vp; 539 struct usb_ctlr *usbctlr = config->reg; 540 541 /* set up ULPI reference clock on pllp_out4 */ 542 clock_enable(PERIPH_ID_DEV2_OUT); 543 clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK); 544 545 /* reset ULPI phy */ 546 if (fdt_gpio_isvalid(&config->phy_reset_gpio)) { 547 fdtdec_setup_gpio(&config->phy_reset_gpio); 548 gpio_direction_output(config->phy_reset_gpio.gpio, 0); 549 mdelay(5); 550 gpio_set_value(config->phy_reset_gpio.gpio, 1); 551 } 552 553 /* Reset the usb controller */ 554 clock_enable(config->periph_id); 555 usbf_reset_controller(config, usbctlr); 556 557 /* enable pinmux bypass */ 558 setbits_le32(&usbctlr->ulpi_timing_ctrl_0, 559 ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); 560 561 /* Select ULPI parallel interface */ 562 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT); 563 564 /* enable ULPI transceiver */ 565 setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); 566 567 /* configure ULPI transceiver timings */ 568 val = 0; 569 writel(val, &usbctlr->ulpi_timing_ctrl_1); 570 571 val |= ULPI_DATA_TRIMMER_SEL(4); 572 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); 573 val |= ULPI_DIR_TRIMMER_SEL(4); 574 writel(val, &usbctlr->ulpi_timing_ctrl_1); 575 udelay(10); 576 577 val |= ULPI_DATA_TRIMMER_LOAD; 578 val |= ULPI_STPDIRNXT_TRIMMER_LOAD; 579 val |= ULPI_DIR_TRIMMER_LOAD; 580 writel(val, &usbctlr->ulpi_timing_ctrl_1); 581 582 /* set up phy for host operation with external vbus supply */ 583 ulpi_vp.port_num = 0; 584 ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport; 585 586 if (ulpi_init(&ulpi_vp)) { 587 printf("Tegra ULPI viewport init failed\n"); 588 return -1; 589 } 590 591 ulpi_set_vbus(&ulpi_vp, 1, 1); 592 ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0); 593 594 /* enable wakeup events */ 595 setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC); 596 597 /* Enable and wait for the phy clock to become valid in 100 ms */ 598 setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 599 for (loop_count = 100000; loop_count != 0; loop_count--) { 600 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 601 break; 602 udelay(1); 603 } 604 if (!loop_count) 605 return -1; 606 clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 607 608 return 0; 609 } 610 #else 611 static int init_ulpi_usb_controller(struct fdt_usb *config) 612 { 613 printf("No code to set up ULPI controller, please enable" 614 "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT"); 615 return -1; 616 } 617 #endif 618 619 static void config_clock(const u32 timing[]) 620 { 621 clock_start_pll(CLOCK_ID_USB, 622 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], 623 timing[PARAM_CPCON], timing[PARAM_LFCON]); 624 } 625 626 static int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config) 627 { 628 const char *phy, *mode; 629 630 config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg"); 631 mode = fdt_getprop(blob, node, "dr_mode", NULL); 632 if (mode) { 633 if (0 == strcmp(mode, "host")) 634 config->dr_mode = DR_MODE_HOST; 635 else if (0 == strcmp(mode, "peripheral")) 636 config->dr_mode = DR_MODE_DEVICE; 637 else if (0 == strcmp(mode, "otg")) 638 config->dr_mode = DR_MODE_OTG; 639 else { 640 debug("%s: Cannot decode dr_mode '%s'\n", __func__, 641 mode); 642 return -FDT_ERR_NOTFOUND; 643 } 644 } else { 645 config->dr_mode = DR_MODE_HOST; 646 } 647 648 phy = fdt_getprop(blob, node, "phy_type", NULL); 649 config->utmi = phy && 0 == strcmp("utmi", phy); 650 config->ulpi = phy && 0 == strcmp("ulpi", phy); 651 config->enabled = fdtdec_get_is_enabled(blob, node); 652 config->has_legacy_mode = fdtdec_get_bool(blob, node, 653 "nvidia,has-legacy-mode"); 654 if (config->has_legacy_mode) 655 port_addr_clear_csc = (u32) config->reg; 656 config->periph_id = clock_decode_periph_id(blob, node); 657 if (config->periph_id == PERIPH_ID_NONE) { 658 debug("%s: Missing/invalid peripheral ID\n", __func__); 659 return -FDT_ERR_NOTFOUND; 660 } 661 fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio); 662 fdtdec_decode_gpio(blob, node, "nvidia,phy-reset-gpio", 663 &config->phy_reset_gpio); 664 debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, " 665 "vbus=%d, phy_reset=%d, dr_mode=%d\n", 666 config->enabled, config->has_legacy_mode, config->utmi, 667 config->ulpi, config->periph_id, config->vbus_gpio.gpio, 668 config->phy_reset_gpio.gpio, config->dr_mode); 669 670 return 0; 671 } 672 673 /* 674 * process_usb_nodes() - Process a list of USB nodes, adding them to our list 675 * of USB ports. 676 * @blob: fdt blob 677 * @node_list: list of nodes to process (any <=0 are ignored) 678 * @count: number of nodes to process 679 * 680 * Return: 0 - ok, -1 - error 681 */ 682 static int process_usb_nodes(const void *blob, int node_list[], int count) 683 { 684 struct fdt_usb config; 685 int node, i; 686 int clk_done = 0; 687 688 port_count = 0; 689 for (i = 0; i < count; i++) { 690 if (port_count == USB_PORTS_MAX) { 691 printf("tegrausb: Cannot register more than %d ports\n", 692 USB_PORTS_MAX); 693 return -1; 694 } 695 696 debug("USB %d: ", i); 697 node = node_list[i]; 698 if (!node) 699 continue; 700 if (fdt_decode_usb(blob, node, &config)) { 701 debug("Cannot decode USB node %s\n", 702 fdt_get_name(blob, node, NULL)); 703 return -1; 704 } 705 if (!clk_done) { 706 config_clock(get_pll_timing()); 707 clk_done = 1; 708 } 709 config.initialized = 0; 710 711 /* add new USB port to the list of available ports */ 712 port[port_count++] = config; 713 } 714 715 return 0; 716 } 717 718 int board_usb_init(const void *blob) 719 { 720 int node_list[USB_PORTS_MAX]; 721 int count, err = 0; 722 int i; 723 724 for (i = 0; i < ARRAY_SIZE(fdt_usb_controllers); i++) { 725 controller = &fdt_usb_controllers[i]; 726 727 count = fdtdec_find_aliases_for_id(blob, "usb", 728 controller->compat, node_list, USB_PORTS_MAX); 729 if (count) { 730 err = process_usb_nodes(blob, node_list, count); 731 if (err) 732 printf("%s: Error processing USB node!\n", 733 __func__); 734 return err; 735 } 736 } 737 if (i == ARRAY_SIZE(fdt_usb_controllers)) 738 controller = NULL; 739 740 return err; 741 } 742 743 /** 744 * Start up the given port number (ports are numbered from 0 on each board). 745 * This returns values for the appropriate hccr and hcor addresses to use for 746 * USB EHCI operations. 747 * 748 * @param index port number to start 749 * @param hccr returns start address of EHCI HCCR registers 750 * @param hcor returns start address of EHCI HCOR registers 751 * @return 0 if ok, -1 on error (generally invalid port number) 752 */ 753 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) 754 { 755 struct fdt_usb *config; 756 struct usb_ctlr *usbctlr; 757 758 if (index >= port_count) 759 return -1; 760 761 config = &port[index]; 762 763 /* skip init, if the port is already initialized */ 764 if (config->initialized) 765 goto success; 766 767 if (config->utmi && init_utmi_usb_controller(config)) { 768 printf("tegrausb: Cannot init port %d\n", index); 769 return -1; 770 } 771 772 if (config->ulpi && init_ulpi_usb_controller(config)) { 773 printf("tegrausb: Cannot init port %d\n", index); 774 return -1; 775 } 776 777 set_host_mode(config); 778 779 config->initialized = 1; 780 781 success: 782 usbctlr = config->reg; 783 *hccr = (struct ehci_hccr *)&usbctlr->cap_length; 784 *hcor = (struct ehci_hcor *)&usbctlr->usb_cmd; 785 786 if (controller->has_hostpc) { 787 /* Set to Host mode after Controller Reset was done */ 788 clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, 789 USBMODE_CM_HC); 790 /* Select UTMI parallel interface after setting host mode */ 791 if (config->utmi) { 792 clrsetbits_le32((char *)&usbctlr->usb_cmd + 793 HOSTPC1_DEVLC, PTS_MASK, 794 PTS_UTMI << PTS_SHIFT); 795 clrbits_le32((char *)&usbctlr->usb_cmd + 796 HOSTPC1_DEVLC, STS); 797 } 798 } 799 return 0; 800 } 801 802 /* 803 * Bring down the specified USB controller 804 */ 805 int ehci_hcd_stop(int index) 806 { 807 struct usb_ctlr *usbctlr; 808 809 usbctlr = port[index].reg; 810 811 /* Stop controller */ 812 writel(0, &usbctlr->usb_cmd); 813 udelay(1000); 814 815 /* Initiate controller reset */ 816 writel(2, &usbctlr->usb_cmd); 817 udelay(1000); 818 819 port[index].initialized = 0; 820 821 return 0; 822 } 823