1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * Copyright (c) 2009-2015 NVIDIA Corporation 4 * Copyright (c) 2013 Lucas Stach 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <linux/errno.h> 12 #include <asm/io.h> 13 #include <asm-generic/gpio.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch-tegra/usb.h> 16 #include <asm/arch-tegra/clk_rst.h> 17 #include <usb.h> 18 #include <usb/ulpi.h> 19 #include <libfdt.h> 20 21 #include "ehci.h" 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #define USB1_ADDR_MASK 0xFFFF0000 26 27 #define HOSTPC1_DEVLC 0x84 28 #define HOSTPC1_PSPD(x) (((x) >> 25) & 0x3) 29 30 #ifdef CONFIG_USB_ULPI 31 #ifndef CONFIG_USB_ULPI_VIEWPORT 32 #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \ 33 define CONFIG_USB_ULPI_VIEWPORT" 34 #endif 35 #endif 36 37 /* Parameters we need for USB */ 38 enum { 39 PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ 40 PARAM_DIVM, /* PLL INPUT DIVIDER */ 41 PARAM_DIVP, /* POST DIVIDER (2^N) */ 42 PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ 43 PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ 44 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ 45 PARAM_STABLE_COUNT, /* PLL-U STABLE count */ 46 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ 47 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ 48 PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ 49 PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ 50 51 PARAM_COUNT 52 }; 53 54 /* Possible port types (dual role mode) */ 55 enum dr_mode { 56 DR_MODE_NONE = 0, 57 DR_MODE_HOST, /* supports host operation */ 58 DR_MODE_DEVICE, /* supports device operation */ 59 DR_MODE_OTG, /* supports both */ 60 }; 61 62 enum usb_ctlr_type { 63 USB_CTLR_T20, 64 USB_CTLR_T30, 65 USB_CTLR_T114, 66 USB_CTLR_T210, 67 68 USB_CTRL_COUNT, 69 }; 70 71 /* Information about a USB port */ 72 struct fdt_usb { 73 struct ehci_ctrl ehci; 74 struct usb_ctlr *reg; /* address of registers in physical memory */ 75 unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ 76 unsigned ulpi:1; /* 1 if port has external ULPI transceiver */ 77 unsigned enabled:1; /* 1 to enable, 0 to disable */ 78 unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ 79 enum usb_ctlr_type type; 80 enum usb_init_type init_type; 81 enum dr_mode dr_mode; /* dual role mode */ 82 enum periph_id periph_id;/* peripheral id */ 83 struct gpio_desc vbus_gpio; /* GPIO for vbus enable */ 84 struct gpio_desc phy_reset_gpio; /* GPIO to reset ULPI phy */ 85 }; 86 87 /* 88 * This table has USB timing parameters for each Oscillator frequency we 89 * support. There are four sets of values: 90 * 91 * 1. PLLU configuration information (reference clock is osc/clk_m and 92 * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). 93 * 94 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 95 * ---------------------------------------------------------------------- 96 * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) 97 * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) 98 * Filter frequency (MHz) 1 4.8 6 2 99 * CPCON 1100b 0011b 1100b 1100b 100 * LFCON0 0 0 0 0 101 * 102 * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: 103 * 104 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 105 * --------------------------------------------------------------------------- 106 * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) 107 * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) 108 * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) 109 * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) 110 * 111 * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and 112 * SessEnd. Each of these signals have their own debouncer and for each of 113 * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or 114 * BIAS_DEBOUNCE_B). 115 * 116 * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: 117 * 0xffff -> No debouncing at all 118 * <n> ms = <n> *1000 / (1/19.2MHz) / 4 119 * 120 * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: 121 * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 122 * 123 * We need to use only DebounceA for BOOTROM. We don't need the DebounceB 124 * values, so we can keep those to default. 125 * 126 * 4. The 20 microsecond delay after bias cell operation. 127 */ 128 static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 129 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 130 { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, 131 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, 132 { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, 133 { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }, 134 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 135 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 } 136 }; 137 138 static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 139 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 140 { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 }, 141 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 }, 142 { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 143 { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }, 144 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 145 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 } 146 }; 147 148 static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 149 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 150 { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 }, 151 { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 }, 152 { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 153 { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 11 }, 154 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, 155 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 } 156 }; 157 158 /* NOTE: 13/26MHz settings are N/A for T210, so dupe 12MHz settings for now */ 159 static const unsigned T210_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 160 /* DivN, DivM, DivP, KCP, KVCO, Delays Debounce, Bias */ 161 { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 32500, 5 }, 162 { 0x019, 0x01, 0x01, 0x0, 0, 0x03, 0x4B, 0x0C, 0xBB, 48000, 8 }, 163 { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 }, 164 { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 65000, 5 }, 165 { 0x019, 0x02, 0x01, 0x0, 0, 0x05, 0x96, 0x18, 0x177, 96000, 15 }, 166 { 0x028, 0x04, 0x01, 0x0, 0, 0x04, 0x66, 0x09, 0xFE, 120000, 20 } 167 }; 168 169 /* UTMIP Idle Wait Delay */ 170 static const u8 utmip_idle_wait_delay = 17; 171 172 /* UTMIP Elastic limit */ 173 static const u8 utmip_elastic_limit = 16; 174 175 /* UTMIP High Speed Sync Start Delay */ 176 static const u8 utmip_hs_sync_start_delay = 9; 177 178 struct fdt_usb_controller { 179 /* flag to determine whether controller supports hostpc register */ 180 u32 has_hostpc:1; 181 const unsigned *pll_parameter; 182 }; 183 184 static struct fdt_usb_controller fdt_usb_controllers[USB_CTRL_COUNT] = { 185 { 186 .has_hostpc = 0, 187 .pll_parameter = (const unsigned *)T20_usb_pll, 188 }, 189 { 190 .has_hostpc = 1, 191 .pll_parameter = (const unsigned *)T30_usb_pll, 192 }, 193 { 194 .has_hostpc = 1, 195 .pll_parameter = (const unsigned *)T114_usb_pll, 196 }, 197 { 198 .has_hostpc = 1, 199 .pll_parameter = (const unsigned *)T210_usb_pll, 200 }, 201 }; 202 203 /* 204 * A known hardware issue where Connect Status Change bit of PORTSC register 205 * of USB1 controller will be set after Port Reset. 206 * We have to clear it in order for later device enumeration to proceed. 207 */ 208 static void tegra_ehci_powerup_fixup(struct ehci_ctrl *ctrl, 209 uint32_t *status_reg, uint32_t *reg) 210 { 211 struct fdt_usb *config = ctrl->priv; 212 struct fdt_usb_controller *controller; 213 214 controller = &fdt_usb_controllers[config->type]; 215 mdelay(50); 216 /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */ 217 if (controller->has_hostpc) 218 *reg |= EHCI_PS_PE; 219 220 if (!config->has_legacy_mode) 221 return; 222 /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */ 223 if (ehci_readl(status_reg) & EHCI_PS_CSC) 224 *reg |= EHCI_PS_CSC; 225 } 226 227 static void tegra_ehci_set_usbmode(struct ehci_ctrl *ctrl) 228 { 229 struct fdt_usb *config = ctrl->priv; 230 struct usb_ctlr *usbctlr; 231 uint32_t tmp; 232 233 usbctlr = config->reg; 234 235 tmp = ehci_readl(&usbctlr->usb_mode); 236 tmp |= USBMODE_CM_HC; 237 ehci_writel(&usbctlr->usb_mode, tmp); 238 } 239 240 static int tegra_ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg) 241 { 242 struct fdt_usb *config = ctrl->priv; 243 struct fdt_usb_controller *controller; 244 uint32_t tmp; 245 uint32_t *reg_ptr; 246 247 controller = &fdt_usb_controllers[config->type]; 248 if (controller->has_hostpc) { 249 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + 250 HOSTPC1_DEVLC); 251 tmp = ehci_readl(reg_ptr); 252 return HOSTPC1_PSPD(tmp); 253 } else 254 return PORTSC_PSPD(reg); 255 } 256 257 /* Set up VBUS for host/device mode */ 258 static void set_up_vbus(struct fdt_usb *config, enum usb_init_type init) 259 { 260 /* 261 * If we are an OTG port initializing in host mode, 262 * check if remote host is driving VBus and bail out in this case. 263 */ 264 if (init == USB_INIT_HOST && 265 config->dr_mode == DR_MODE_OTG && 266 (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) { 267 printf("tegrausb: VBUS input active; not enabling as host\n"); 268 return; 269 } 270 271 if (dm_gpio_is_valid(&config->vbus_gpio)) { 272 int vbus_value; 273 274 vbus_value = (init == USB_INIT_HOST); 275 dm_gpio_set_value(&config->vbus_gpio, vbus_value); 276 277 debug("set_up_vbus: GPIO %d %d\n", 278 gpio_get_number(&config->vbus_gpio), vbus_value); 279 } 280 } 281 282 static void usbf_reset_controller(struct fdt_usb *config, 283 struct usb_ctlr *usbctlr) 284 { 285 /* Reset the USB controller with 2us delay */ 286 reset_periph(config->periph_id, 2); 287 288 /* 289 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under 290 * base address 291 */ 292 if (config->has_legacy_mode) 293 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); 294 295 /* Put UTMIP1/3 in reset */ 296 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 297 298 /* Enable the UTMIP PHY */ 299 if (config->utmi) 300 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); 301 } 302 303 static const unsigned *get_pll_timing(struct fdt_usb_controller *controller) 304 { 305 const unsigned *timing; 306 307 timing = controller->pll_parameter + 308 clock_get_osc_freq() * PARAM_COUNT; 309 310 return timing; 311 } 312 313 /* select the PHY to use with a USB controller */ 314 static void init_phy_mux(struct fdt_usb *config, uint pts, 315 enum usb_init_type init) 316 { 317 struct usb_ctlr *usbctlr = config->reg; 318 319 #if defined(CONFIG_TEGRA20) 320 if (config->periph_id == PERIPH_ID_USBD) { 321 clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, 322 pts << PTS1_SHIFT); 323 clrbits_le32(&usbctlr->port_sc1, STS1); 324 } else { 325 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, 326 pts << PTS_SHIFT); 327 clrbits_le32(&usbctlr->port_sc1, STS); 328 } 329 #else 330 /* Set to Host mode (if applicable) after Controller Reset was done */ 331 clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, 332 (init == USB_INIT_HOST) ? USBMODE_CM_HC : 0); 333 /* 334 * Select PHY interface after setting host mode. 335 * For device mode, the ordering requirement is not an issue, since 336 * only the first USB controller supports device mode, and that USB 337 * controller can only talk to a UTMI PHY, so the PHY selection is 338 * already made at reset time, so this write is a no-op. 339 */ 340 clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, 341 pts << PTS_SHIFT); 342 clrbits_le32(&usbctlr->hostpc1_devlc, STS); 343 #endif 344 } 345 346 /* set up the UTMI USB controller with the parameters provided */ 347 static int init_utmi_usb_controller(struct fdt_usb *config, 348 enum usb_init_type init) 349 { 350 struct fdt_usb_controller *controller; 351 u32 b_sess_valid_mask, val; 352 int loop_count; 353 const unsigned *timing; 354 struct usb_ctlr *usbctlr = config->reg; 355 struct clk_rst_ctlr *clkrst; 356 struct usb_ctlr *usb1ctlr; 357 358 clock_enable(config->periph_id); 359 360 /* Reset the usb controller */ 361 usbf_reset_controller(config, usbctlr); 362 363 /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ 364 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 365 366 /* Follow the crystal clock disable by >100ns delay */ 367 udelay(1); 368 369 b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN); 370 clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask, 371 (init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0); 372 373 /* 374 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP 375 * mux must be switched to actually use a_sess_vld threshold. 376 */ 377 if (config->dr_mode == DR_MODE_OTG && 378 dm_gpio_is_valid(&config->vbus_gpio)) 379 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, 380 VBUS_SENSE_CTL_MASK, 381 VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); 382 383 controller = &fdt_usb_controllers[config->type]; 384 debug("controller=%p, type=%d\n", controller, config->type); 385 386 /* 387 * PLL Delay CONFIGURATION settings. The following parameters control 388 * the bring up of the plls. 389 */ 390 timing = get_pll_timing(controller); 391 392 if (!controller->has_hostpc) { 393 val = readl(&usbctlr->utmip_misc_cfg1); 394 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 395 timing[PARAM_STABLE_COUNT] << 396 UTMIP_PLLU_STABLE_COUNT_SHIFT); 397 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 398 timing[PARAM_ACTIVE_DELAY_COUNT] << 399 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 400 writel(val, &usbctlr->utmip_misc_cfg1); 401 402 /* Set PLL enable delay count and crystal frequency count */ 403 val = readl(&usbctlr->utmip_pll_cfg1); 404 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 405 timing[PARAM_ENABLE_DELAY_COUNT] << 406 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 407 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 408 timing[PARAM_XTAL_FREQ_COUNT] << 409 UTMIP_XTAL_FREQ_COUNT_SHIFT); 410 writel(val, &usbctlr->utmip_pll_cfg1); 411 } else { 412 clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 413 414 val = readl(&clkrst->crc_utmip_pll_cfg2); 415 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 416 timing[PARAM_STABLE_COUNT] << 417 UTMIP_PLLU_STABLE_COUNT_SHIFT); 418 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 419 timing[PARAM_ACTIVE_DELAY_COUNT] << 420 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 421 writel(val, &clkrst->crc_utmip_pll_cfg2); 422 423 /* Set PLL enable delay count and crystal frequency count */ 424 val = readl(&clkrst->crc_utmip_pll_cfg1); 425 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 426 timing[PARAM_ENABLE_DELAY_COUNT] << 427 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 428 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 429 timing[PARAM_XTAL_FREQ_COUNT] << 430 UTMIP_XTAL_FREQ_COUNT_SHIFT); 431 writel(val, &clkrst->crc_utmip_pll_cfg1); 432 433 /* Disable Power Down state for PLL */ 434 clrbits_le32(&clkrst->crc_utmip_pll_cfg1, 435 PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN | 436 PLL_ACTIVE_POWERDOWN); 437 438 /* Recommended PHY settings for EYE diagram */ 439 val = readl(&usbctlr->utmip_xcvr_cfg0); 440 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK, 441 0x4 << UTMIP_XCVR_SETUP_SHIFT); 442 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK, 443 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT); 444 clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK, 445 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT); 446 writel(val, &usbctlr->utmip_xcvr_cfg0); 447 clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1, 448 UTMIP_XCVR_TERM_RANGE_ADJ_MASK, 449 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT); 450 451 /* Some registers can be controlled from USB1 only. */ 452 if (config->periph_id != PERIPH_ID_USBD) { 453 clock_enable(PERIPH_ID_USBD); 454 /* Disable Reset if in Reset state */ 455 reset_set_enable(PERIPH_ID_USBD, 0); 456 } 457 usb1ctlr = (struct usb_ctlr *) 458 ((unsigned long)config->reg & USB1_ADDR_MASK); 459 val = readl(&usb1ctlr->utmip_bias_cfg0); 460 setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB); 461 clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK, 462 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT); 463 clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK, 464 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT); 465 writel(val, &usb1ctlr->utmip_bias_cfg0); 466 467 /* Miscellaneous setting mentioned in Programming Guide */ 468 clrbits_le32(&usbctlr->utmip_misc_cfg0, 469 UTMIP_SUSPEND_EXIT_ON_EDGE); 470 } 471 472 /* Setting the tracking length time */ 473 clrsetbits_le32(&usbctlr->utmip_bias_cfg1, 474 UTMIP_BIAS_PDTRK_COUNT_MASK, 475 timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); 476 477 /* Program debounce time for VBUS to become valid */ 478 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, 479 UTMIP_DEBOUNCE_CFG0_MASK, 480 timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); 481 482 if (timing[PARAM_DEBOUNCE_A_TIME] > 0xFFFF) { 483 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, 484 UTMIP_DEBOUNCE_CFG0_MASK, 485 (timing[PARAM_DEBOUNCE_A_TIME] >> 1) 486 << UTMIP_DEBOUNCE_CFG0_SHIFT); 487 clrsetbits_le32(&usbctlr->utmip_bias_cfg1, 488 UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK, 489 1 << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT); 490 } 491 492 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); 493 494 /* Disable battery charge enabling bit */ 495 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); 496 497 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); 498 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); 499 500 /* 501 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT 502 * Setting these fields, together with default values of the 503 * other fields, results in programming the registers below as 504 * follows: 505 * UTMIP_HSRX_CFG0 = 0x9168c000 506 * UTMIP_HSRX_CFG1 = 0x13 507 */ 508 509 /* Set PLL enable delay count and Crystal frequency count */ 510 val = readl(&usbctlr->utmip_hsrx_cfg0); 511 clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, 512 utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); 513 clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, 514 utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); 515 writel(val, &usbctlr->utmip_hsrx_cfg0); 516 517 /* Configure the UTMIP_HS_SYNC_START_DLY */ 518 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, 519 UTMIP_HS_SYNC_START_DLY_MASK, 520 utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); 521 522 /* Preceed the crystal clock disable by >100ns delay. */ 523 udelay(1); 524 525 /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ 526 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 527 528 if (controller->has_hostpc) { 529 if (config->periph_id == PERIPH_ID_USBD) 530 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 531 UTMIP_FORCE_PD_SAMP_A_POWERDOWN); 532 if (config->periph_id == PERIPH_ID_USB2) 533 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 534 UTMIP_FORCE_PD_SAMP_B_POWERDOWN); 535 if (config->periph_id == PERIPH_ID_USB3) 536 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 537 UTMIP_FORCE_PD_SAMP_C_POWERDOWN); 538 } 539 /* Finished the per-controller init. */ 540 541 /* De-assert UTMIP_RESET to bring out of reset. */ 542 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 543 544 /* Wait for the phy clock to become valid in 100 ms */ 545 for (loop_count = 100000; loop_count != 0; loop_count--) { 546 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 547 break; 548 udelay(1); 549 } 550 if (!loop_count) 551 return -ETIMEDOUT; 552 553 /* Disable ICUSB FS/LS transceiver */ 554 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); 555 556 /* Select UTMI parallel interface */ 557 init_phy_mux(config, PTS_UTMI, init); 558 559 /* Deassert power down state */ 560 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | 561 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); 562 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | 563 UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); 564 565 if (controller->has_hostpc) { 566 /* 567 * BIAS Pad Power Down is common among all 3 USB 568 * controllers and can be controlled from USB1 only. 569 */ 570 usb1ctlr = (struct usb_ctlr *) 571 ((unsigned long)config->reg & USB1_ADDR_MASK); 572 clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD); 573 udelay(25); 574 clrbits_le32(&usb1ctlr->utmip_bias_cfg1, 575 UTMIP_FORCE_PDTRK_POWERDOWN); 576 } 577 return 0; 578 } 579 580 #ifdef CONFIG_USB_ULPI 581 /* if board file does not set a ULPI reference frequency we default to 24MHz */ 582 #ifndef CONFIG_ULPI_REF_CLK 583 #define CONFIG_ULPI_REF_CLK 24000000 584 #endif 585 586 /* set up the ULPI USB controller with the parameters provided */ 587 static int init_ulpi_usb_controller(struct fdt_usb *config, 588 enum usb_init_type init) 589 { 590 u32 val; 591 int loop_count; 592 struct ulpi_viewport ulpi_vp; 593 struct usb_ctlr *usbctlr = config->reg; 594 int ret; 595 596 /* set up ULPI reference clock on pllp_out4 */ 597 clock_enable(PERIPH_ID_DEV2_OUT); 598 clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK); 599 600 /* reset ULPI phy */ 601 if (dm_gpio_is_valid(&config->phy_reset_gpio)) { 602 /* 603 * This GPIO is typically active-low, and marked as such in 604 * device tree. dm_gpio_set_value() takes this into account 605 * and inverts the value we pass here if required. In other 606 * words, this first call logically asserts the reset signal, 607 * which typically results in driving the physical GPIO low, 608 * and the second call logically de-asserts the reset signal, 609 * which typically results in driver the GPIO high. 610 */ 611 dm_gpio_set_value(&config->phy_reset_gpio, 1); 612 mdelay(5); 613 dm_gpio_set_value(&config->phy_reset_gpio, 0); 614 } 615 616 /* Reset the usb controller */ 617 clock_enable(config->periph_id); 618 usbf_reset_controller(config, usbctlr); 619 620 /* enable pinmux bypass */ 621 setbits_le32(&usbctlr->ulpi_timing_ctrl_0, 622 ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); 623 624 /* Select ULPI parallel interface */ 625 init_phy_mux(config, PTS_ULPI, init); 626 627 /* enable ULPI transceiver */ 628 setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); 629 630 /* configure ULPI transceiver timings */ 631 val = 0; 632 writel(val, &usbctlr->ulpi_timing_ctrl_1); 633 634 val |= ULPI_DATA_TRIMMER_SEL(4); 635 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); 636 val |= ULPI_DIR_TRIMMER_SEL(4); 637 writel(val, &usbctlr->ulpi_timing_ctrl_1); 638 udelay(10); 639 640 val |= ULPI_DATA_TRIMMER_LOAD; 641 val |= ULPI_STPDIRNXT_TRIMMER_LOAD; 642 val |= ULPI_DIR_TRIMMER_LOAD; 643 writel(val, &usbctlr->ulpi_timing_ctrl_1); 644 645 /* set up phy for host operation with external vbus supply */ 646 ulpi_vp.port_num = 0; 647 ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport; 648 649 ret = ulpi_init(&ulpi_vp); 650 if (ret) { 651 printf("Tegra ULPI viewport init failed\n"); 652 return ret; 653 } 654 655 ulpi_set_vbus(&ulpi_vp, 1, 1); 656 ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0); 657 658 /* enable wakeup events */ 659 setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC); 660 661 /* Enable and wait for the phy clock to become valid in 100 ms */ 662 setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 663 for (loop_count = 100000; loop_count != 0; loop_count--) { 664 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 665 break; 666 udelay(1); 667 } 668 if (!loop_count) 669 return -ETIMEDOUT; 670 clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 671 672 return 0; 673 } 674 #else 675 static int init_ulpi_usb_controller(struct fdt_usb *config, 676 enum usb_init_type init) 677 { 678 printf("No code to set up ULPI controller, please enable" 679 "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT"); 680 return -ENOSYS; 681 } 682 #endif 683 684 static void config_clock(const u32 timing[]) 685 { 686 debug("%s: DIVM = %d, DIVN = %d, DIVP = %d, cpcon/lfcon = %d/%d\n", 687 __func__, timing[PARAM_DIVM], timing[PARAM_DIVN], 688 timing[PARAM_DIVP], timing[PARAM_CPCON], timing[PARAM_LFCON]); 689 690 clock_start_pll(CLOCK_ID_USB, 691 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], 692 timing[PARAM_CPCON], timing[PARAM_LFCON]); 693 } 694 695 static int fdt_decode_usb(struct udevice *dev, struct fdt_usb *config) 696 { 697 const char *phy, *mode; 698 699 config->reg = (struct usb_ctlr *)dev_read_addr(dev); 700 debug("reg=%p\n", config->reg); 701 mode = dev_read_string(dev, "dr_mode"); 702 if (mode) { 703 if (0 == strcmp(mode, "host")) 704 config->dr_mode = DR_MODE_HOST; 705 else if (0 == strcmp(mode, "peripheral")) 706 config->dr_mode = DR_MODE_DEVICE; 707 else if (0 == strcmp(mode, "otg")) 708 config->dr_mode = DR_MODE_OTG; 709 else { 710 debug("%s: Cannot decode dr_mode '%s'\n", __func__, 711 mode); 712 return -EINVAL; 713 } 714 } else { 715 config->dr_mode = DR_MODE_HOST; 716 } 717 718 phy = dev_read_string(dev, "phy_type"); 719 config->utmi = phy && 0 == strcmp("utmi", phy); 720 config->ulpi = phy && 0 == strcmp("ulpi", phy); 721 config->has_legacy_mode = dev_read_bool(dev, "nvidia,has-legacy-mode"); 722 config->periph_id = clock_decode_periph_id(dev); 723 if (config->periph_id == PERIPH_ID_NONE) { 724 debug("%s: Missing/invalid peripheral ID\n", __func__); 725 return -EINVAL; 726 } 727 gpio_request_by_name(dev, "nvidia,vbus-gpio", 0, &config->vbus_gpio, 728 GPIOD_IS_OUT); 729 gpio_request_by_name(dev, "nvidia,phy-reset-gpio", 0, 730 &config->phy_reset_gpio, GPIOD_IS_OUT); 731 debug("legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, vbus=%d, phy_reset=%d, dr_mode=%d, reg=%p\n", 732 config->has_legacy_mode, config->utmi, config->ulpi, 733 config->periph_id, gpio_get_number(&config->vbus_gpio), 734 gpio_get_number(&config->phy_reset_gpio), config->dr_mode, 735 config->reg); 736 737 return 0; 738 } 739 740 int usb_common_init(struct fdt_usb *config, enum usb_init_type init) 741 { 742 int ret = 0; 743 744 switch (init) { 745 case USB_INIT_HOST: 746 switch (config->dr_mode) { 747 case DR_MODE_HOST: 748 case DR_MODE_OTG: 749 break; 750 default: 751 printf("tegrausb: Invalid dr_mode %d for host mode\n", 752 config->dr_mode); 753 return -1; 754 } 755 break; 756 case USB_INIT_DEVICE: 757 if (config->periph_id != PERIPH_ID_USBD) { 758 printf("tegrausb: Device mode only supported on first USB controller\n"); 759 return -1; 760 } 761 if (!config->utmi) { 762 printf("tegrausb: Device mode only supported with UTMI PHY\n"); 763 return -1; 764 } 765 switch (config->dr_mode) { 766 case DR_MODE_DEVICE: 767 case DR_MODE_OTG: 768 break; 769 default: 770 printf("tegrausb: Invalid dr_mode %d for device mode\n", 771 config->dr_mode); 772 return -1; 773 } 774 break; 775 default: 776 printf("tegrausb: Unknown USB_INIT_* %d\n", init); 777 return -1; 778 } 779 780 debug("%d, %d\n", config->utmi, config->ulpi); 781 if (config->utmi) 782 ret = init_utmi_usb_controller(config, init); 783 else if (config->ulpi) 784 ret = init_ulpi_usb_controller(config, init); 785 if (ret) 786 return ret; 787 788 set_up_vbus(config, init); 789 790 config->init_type = init; 791 792 return 0; 793 } 794 795 void usb_common_uninit(struct fdt_usb *priv) 796 { 797 struct usb_ctlr *usbctlr; 798 799 usbctlr = priv->reg; 800 801 /* Stop controller */ 802 writel(0, &usbctlr->usb_cmd); 803 udelay(1000); 804 805 /* Initiate controller reset */ 806 writel(2, &usbctlr->usb_cmd); 807 udelay(1000); 808 } 809 810 static const struct ehci_ops tegra_ehci_ops = { 811 .set_usb_mode = tegra_ehci_set_usbmode, 812 .get_port_speed = tegra_ehci_get_port_speed, 813 .powerup_fixup = tegra_ehci_powerup_fixup, 814 }; 815 816 static int ehci_usb_ofdata_to_platdata(struct udevice *dev) 817 { 818 struct fdt_usb *priv = dev_get_priv(dev); 819 int ret; 820 821 ret = fdt_decode_usb(dev, priv); 822 if (ret) 823 return ret; 824 825 priv->type = dev_get_driver_data(dev); 826 827 return 0; 828 } 829 830 static int ehci_usb_probe(struct udevice *dev) 831 { 832 struct usb_platdata *plat = dev_get_platdata(dev); 833 struct fdt_usb *priv = dev_get_priv(dev); 834 struct ehci_hccr *hccr; 835 struct ehci_hcor *hcor; 836 static bool clk_done; 837 int ret; 838 839 ret = usb_common_init(priv, plat->init_type); 840 if (ret) 841 return ret; 842 hccr = (struct ehci_hccr *)&priv->reg->cap_length; 843 hcor = (struct ehci_hcor *)&priv->reg->usb_cmd; 844 if (!clk_done) { 845 config_clock(get_pll_timing(&fdt_usb_controllers[priv->type])); 846 clk_done = true; 847 } 848 849 return ehci_register(dev, hccr, hcor, &tegra_ehci_ops, 0, 850 plat->init_type); 851 } 852 853 static const struct udevice_id ehci_usb_ids[] = { 854 { .compatible = "nvidia,tegra20-ehci", .data = USB_CTLR_T20 }, 855 { .compatible = "nvidia,tegra30-ehci", .data = USB_CTLR_T30 }, 856 { .compatible = "nvidia,tegra114-ehci", .data = USB_CTLR_T114 }, 857 { .compatible = "nvidia,tegra210-ehci", .data = USB_CTLR_T210 }, 858 { } 859 }; 860 861 U_BOOT_DRIVER(usb_ehci) = { 862 .name = "ehci_tegra", 863 .id = UCLASS_USB, 864 .of_match = ehci_usb_ids, 865 .ofdata_to_platdata = ehci_usb_ofdata_to_platdata, 866 .probe = ehci_usb_probe, 867 .remove = ehci_deregister, 868 .ops = &ehci_usb_ops, 869 .platdata_auto_alloc_size = sizeof(struct usb_platdata), 870 .priv_auto_alloc_size = sizeof(struct fdt_usb), 871 .flags = DM_FLAG_ALLOC_PRIV_DMA, 872 }; 873