1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * Copyright (c) 2009-2013 NVIDIA Corporation 4 * Copyright (c) 2013 Lucas Stach 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/errno.h> 11 #include <asm/io.h> 12 #include <asm-generic/gpio.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch-tegra/usb.h> 15 #include <asm/arch-tegra/clk_rst.h> 16 #include <asm/arch/usb.h> 17 #include <usb.h> 18 #include <usb/ulpi.h> 19 #include <libfdt.h> 20 #include <fdtdec.h> 21 22 #include "ehci.h" 23 24 #define USB1_ADDR_MASK 0xFFFF0000 25 26 #define HOSTPC1_DEVLC 0x84 27 #define HOSTPC1_PSPD(x) (((x) >> 25) & 0x3) 28 29 #ifdef CONFIG_USB_ULPI 30 #ifndef CONFIG_USB_ULPI_VIEWPORT 31 #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \ 32 define CONFIG_USB_ULPI_VIEWPORT" 33 #endif 34 #endif 35 36 enum { 37 USB_PORTS_MAX = 3, /* Maximum ports we allow */ 38 }; 39 40 /* Parameters we need for USB */ 41 enum { 42 PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ 43 PARAM_DIVM, /* PLL INPUT DIVIDER */ 44 PARAM_DIVP, /* POST DIVIDER (2^N) */ 45 PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ 46 PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ 47 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ 48 PARAM_STABLE_COUNT, /* PLL-U STABLE count */ 49 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ 50 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ 51 PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ 52 PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ 53 54 PARAM_COUNT 55 }; 56 57 /* Possible port types (dual role mode) */ 58 enum dr_mode { 59 DR_MODE_NONE = 0, 60 DR_MODE_HOST, /* supports host operation */ 61 DR_MODE_DEVICE, /* supports device operation */ 62 DR_MODE_OTG, /* supports both */ 63 }; 64 65 /* Information about a USB port */ 66 struct fdt_usb { 67 struct usb_ctlr *reg; /* address of registers in physical memory */ 68 unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ 69 unsigned ulpi:1; /* 1 if port has external ULPI transceiver */ 70 unsigned enabled:1; /* 1 to enable, 0 to disable */ 71 unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ 72 unsigned initialized:1; /* has this port already been initialized? */ 73 enum dr_mode dr_mode; /* dual role mode */ 74 enum periph_id periph_id;/* peripheral id */ 75 struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */ 76 struct fdt_gpio_state phy_reset_gpio; /* GPIO to reset ULPI phy */ 77 }; 78 79 static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */ 80 static unsigned port_count; /* Number of available ports */ 81 /* Port that needs to clear CSC after Port Reset */ 82 static u32 port_addr_clear_csc; 83 84 /* 85 * This table has USB timing parameters for each Oscillator frequency we 86 * support. There are four sets of values: 87 * 88 * 1. PLLU configuration information (reference clock is osc/clk_m and 89 * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). 90 * 91 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 92 * ---------------------------------------------------------------------- 93 * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) 94 * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) 95 * Filter frequency (MHz) 1 4.8 6 2 96 * CPCON 1100b 0011b 1100b 1100b 97 * LFCON0 0 0 0 0 98 * 99 * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: 100 * 101 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 102 * --------------------------------------------------------------------------- 103 * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) 104 * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) 105 * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) 106 * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) 107 * 108 * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and 109 * SessEnd. Each of these signals have their own debouncer and for each of 110 * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or 111 * BIAS_DEBOUNCE_B). 112 * 113 * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: 114 * 0xffff -> No debouncing at all 115 * <n> ms = <n> *1000 / (1/19.2MHz) / 4 116 * 117 * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: 118 * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 119 * 120 * We need to use only DebounceA for BOOTROM. We don't need the DebounceB 121 * values, so we can keep those to default. 122 * 123 * 4. The 20 microsecond delay after bias cell operation. 124 */ 125 static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 126 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 127 { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, 128 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, 129 { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, 130 { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 131 }; 132 133 static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 134 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 135 { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 }, 136 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 }, 137 { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 138 { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 139 }; 140 141 static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 142 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 143 { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 }, 144 { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 }, 145 { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 146 { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB } 147 }; 148 149 /* UTMIP Idle Wait Delay */ 150 static const u8 utmip_idle_wait_delay = 17; 151 152 /* UTMIP Elastic limit */ 153 static const u8 utmip_elastic_limit = 16; 154 155 /* UTMIP High Speed Sync Start Delay */ 156 static const u8 utmip_hs_sync_start_delay = 9; 157 158 struct fdt_usb_controller { 159 int compat; 160 /* flag to determine whether controller supports hostpc register */ 161 u32 has_hostpc:1; 162 const unsigned *pll_parameter; 163 }; 164 165 static struct fdt_usb_controller fdt_usb_controllers[] = { 166 { 167 .compat = COMPAT_NVIDIA_TEGRA20_USB, 168 .has_hostpc = 0, 169 .pll_parameter = (const unsigned *)T20_usb_pll, 170 }, 171 { 172 .compat = COMPAT_NVIDIA_TEGRA30_USB, 173 .has_hostpc = 1, 174 .pll_parameter = (const unsigned *)T30_usb_pll, 175 }, 176 { 177 .compat = COMPAT_NVIDIA_TEGRA114_USB, 178 .has_hostpc = 1, 179 .pll_parameter = (const unsigned *)T114_usb_pll, 180 }, 181 }; 182 183 static struct fdt_usb_controller *controller; 184 185 /* 186 * A known hardware issue where Connect Status Change bit of PORTSC register 187 * of USB1 controller will be set after Port Reset. 188 * We have to clear it in order for later device enumeration to proceed. 189 * This ehci_powerup_fixup overrides the weak function ehci_powerup_fixup 190 * in "ehci-hcd.c". 191 */ 192 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) 193 { 194 mdelay(50); 195 /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */ 196 if (controller->has_hostpc) 197 *reg |= EHCI_PS_PE; 198 199 if (((u32)status_reg & TEGRA_USB_ADDR_MASK) != port_addr_clear_csc) 200 return; 201 /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */ 202 if (ehci_readl(status_reg) & EHCI_PS_CSC) 203 *reg |= EHCI_PS_CSC; 204 } 205 206 /* 207 * This ehci_set_usbmode overrides the weak function ehci_set_usbmode 208 * in "ehci-hcd.c". 209 */ 210 void ehci_set_usbmode(int index) 211 { 212 struct fdt_usb *config; 213 struct usb_ctlr *usbctlr; 214 uint32_t tmp; 215 216 config = &port[index]; 217 usbctlr = config->reg; 218 219 tmp = ehci_readl(&usbctlr->usb_mode); 220 tmp |= USBMODE_CM_HC; 221 ehci_writel(&usbctlr->usb_mode, tmp); 222 } 223 224 /* 225 * This ehci_get_port_speed overrides the weak function ehci_get_port_speed 226 * in "ehci-hcd.c". 227 */ 228 int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg) 229 { 230 uint32_t tmp; 231 uint32_t *reg_ptr; 232 233 if (controller->has_hostpc) { 234 reg_ptr = (uint32_t *)((u8 *)&hcor->or_usbcmd + HOSTPC1_DEVLC); 235 tmp = ehci_readl(reg_ptr); 236 return HOSTPC1_PSPD(tmp); 237 } else 238 return PORTSC_PSPD(reg); 239 } 240 241 /* Put the port into host mode */ 242 static void set_host_mode(struct fdt_usb *config) 243 { 244 /* 245 * If we are an OTG port, check if remote host is driving VBus and 246 * bail out in this case. 247 */ 248 if (config->dr_mode == DR_MODE_OTG && 249 (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) 250 return; 251 252 /* 253 * If not driving, we set the GPIO to enable VBUS. We assume 254 * that the pinmux is set up correctly for this. 255 */ 256 if (fdt_gpio_isvalid(&config->vbus_gpio)) { 257 fdtdec_setup_gpio(&config->vbus_gpio); 258 gpio_direction_output(config->vbus_gpio.gpio, 259 (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? 260 0 : 1); 261 debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio, 262 (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? 263 "low" : "high"); 264 } 265 } 266 267 void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr) 268 { 269 /* Reset the USB controller with 2us delay */ 270 reset_periph(config->periph_id, 2); 271 272 /* 273 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under 274 * base address 275 */ 276 if (config->has_legacy_mode) 277 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); 278 279 /* Put UTMIP1/3 in reset */ 280 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 281 282 /* Enable the UTMIP PHY */ 283 if (config->utmi) 284 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); 285 } 286 287 static const unsigned *get_pll_timing(void) 288 { 289 const unsigned *timing; 290 291 timing = controller->pll_parameter + 292 clock_get_osc_freq() * PARAM_COUNT; 293 294 return timing; 295 } 296 297 /* set up the UTMI USB controller with the parameters provided */ 298 static int init_utmi_usb_controller(struct fdt_usb *config) 299 { 300 u32 val; 301 int loop_count; 302 const unsigned *timing; 303 struct usb_ctlr *usbctlr = config->reg; 304 struct clk_rst_ctlr *clkrst; 305 struct usb_ctlr *usb1ctlr; 306 307 clock_enable(config->periph_id); 308 309 /* Reset the usb controller */ 310 usbf_reset_controller(config, usbctlr); 311 312 /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ 313 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 314 315 /* Follow the crystal clock disable by >100ns delay */ 316 udelay(1); 317 318 /* 319 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP 320 * mux must be switched to actually use a_sess_vld threshold. 321 */ 322 if (config->dr_mode == DR_MODE_OTG && 323 fdt_gpio_isvalid(&config->vbus_gpio)) 324 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, 325 VBUS_SENSE_CTL_MASK, 326 VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); 327 328 /* 329 * PLL Delay CONFIGURATION settings. The following parameters control 330 * the bring up of the plls. 331 */ 332 timing = get_pll_timing(); 333 334 if (!controller->has_hostpc) { 335 val = readl(&usbctlr->utmip_misc_cfg1); 336 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 337 timing[PARAM_STABLE_COUNT] << 338 UTMIP_PLLU_STABLE_COUNT_SHIFT); 339 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 340 timing[PARAM_ACTIVE_DELAY_COUNT] << 341 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 342 writel(val, &usbctlr->utmip_misc_cfg1); 343 344 /* Set PLL enable delay count and crystal frequency count */ 345 val = readl(&usbctlr->utmip_pll_cfg1); 346 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 347 timing[PARAM_ENABLE_DELAY_COUNT] << 348 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 349 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 350 timing[PARAM_XTAL_FREQ_COUNT] << 351 UTMIP_XTAL_FREQ_COUNT_SHIFT); 352 writel(val, &usbctlr->utmip_pll_cfg1); 353 } else { 354 clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 355 356 val = readl(&clkrst->crc_utmip_pll_cfg2); 357 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 358 timing[PARAM_STABLE_COUNT] << 359 UTMIP_PLLU_STABLE_COUNT_SHIFT); 360 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 361 timing[PARAM_ACTIVE_DELAY_COUNT] << 362 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 363 writel(val, &clkrst->crc_utmip_pll_cfg2); 364 365 /* Set PLL enable delay count and crystal frequency count */ 366 val = readl(&clkrst->crc_utmip_pll_cfg1); 367 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 368 timing[PARAM_ENABLE_DELAY_COUNT] << 369 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 370 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 371 timing[PARAM_XTAL_FREQ_COUNT] << 372 UTMIP_XTAL_FREQ_COUNT_SHIFT); 373 writel(val, &clkrst->crc_utmip_pll_cfg1); 374 375 /* Disable Power Down state for PLL */ 376 clrbits_le32(&clkrst->crc_utmip_pll_cfg1, 377 PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN | 378 PLL_ACTIVE_POWERDOWN); 379 380 /* Recommended PHY settings for EYE diagram */ 381 val = readl(&usbctlr->utmip_xcvr_cfg0); 382 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK, 383 0x4 << UTMIP_XCVR_SETUP_SHIFT); 384 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK, 385 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT); 386 clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK, 387 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT); 388 writel(val, &usbctlr->utmip_xcvr_cfg0); 389 clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1, 390 UTMIP_XCVR_TERM_RANGE_ADJ_MASK, 391 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT); 392 393 /* Some registers can be controlled from USB1 only. */ 394 if (config->periph_id != PERIPH_ID_USBD) { 395 clock_enable(PERIPH_ID_USBD); 396 /* Disable Reset if in Reset state */ 397 reset_set_enable(PERIPH_ID_USBD, 0); 398 } 399 usb1ctlr = (struct usb_ctlr *) 400 ((u32)config->reg & USB1_ADDR_MASK); 401 val = readl(&usb1ctlr->utmip_bias_cfg0); 402 setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB); 403 clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK, 404 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT); 405 clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK, 406 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT); 407 writel(val, &usb1ctlr->utmip_bias_cfg0); 408 409 /* Miscellaneous setting mentioned in Programming Guide */ 410 clrbits_le32(&usbctlr->utmip_misc_cfg0, 411 UTMIP_SUSPEND_EXIT_ON_EDGE); 412 } 413 414 /* Setting the tracking length time */ 415 clrsetbits_le32(&usbctlr->utmip_bias_cfg1, 416 UTMIP_BIAS_PDTRK_COUNT_MASK, 417 timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); 418 419 /* Program debounce time for VBUS to become valid */ 420 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, 421 UTMIP_DEBOUNCE_CFG0_MASK, 422 timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); 423 424 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); 425 426 /* Disable battery charge enabling bit */ 427 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); 428 429 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); 430 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); 431 432 /* 433 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT 434 * Setting these fields, together with default values of the 435 * other fields, results in programming the registers below as 436 * follows: 437 * UTMIP_HSRX_CFG0 = 0x9168c000 438 * UTMIP_HSRX_CFG1 = 0x13 439 */ 440 441 /* Set PLL enable delay count and Crystal frequency count */ 442 val = readl(&usbctlr->utmip_hsrx_cfg0); 443 clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, 444 utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); 445 clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, 446 utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); 447 writel(val, &usbctlr->utmip_hsrx_cfg0); 448 449 /* Configure the UTMIP_HS_SYNC_START_DLY */ 450 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, 451 UTMIP_HS_SYNC_START_DLY_MASK, 452 utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); 453 454 /* Preceed the crystal clock disable by >100ns delay. */ 455 udelay(1); 456 457 /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ 458 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 459 460 if (controller->has_hostpc) { 461 if (config->periph_id == PERIPH_ID_USBD) 462 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 463 UTMIP_FORCE_PD_SAMP_A_POWERDOWN); 464 if (config->periph_id == PERIPH_ID_USB3) 465 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 466 UTMIP_FORCE_PD_SAMP_C_POWERDOWN); 467 } 468 /* Finished the per-controller init. */ 469 470 /* De-assert UTMIP_RESET to bring out of reset. */ 471 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 472 473 /* Wait for the phy clock to become valid in 100 ms */ 474 for (loop_count = 100000; loop_count != 0; loop_count--) { 475 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 476 break; 477 udelay(1); 478 } 479 if (!loop_count) 480 return -1; 481 482 /* Disable ICUSB FS/LS transceiver */ 483 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); 484 485 /* Select UTMI parallel interface */ 486 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, 487 PTS_UTMI << PTS_SHIFT); 488 clrbits_le32(&usbctlr->port_sc1, STS); 489 490 /* Deassert power down state */ 491 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | 492 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); 493 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | 494 UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); 495 496 if (controller->has_hostpc) { 497 /* 498 * BIAS Pad Power Down is common among all 3 USB 499 * controllers and can be controlled from USB1 only. 500 */ 501 usb1ctlr = (struct usb_ctlr *) 502 ((u32)config->reg & USB1_ADDR_MASK); 503 clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD); 504 udelay(25); 505 clrbits_le32(&usb1ctlr->utmip_bias_cfg1, 506 UTMIP_FORCE_PDTRK_POWERDOWN); 507 } 508 return 0; 509 } 510 511 #ifdef CONFIG_USB_ULPI 512 /* if board file does not set a ULPI reference frequency we default to 24MHz */ 513 #ifndef CONFIG_ULPI_REF_CLK 514 #define CONFIG_ULPI_REF_CLK 24000000 515 #endif 516 517 /* set up the ULPI USB controller with the parameters provided */ 518 static int init_ulpi_usb_controller(struct fdt_usb *config) 519 { 520 u32 val; 521 int loop_count; 522 struct ulpi_viewport ulpi_vp; 523 struct usb_ctlr *usbctlr = config->reg; 524 525 /* set up ULPI reference clock on pllp_out4 */ 526 clock_enable(PERIPH_ID_DEV2_OUT); 527 clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK); 528 529 /* reset ULPI phy */ 530 if (fdt_gpio_isvalid(&config->phy_reset_gpio)) { 531 fdtdec_setup_gpio(&config->phy_reset_gpio); 532 gpio_direction_output(config->phy_reset_gpio.gpio, 0); 533 mdelay(5); 534 gpio_set_value(config->phy_reset_gpio.gpio, 1); 535 } 536 537 /* Reset the usb controller */ 538 clock_enable(config->periph_id); 539 usbf_reset_controller(config, usbctlr); 540 541 /* enable pinmux bypass */ 542 setbits_le32(&usbctlr->ulpi_timing_ctrl_0, 543 ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); 544 545 /* Select ULPI parallel interface */ 546 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT); 547 548 /* enable ULPI transceiver */ 549 setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); 550 551 /* configure ULPI transceiver timings */ 552 val = 0; 553 writel(val, &usbctlr->ulpi_timing_ctrl_1); 554 555 val |= ULPI_DATA_TRIMMER_SEL(4); 556 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); 557 val |= ULPI_DIR_TRIMMER_SEL(4); 558 writel(val, &usbctlr->ulpi_timing_ctrl_1); 559 udelay(10); 560 561 val |= ULPI_DATA_TRIMMER_LOAD; 562 val |= ULPI_STPDIRNXT_TRIMMER_LOAD; 563 val |= ULPI_DIR_TRIMMER_LOAD; 564 writel(val, &usbctlr->ulpi_timing_ctrl_1); 565 566 /* set up phy for host operation with external vbus supply */ 567 ulpi_vp.port_num = 0; 568 ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport; 569 570 if (ulpi_init(&ulpi_vp)) { 571 printf("Tegra ULPI viewport init failed\n"); 572 return -1; 573 } 574 575 ulpi_set_vbus(&ulpi_vp, 1, 1); 576 ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0); 577 578 /* enable wakeup events */ 579 setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC); 580 581 /* Enable and wait for the phy clock to become valid in 100 ms */ 582 setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 583 for (loop_count = 100000; loop_count != 0; loop_count--) { 584 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 585 break; 586 udelay(1); 587 } 588 if (!loop_count) 589 return -1; 590 clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 591 592 return 0; 593 } 594 #else 595 static int init_ulpi_usb_controller(struct fdt_usb *config) 596 { 597 printf("No code to set up ULPI controller, please enable" 598 "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT"); 599 return -1; 600 } 601 #endif 602 603 static void config_clock(const u32 timing[]) 604 { 605 clock_start_pll(CLOCK_ID_USB, 606 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], 607 timing[PARAM_CPCON], timing[PARAM_LFCON]); 608 } 609 610 static int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config) 611 { 612 const char *phy, *mode; 613 614 config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg"); 615 mode = fdt_getprop(blob, node, "dr_mode", NULL); 616 if (mode) { 617 if (0 == strcmp(mode, "host")) 618 config->dr_mode = DR_MODE_HOST; 619 else if (0 == strcmp(mode, "peripheral")) 620 config->dr_mode = DR_MODE_DEVICE; 621 else if (0 == strcmp(mode, "otg")) 622 config->dr_mode = DR_MODE_OTG; 623 else { 624 debug("%s: Cannot decode dr_mode '%s'\n", __func__, 625 mode); 626 return -FDT_ERR_NOTFOUND; 627 } 628 } else { 629 config->dr_mode = DR_MODE_HOST; 630 } 631 632 phy = fdt_getprop(blob, node, "phy_type", NULL); 633 config->utmi = phy && 0 == strcmp("utmi", phy); 634 config->ulpi = phy && 0 == strcmp("ulpi", phy); 635 config->enabled = fdtdec_get_is_enabled(blob, node); 636 config->has_legacy_mode = fdtdec_get_bool(blob, node, 637 "nvidia,has-legacy-mode"); 638 if (config->has_legacy_mode) 639 port_addr_clear_csc = (u32) config->reg; 640 config->periph_id = clock_decode_periph_id(blob, node); 641 if (config->periph_id == PERIPH_ID_NONE) { 642 debug("%s: Missing/invalid peripheral ID\n", __func__); 643 return -FDT_ERR_NOTFOUND; 644 } 645 fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio); 646 fdtdec_decode_gpio(blob, node, "nvidia,phy-reset-gpio", 647 &config->phy_reset_gpio); 648 debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, " 649 "vbus=%d, phy_reset=%d, dr_mode=%d\n", 650 config->enabled, config->has_legacy_mode, config->utmi, 651 config->ulpi, config->periph_id, config->vbus_gpio.gpio, 652 config->phy_reset_gpio.gpio, config->dr_mode); 653 654 return 0; 655 } 656 657 /* 658 * process_usb_nodes() - Process a list of USB nodes, adding them to our list 659 * of USB ports. 660 * @blob: fdt blob 661 * @node_list: list of nodes to process (any <=0 are ignored) 662 * @count: number of nodes to process 663 * 664 * Return: 0 - ok, -1 - error 665 */ 666 static int process_usb_nodes(const void *blob, int node_list[], int count) 667 { 668 struct fdt_usb config; 669 int node, i; 670 int clk_done = 0; 671 672 port_count = 0; 673 for (i = 0; i < count; i++) { 674 if (port_count == USB_PORTS_MAX) { 675 printf("tegrausb: Cannot register more than %d ports\n", 676 USB_PORTS_MAX); 677 return -1; 678 } 679 680 debug("USB %d: ", i); 681 node = node_list[i]; 682 if (!node) 683 continue; 684 if (fdt_decode_usb(blob, node, &config)) { 685 debug("Cannot decode USB node %s\n", 686 fdt_get_name(blob, node, NULL)); 687 return -1; 688 } 689 if (!clk_done) { 690 config_clock(get_pll_timing()); 691 clk_done = 1; 692 } 693 config.initialized = 0; 694 695 /* add new USB port to the list of available ports */ 696 port[port_count++] = config; 697 } 698 699 return 0; 700 } 701 702 int usb_process_devicetree(const void *blob) 703 { 704 int node_list[USB_PORTS_MAX]; 705 int count, err = 0; 706 int i; 707 708 for (i = 0; i < ARRAY_SIZE(fdt_usb_controllers); i++) { 709 controller = &fdt_usb_controllers[i]; 710 711 count = fdtdec_find_aliases_for_id(blob, "usb", 712 controller->compat, node_list, USB_PORTS_MAX); 713 if (count) { 714 err = process_usb_nodes(blob, node_list, count); 715 if (err) 716 printf("%s: Error processing USB node!\n", 717 __func__); 718 return err; 719 } 720 } 721 if (i == ARRAY_SIZE(fdt_usb_controllers)) 722 controller = NULL; 723 724 return err; 725 } 726 727 /** 728 * Start up the given port number (ports are numbered from 0 on each board). 729 * This returns values for the appropriate hccr and hcor addresses to use for 730 * USB EHCI operations. 731 * 732 * @param index port number to start 733 * @param hccr returns start address of EHCI HCCR registers 734 * @param hcor returns start address of EHCI HCOR registers 735 * @return 0 if ok, -1 on error (generally invalid port number) 736 */ 737 int ehci_hcd_init(int index, enum usb_init_type init, 738 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 739 { 740 struct fdt_usb *config; 741 struct usb_ctlr *usbctlr; 742 743 if (index >= port_count) 744 return -1; 745 746 config = &port[index]; 747 748 /* skip init, if the port is already initialized */ 749 if (config->initialized) 750 goto success; 751 752 if (config->utmi && init_utmi_usb_controller(config)) { 753 printf("tegrausb: Cannot init port %d\n", index); 754 return -1; 755 } 756 757 if (config->ulpi && init_ulpi_usb_controller(config)) { 758 printf("tegrausb: Cannot init port %d\n", index); 759 return -1; 760 } 761 762 set_host_mode(config); 763 764 config->initialized = 1; 765 766 success: 767 usbctlr = config->reg; 768 *hccr = (struct ehci_hccr *)&usbctlr->cap_length; 769 *hcor = (struct ehci_hcor *)&usbctlr->usb_cmd; 770 771 if (controller->has_hostpc) { 772 /* Set to Host mode after Controller Reset was done */ 773 clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, 774 USBMODE_CM_HC); 775 /* Select UTMI parallel interface after setting host mode */ 776 if (config->utmi) { 777 clrsetbits_le32((char *)&usbctlr->usb_cmd + 778 HOSTPC1_DEVLC, PTS_MASK, 779 PTS_UTMI << PTS_SHIFT); 780 clrbits_le32((char *)&usbctlr->usb_cmd + 781 HOSTPC1_DEVLC, STS); 782 } 783 } 784 return 0; 785 } 786 787 /* 788 * Bring down the specified USB controller 789 */ 790 int ehci_hcd_stop(int index) 791 { 792 struct usb_ctlr *usbctlr; 793 794 usbctlr = port[index].reg; 795 796 /* Stop controller */ 797 writel(0, &usbctlr->usb_cmd); 798 udelay(1000); 799 800 /* Initiate controller reset */ 801 writel(2, &usbctlr->usb_cmd); 802 udelay(1000); 803 804 port[index].initialized = 0; 805 806 return 0; 807 } 808