1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * Copyright (c) 2009-2015 NVIDIA Corporation 4 * Copyright (c) 2013 Lucas Stach 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <asm/errno.h> 12 #include <asm/io.h> 13 #include <asm-generic/gpio.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch-tegra/usb.h> 16 #include <asm/arch-tegra/clk_rst.h> 17 #include <usb.h> 18 #include <usb/ulpi.h> 19 #include <libfdt.h> 20 #include <fdtdec.h> 21 22 #include "ehci.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define USB1_ADDR_MASK 0xFFFF0000 27 28 #define HOSTPC1_DEVLC 0x84 29 #define HOSTPC1_PSPD(x) (((x) >> 25) & 0x3) 30 31 #ifdef CONFIG_USB_ULPI 32 #ifndef CONFIG_USB_ULPI_VIEWPORT 33 #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \ 34 define CONFIG_USB_ULPI_VIEWPORT" 35 #endif 36 #endif 37 38 /* Parameters we need for USB */ 39 enum { 40 PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ 41 PARAM_DIVM, /* PLL INPUT DIVIDER */ 42 PARAM_DIVP, /* POST DIVIDER (2^N) */ 43 PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ 44 PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ 45 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ 46 PARAM_STABLE_COUNT, /* PLL-U STABLE count */ 47 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ 48 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ 49 PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ 50 PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ 51 52 PARAM_COUNT 53 }; 54 55 /* Possible port types (dual role mode) */ 56 enum dr_mode { 57 DR_MODE_NONE = 0, 58 DR_MODE_HOST, /* supports host operation */ 59 DR_MODE_DEVICE, /* supports device operation */ 60 DR_MODE_OTG, /* supports both */ 61 }; 62 63 enum usb_ctlr_type { 64 USB_CTLR_T20, 65 USB_CTLR_T30, 66 USB_CTLR_T114, 67 USB_CTLR_T210, 68 69 USB_CTRL_COUNT, 70 }; 71 72 /* Information about a USB port */ 73 struct fdt_usb { 74 struct ehci_ctrl ehci; 75 struct usb_ctlr *reg; /* address of registers in physical memory */ 76 unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ 77 unsigned ulpi:1; /* 1 if port has external ULPI transceiver */ 78 unsigned enabled:1; /* 1 to enable, 0 to disable */ 79 unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ 80 enum usb_ctlr_type type; 81 enum usb_init_type init_type; 82 enum dr_mode dr_mode; /* dual role mode */ 83 enum periph_id periph_id;/* peripheral id */ 84 struct gpio_desc vbus_gpio; /* GPIO for vbus enable */ 85 struct gpio_desc phy_reset_gpio; /* GPIO to reset ULPI phy */ 86 }; 87 88 /* 89 * This table has USB timing parameters for each Oscillator frequency we 90 * support. There are four sets of values: 91 * 92 * 1. PLLU configuration information (reference clock is osc/clk_m and 93 * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). 94 * 95 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 96 * ---------------------------------------------------------------------- 97 * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) 98 * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) 99 * Filter frequency (MHz) 1 4.8 6 2 100 * CPCON 1100b 0011b 1100b 1100b 101 * LFCON0 0 0 0 0 102 * 103 * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: 104 * 105 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 106 * --------------------------------------------------------------------------- 107 * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) 108 * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) 109 * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) 110 * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) 111 * 112 * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and 113 * SessEnd. Each of these signals have their own debouncer and for each of 114 * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or 115 * BIAS_DEBOUNCE_B). 116 * 117 * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: 118 * 0xffff -> No debouncing at all 119 * <n> ms = <n> *1000 / (1/19.2MHz) / 4 120 * 121 * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: 122 * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 123 * 124 * We need to use only DebounceA for BOOTROM. We don't need the DebounceB 125 * values, so we can keep those to default. 126 * 127 * 4. The 20 microsecond delay after bias cell operation. 128 */ 129 static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 130 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 131 { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, 132 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, 133 { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, 134 { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 135 }; 136 137 static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 138 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 139 { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 }, 140 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 }, 141 { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 142 { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 143 }; 144 145 static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 146 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 147 { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 }, 148 { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 }, 149 { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 150 { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB } 151 }; 152 153 /* NOTE: 13/26MHz settings are N/A for T210, so dupe 12MHz settings for now */ 154 static const unsigned T210_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 155 /* DivN, DivM, DivP, KCP, KVCO, Delays Debounce, Bias */ 156 { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 }, 157 { 0x019, 0x01, 0x01, 0x0, 0, 0x03, 0x4B, 0x0C, 0xBB, 48000, 8 }, 158 { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 }, 159 { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 }, 160 }; 161 162 /* UTMIP Idle Wait Delay */ 163 static const u8 utmip_idle_wait_delay = 17; 164 165 /* UTMIP Elastic limit */ 166 static const u8 utmip_elastic_limit = 16; 167 168 /* UTMIP High Speed Sync Start Delay */ 169 static const u8 utmip_hs_sync_start_delay = 9; 170 171 struct fdt_usb_controller { 172 /* flag to determine whether controller supports hostpc register */ 173 u32 has_hostpc:1; 174 const unsigned *pll_parameter; 175 }; 176 177 static struct fdt_usb_controller fdt_usb_controllers[USB_CTRL_COUNT] = { 178 { 179 .has_hostpc = 0, 180 .pll_parameter = (const unsigned *)T20_usb_pll, 181 }, 182 { 183 .has_hostpc = 1, 184 .pll_parameter = (const unsigned *)T30_usb_pll, 185 }, 186 { 187 .has_hostpc = 1, 188 .pll_parameter = (const unsigned *)T114_usb_pll, 189 }, 190 { 191 .has_hostpc = 1, 192 .pll_parameter = (const unsigned *)T210_usb_pll, 193 }, 194 }; 195 196 /* 197 * A known hardware issue where Connect Status Change bit of PORTSC register 198 * of USB1 controller will be set after Port Reset. 199 * We have to clear it in order for later device enumeration to proceed. 200 */ 201 static void tegra_ehci_powerup_fixup(struct ehci_ctrl *ctrl, 202 uint32_t *status_reg, uint32_t *reg) 203 { 204 struct fdt_usb *config = ctrl->priv; 205 struct fdt_usb_controller *controller; 206 207 controller = &fdt_usb_controllers[config->type]; 208 mdelay(50); 209 /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */ 210 if (controller->has_hostpc) 211 *reg |= EHCI_PS_PE; 212 213 if (!config->has_legacy_mode) 214 return; 215 /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */ 216 if (ehci_readl(status_reg) & EHCI_PS_CSC) 217 *reg |= EHCI_PS_CSC; 218 } 219 220 static void tegra_ehci_set_usbmode(struct ehci_ctrl *ctrl) 221 { 222 struct fdt_usb *config = ctrl->priv; 223 struct usb_ctlr *usbctlr; 224 uint32_t tmp; 225 226 usbctlr = config->reg; 227 228 tmp = ehci_readl(&usbctlr->usb_mode); 229 tmp |= USBMODE_CM_HC; 230 ehci_writel(&usbctlr->usb_mode, tmp); 231 } 232 233 static int tegra_ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg) 234 { 235 struct fdt_usb *config = ctrl->priv; 236 struct fdt_usb_controller *controller; 237 uint32_t tmp; 238 uint32_t *reg_ptr; 239 240 controller = &fdt_usb_controllers[config->type]; 241 if (controller->has_hostpc) { 242 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + 243 HOSTPC1_DEVLC); 244 tmp = ehci_readl(reg_ptr); 245 return HOSTPC1_PSPD(tmp); 246 } else 247 return PORTSC_PSPD(reg); 248 } 249 250 /* Set up VBUS for host/device mode */ 251 static void set_up_vbus(struct fdt_usb *config, enum usb_init_type init) 252 { 253 /* 254 * If we are an OTG port initializing in host mode, 255 * check if remote host is driving VBus and bail out in this case. 256 */ 257 if (init == USB_INIT_HOST && 258 config->dr_mode == DR_MODE_OTG && 259 (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) { 260 printf("tegrausb: VBUS input active; not enabling as host\n"); 261 return; 262 } 263 264 if (dm_gpio_is_valid(&config->vbus_gpio)) { 265 int vbus_value; 266 267 vbus_value = (init == USB_INIT_HOST); 268 dm_gpio_set_value(&config->vbus_gpio, vbus_value); 269 270 debug("set_up_vbus: GPIO %d %d\n", 271 gpio_get_number(&config->vbus_gpio), vbus_value); 272 } 273 } 274 275 static void usbf_reset_controller(struct fdt_usb *config, 276 struct usb_ctlr *usbctlr) 277 { 278 /* Reset the USB controller with 2us delay */ 279 reset_periph(config->periph_id, 2); 280 281 /* 282 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under 283 * base address 284 */ 285 if (config->has_legacy_mode) 286 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); 287 288 /* Put UTMIP1/3 in reset */ 289 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 290 291 /* Enable the UTMIP PHY */ 292 if (config->utmi) 293 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); 294 } 295 296 static const unsigned *get_pll_timing(struct fdt_usb_controller *controller) 297 { 298 const unsigned *timing; 299 300 timing = controller->pll_parameter + 301 clock_get_osc_freq() * PARAM_COUNT; 302 303 return timing; 304 } 305 306 /* select the PHY to use with a USB controller */ 307 static void init_phy_mux(struct fdt_usb *config, uint pts, 308 enum usb_init_type init) 309 { 310 struct usb_ctlr *usbctlr = config->reg; 311 312 #if defined(CONFIG_TEGRA20) 313 if (config->periph_id == PERIPH_ID_USBD) { 314 clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, 315 pts << PTS1_SHIFT); 316 clrbits_le32(&usbctlr->port_sc1, STS1); 317 } else { 318 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, 319 pts << PTS_SHIFT); 320 clrbits_le32(&usbctlr->port_sc1, STS); 321 } 322 #else 323 /* Set to Host mode (if applicable) after Controller Reset was done */ 324 clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, 325 (init == USB_INIT_HOST) ? USBMODE_CM_HC : 0); 326 /* 327 * Select PHY interface after setting host mode. 328 * For device mode, the ordering requirement is not an issue, since 329 * only the first USB controller supports device mode, and that USB 330 * controller can only talk to a UTMI PHY, so the PHY selection is 331 * already made at reset time, so this write is a no-op. 332 */ 333 clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, 334 pts << PTS_SHIFT); 335 clrbits_le32(&usbctlr->hostpc1_devlc, STS); 336 #endif 337 } 338 339 /* set up the UTMI USB controller with the parameters provided */ 340 static int init_utmi_usb_controller(struct fdt_usb *config, 341 enum usb_init_type init) 342 { 343 struct fdt_usb_controller *controller; 344 u32 b_sess_valid_mask, val; 345 int loop_count; 346 const unsigned *timing; 347 struct usb_ctlr *usbctlr = config->reg; 348 struct clk_rst_ctlr *clkrst; 349 struct usb_ctlr *usb1ctlr; 350 351 clock_enable(config->periph_id); 352 353 /* Reset the usb controller */ 354 usbf_reset_controller(config, usbctlr); 355 356 /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ 357 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 358 359 /* Follow the crystal clock disable by >100ns delay */ 360 udelay(1); 361 362 b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN); 363 clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask, 364 (init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0); 365 366 /* 367 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP 368 * mux must be switched to actually use a_sess_vld threshold. 369 */ 370 if (config->dr_mode == DR_MODE_OTG && 371 dm_gpio_is_valid(&config->vbus_gpio)) 372 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, 373 VBUS_SENSE_CTL_MASK, 374 VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); 375 376 controller = &fdt_usb_controllers[config->type]; 377 debug("controller=%p, type=%d\n", controller, config->type); 378 379 /* 380 * PLL Delay CONFIGURATION settings. The following parameters control 381 * the bring up of the plls. 382 */ 383 timing = get_pll_timing(controller); 384 385 if (!controller->has_hostpc) { 386 val = readl(&usbctlr->utmip_misc_cfg1); 387 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 388 timing[PARAM_STABLE_COUNT] << 389 UTMIP_PLLU_STABLE_COUNT_SHIFT); 390 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 391 timing[PARAM_ACTIVE_DELAY_COUNT] << 392 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 393 writel(val, &usbctlr->utmip_misc_cfg1); 394 395 /* Set PLL enable delay count and crystal frequency count */ 396 val = readl(&usbctlr->utmip_pll_cfg1); 397 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 398 timing[PARAM_ENABLE_DELAY_COUNT] << 399 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 400 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 401 timing[PARAM_XTAL_FREQ_COUNT] << 402 UTMIP_XTAL_FREQ_COUNT_SHIFT); 403 writel(val, &usbctlr->utmip_pll_cfg1); 404 } else { 405 clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 406 407 val = readl(&clkrst->crc_utmip_pll_cfg2); 408 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 409 timing[PARAM_STABLE_COUNT] << 410 UTMIP_PLLU_STABLE_COUNT_SHIFT); 411 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 412 timing[PARAM_ACTIVE_DELAY_COUNT] << 413 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 414 writel(val, &clkrst->crc_utmip_pll_cfg2); 415 416 /* Set PLL enable delay count and crystal frequency count */ 417 val = readl(&clkrst->crc_utmip_pll_cfg1); 418 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 419 timing[PARAM_ENABLE_DELAY_COUNT] << 420 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 421 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 422 timing[PARAM_XTAL_FREQ_COUNT] << 423 UTMIP_XTAL_FREQ_COUNT_SHIFT); 424 writel(val, &clkrst->crc_utmip_pll_cfg1); 425 426 /* Disable Power Down state for PLL */ 427 clrbits_le32(&clkrst->crc_utmip_pll_cfg1, 428 PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN | 429 PLL_ACTIVE_POWERDOWN); 430 431 /* Recommended PHY settings for EYE diagram */ 432 val = readl(&usbctlr->utmip_xcvr_cfg0); 433 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK, 434 0x4 << UTMIP_XCVR_SETUP_SHIFT); 435 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK, 436 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT); 437 clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK, 438 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT); 439 writel(val, &usbctlr->utmip_xcvr_cfg0); 440 clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1, 441 UTMIP_XCVR_TERM_RANGE_ADJ_MASK, 442 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT); 443 444 /* Some registers can be controlled from USB1 only. */ 445 if (config->periph_id != PERIPH_ID_USBD) { 446 clock_enable(PERIPH_ID_USBD); 447 /* Disable Reset if in Reset state */ 448 reset_set_enable(PERIPH_ID_USBD, 0); 449 } 450 usb1ctlr = (struct usb_ctlr *) 451 ((unsigned long)config->reg & USB1_ADDR_MASK); 452 val = readl(&usb1ctlr->utmip_bias_cfg0); 453 setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB); 454 clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK, 455 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT); 456 clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK, 457 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT); 458 writel(val, &usb1ctlr->utmip_bias_cfg0); 459 460 /* Miscellaneous setting mentioned in Programming Guide */ 461 clrbits_le32(&usbctlr->utmip_misc_cfg0, 462 UTMIP_SUSPEND_EXIT_ON_EDGE); 463 } 464 465 /* Setting the tracking length time */ 466 clrsetbits_le32(&usbctlr->utmip_bias_cfg1, 467 UTMIP_BIAS_PDTRK_COUNT_MASK, 468 timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); 469 470 /* Program debounce time for VBUS to become valid */ 471 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, 472 UTMIP_DEBOUNCE_CFG0_MASK, 473 timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); 474 475 if (timing[PARAM_DEBOUNCE_A_TIME] > 0xFFFF) { 476 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, 477 UTMIP_DEBOUNCE_CFG0_MASK, 478 (timing[PARAM_DEBOUNCE_A_TIME] >> 1) 479 << UTMIP_DEBOUNCE_CFG0_SHIFT); 480 clrsetbits_le32(&usbctlr->utmip_bias_cfg1, 481 UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK, 482 1 << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT); 483 } 484 485 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); 486 487 /* Disable battery charge enabling bit */ 488 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); 489 490 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); 491 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); 492 493 /* 494 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT 495 * Setting these fields, together with default values of the 496 * other fields, results in programming the registers below as 497 * follows: 498 * UTMIP_HSRX_CFG0 = 0x9168c000 499 * UTMIP_HSRX_CFG1 = 0x13 500 */ 501 502 /* Set PLL enable delay count and Crystal frequency count */ 503 val = readl(&usbctlr->utmip_hsrx_cfg0); 504 clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, 505 utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); 506 clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, 507 utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); 508 writel(val, &usbctlr->utmip_hsrx_cfg0); 509 510 /* Configure the UTMIP_HS_SYNC_START_DLY */ 511 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, 512 UTMIP_HS_SYNC_START_DLY_MASK, 513 utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); 514 515 /* Preceed the crystal clock disable by >100ns delay. */ 516 udelay(1); 517 518 /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ 519 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 520 521 if (controller->has_hostpc) { 522 if (config->periph_id == PERIPH_ID_USBD) 523 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 524 UTMIP_FORCE_PD_SAMP_A_POWERDOWN); 525 if (config->periph_id == PERIPH_ID_USB2) 526 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 527 UTMIP_FORCE_PD_SAMP_B_POWERDOWN); 528 if (config->periph_id == PERIPH_ID_USB3) 529 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 530 UTMIP_FORCE_PD_SAMP_C_POWERDOWN); 531 } 532 /* Finished the per-controller init. */ 533 534 /* De-assert UTMIP_RESET to bring out of reset. */ 535 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 536 537 /* Wait for the phy clock to become valid in 100 ms */ 538 for (loop_count = 100000; loop_count != 0; loop_count--) { 539 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 540 break; 541 udelay(1); 542 } 543 if (!loop_count) 544 return -ETIMEDOUT; 545 546 /* Disable ICUSB FS/LS transceiver */ 547 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); 548 549 /* Select UTMI parallel interface */ 550 init_phy_mux(config, PTS_UTMI, init); 551 552 /* Deassert power down state */ 553 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | 554 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); 555 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | 556 UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); 557 558 if (controller->has_hostpc) { 559 /* 560 * BIAS Pad Power Down is common among all 3 USB 561 * controllers and can be controlled from USB1 only. 562 */ 563 usb1ctlr = (struct usb_ctlr *) 564 ((unsigned long)config->reg & USB1_ADDR_MASK); 565 clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD); 566 udelay(25); 567 clrbits_le32(&usb1ctlr->utmip_bias_cfg1, 568 UTMIP_FORCE_PDTRK_POWERDOWN); 569 } 570 return 0; 571 } 572 573 #ifdef CONFIG_USB_ULPI 574 /* if board file does not set a ULPI reference frequency we default to 24MHz */ 575 #ifndef CONFIG_ULPI_REF_CLK 576 #define CONFIG_ULPI_REF_CLK 24000000 577 #endif 578 579 /* set up the ULPI USB controller with the parameters provided */ 580 static int init_ulpi_usb_controller(struct fdt_usb *config, 581 enum usb_init_type init) 582 { 583 u32 val; 584 int loop_count; 585 struct ulpi_viewport ulpi_vp; 586 struct usb_ctlr *usbctlr = config->reg; 587 int ret; 588 589 /* set up ULPI reference clock on pllp_out4 */ 590 clock_enable(PERIPH_ID_DEV2_OUT); 591 clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK); 592 593 /* reset ULPI phy */ 594 if (dm_gpio_is_valid(&config->phy_reset_gpio)) { 595 dm_gpio_set_value(&config->phy_reset_gpio, 0); 596 mdelay(5); 597 dm_gpio_set_value(&config->phy_reset_gpio, 1); 598 } 599 600 /* Reset the usb controller */ 601 clock_enable(config->periph_id); 602 usbf_reset_controller(config, usbctlr); 603 604 /* enable pinmux bypass */ 605 setbits_le32(&usbctlr->ulpi_timing_ctrl_0, 606 ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); 607 608 /* Select ULPI parallel interface */ 609 init_phy_mux(config, PTS_ULPI, init); 610 611 /* enable ULPI transceiver */ 612 setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); 613 614 /* configure ULPI transceiver timings */ 615 val = 0; 616 writel(val, &usbctlr->ulpi_timing_ctrl_1); 617 618 val |= ULPI_DATA_TRIMMER_SEL(4); 619 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); 620 val |= ULPI_DIR_TRIMMER_SEL(4); 621 writel(val, &usbctlr->ulpi_timing_ctrl_1); 622 udelay(10); 623 624 val |= ULPI_DATA_TRIMMER_LOAD; 625 val |= ULPI_STPDIRNXT_TRIMMER_LOAD; 626 val |= ULPI_DIR_TRIMMER_LOAD; 627 writel(val, &usbctlr->ulpi_timing_ctrl_1); 628 629 /* set up phy for host operation with external vbus supply */ 630 ulpi_vp.port_num = 0; 631 ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport; 632 633 ret = ulpi_init(&ulpi_vp); 634 if (ret) { 635 printf("Tegra ULPI viewport init failed\n"); 636 return ret; 637 } 638 639 ulpi_set_vbus(&ulpi_vp, 1, 1); 640 ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0); 641 642 /* enable wakeup events */ 643 setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC); 644 645 /* Enable and wait for the phy clock to become valid in 100 ms */ 646 setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 647 for (loop_count = 100000; loop_count != 0; loop_count--) { 648 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 649 break; 650 udelay(1); 651 } 652 if (!loop_count) 653 return -ETIMEDOUT; 654 clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 655 656 return 0; 657 } 658 #else 659 static int init_ulpi_usb_controller(struct fdt_usb *config, 660 enum usb_init_type init) 661 { 662 printf("No code to set up ULPI controller, please enable" 663 "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT"); 664 return -ENOSYS; 665 } 666 #endif 667 668 static void config_clock(const u32 timing[]) 669 { 670 debug("%s: DIVM = %d, DIVN = %d, DIVP = %d, cpcon/lfcon = %d/%d\n", 671 __func__, timing[PARAM_DIVM], timing[PARAM_DIVN], 672 timing[PARAM_DIVP], timing[PARAM_CPCON], timing[PARAM_LFCON]); 673 674 clock_start_pll(CLOCK_ID_USB, 675 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], 676 timing[PARAM_CPCON], timing[PARAM_LFCON]); 677 } 678 679 static int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config) 680 { 681 const char *phy, *mode; 682 683 config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg"); 684 mode = fdt_getprop(blob, node, "dr_mode", NULL); 685 if (mode) { 686 if (0 == strcmp(mode, "host")) 687 config->dr_mode = DR_MODE_HOST; 688 else if (0 == strcmp(mode, "peripheral")) 689 config->dr_mode = DR_MODE_DEVICE; 690 else if (0 == strcmp(mode, "otg")) 691 config->dr_mode = DR_MODE_OTG; 692 else { 693 debug("%s: Cannot decode dr_mode '%s'\n", __func__, 694 mode); 695 return -EINVAL; 696 } 697 } else { 698 config->dr_mode = DR_MODE_HOST; 699 } 700 701 phy = fdt_getprop(blob, node, "phy_type", NULL); 702 config->utmi = phy && 0 == strcmp("utmi", phy); 703 config->ulpi = phy && 0 == strcmp("ulpi", phy); 704 config->enabled = fdtdec_get_is_enabled(blob, node); 705 config->has_legacy_mode = fdtdec_get_bool(blob, node, 706 "nvidia,has-legacy-mode"); 707 config->periph_id = clock_decode_periph_id(blob, node); 708 if (config->periph_id == PERIPH_ID_NONE) { 709 debug("%s: Missing/invalid peripheral ID\n", __func__); 710 return -EINVAL; 711 } 712 gpio_request_by_name_nodev(blob, node, "nvidia,vbus-gpio", 0, 713 &config->vbus_gpio, GPIOD_IS_OUT); 714 gpio_request_by_name_nodev(blob, node, "nvidia,phy-reset-gpio", 0, 715 &config->phy_reset_gpio, GPIOD_IS_OUT); 716 debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, " 717 "vbus=%d, phy_reset=%d, dr_mode=%d\n", 718 config->enabled, config->has_legacy_mode, config->utmi, 719 config->ulpi, config->periph_id, 720 gpio_get_number(&config->vbus_gpio), 721 gpio_get_number(&config->phy_reset_gpio), config->dr_mode); 722 723 return 0; 724 } 725 726 int usb_common_init(struct fdt_usb *config, enum usb_init_type init) 727 { 728 int ret = 0; 729 730 switch (init) { 731 case USB_INIT_HOST: 732 switch (config->dr_mode) { 733 case DR_MODE_HOST: 734 case DR_MODE_OTG: 735 break; 736 default: 737 printf("tegrausb: Invalid dr_mode %d for host mode\n", 738 config->dr_mode); 739 return -1; 740 } 741 break; 742 case USB_INIT_DEVICE: 743 if (config->periph_id != PERIPH_ID_USBD) { 744 printf("tegrausb: Device mode only supported on first USB controller\n"); 745 return -1; 746 } 747 if (!config->utmi) { 748 printf("tegrausb: Device mode only supported with UTMI PHY\n"); 749 return -1; 750 } 751 switch (config->dr_mode) { 752 case DR_MODE_DEVICE: 753 case DR_MODE_OTG: 754 break; 755 default: 756 printf("tegrausb: Invalid dr_mode %d for device mode\n", 757 config->dr_mode); 758 return -1; 759 } 760 break; 761 default: 762 printf("tegrausb: Unknown USB_INIT_* %d\n", init); 763 return -1; 764 } 765 766 debug("%d, %d\n", config->utmi, config->ulpi); 767 if (config->utmi) 768 ret = init_utmi_usb_controller(config, init); 769 else if (config->ulpi) 770 ret = init_ulpi_usb_controller(config, init); 771 if (ret) 772 return ret; 773 774 set_up_vbus(config, init); 775 776 config->init_type = init; 777 778 return 0; 779 } 780 781 void usb_common_uninit(struct fdt_usb *priv) 782 { 783 struct usb_ctlr *usbctlr; 784 785 usbctlr = priv->reg; 786 787 /* Stop controller */ 788 writel(0, &usbctlr->usb_cmd); 789 udelay(1000); 790 791 /* Initiate controller reset */ 792 writel(2, &usbctlr->usb_cmd); 793 udelay(1000); 794 } 795 796 static const struct ehci_ops tegra_ehci_ops = { 797 .set_usb_mode = tegra_ehci_set_usbmode, 798 .get_port_speed = tegra_ehci_get_port_speed, 799 .powerup_fixup = tegra_ehci_powerup_fixup, 800 }; 801 802 static int ehci_usb_ofdata_to_platdata(struct udevice *dev) 803 { 804 struct fdt_usb *priv = dev_get_priv(dev); 805 int ret; 806 807 ret = fdt_decode_usb(gd->fdt_blob, dev->of_offset, priv); 808 if (ret) 809 return ret; 810 811 priv->type = dev_get_driver_data(dev); 812 813 return 0; 814 } 815 816 static int ehci_usb_probe(struct udevice *dev) 817 { 818 struct usb_platdata *plat = dev_get_platdata(dev); 819 struct fdt_usb *priv = dev_get_priv(dev); 820 struct ehci_hccr *hccr; 821 struct ehci_hcor *hcor; 822 static bool clk_done; 823 int ret; 824 825 ret = usb_common_init(priv, plat->init_type); 826 if (ret) 827 return ret; 828 hccr = (struct ehci_hccr *)&priv->reg->cap_length; 829 hcor = (struct ehci_hcor *)&priv->reg->usb_cmd; 830 if (!clk_done) { 831 config_clock(get_pll_timing(&fdt_usb_controllers[priv->type])); 832 clk_done = true; 833 } 834 835 return ehci_register(dev, hccr, hcor, &tegra_ehci_ops, 0, 836 plat->init_type); 837 } 838 839 static int ehci_usb_remove(struct udevice *dev) 840 { 841 int ret; 842 843 ret = ehci_deregister(dev); 844 if (ret) 845 return ret; 846 847 return 0; 848 } 849 850 static const struct udevice_id ehci_usb_ids[] = { 851 { .compatible = "nvidia,tegra20-ehci", .data = USB_CTLR_T20 }, 852 { .compatible = "nvidia,tegra30-ehci", .data = USB_CTLR_T30 }, 853 { .compatible = "nvidia,tegra114-ehci", .data = USB_CTLR_T114 }, 854 { .compatible = "nvidia,tegra210-ehci", .data = USB_CTLR_T210 }, 855 { } 856 }; 857 858 U_BOOT_DRIVER(usb_ehci) = { 859 .name = "ehci_tegra", 860 .id = UCLASS_USB, 861 .of_match = ehci_usb_ids, 862 .ofdata_to_platdata = ehci_usb_ofdata_to_platdata, 863 .probe = ehci_usb_probe, 864 .remove = ehci_usb_remove, 865 .ops = &ehci_usb_ops, 866 .platdata_auto_alloc_size = sizeof(struct usb_platdata), 867 .priv_auto_alloc_size = sizeof(struct fdt_usb), 868 .flags = DM_FLAG_ALLOC_PRIV_DMA, 869 }; 870