1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * Copyright (c) 2009-2013 NVIDIA Corporation 4 * Copyright (c) 2013 Lucas Stach 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <asm/errno.h> 12 #include <asm/io.h> 13 #include <asm-generic/gpio.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch-tegra/usb.h> 16 #include <asm/arch-tegra/clk_rst.h> 17 #include <usb.h> 18 #include <usb/ulpi.h> 19 #include <libfdt.h> 20 #include <fdtdec.h> 21 22 #include "ehci.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define USB1_ADDR_MASK 0xFFFF0000 27 28 #define HOSTPC1_DEVLC 0x84 29 #define HOSTPC1_PSPD(x) (((x) >> 25) & 0x3) 30 31 #ifdef CONFIG_USB_ULPI 32 #ifndef CONFIG_USB_ULPI_VIEWPORT 33 #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \ 34 define CONFIG_USB_ULPI_VIEWPORT" 35 #endif 36 #endif 37 38 /* Parameters we need for USB */ 39 enum { 40 PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ 41 PARAM_DIVM, /* PLL INPUT DIVIDER */ 42 PARAM_DIVP, /* POST DIVIDER (2^N) */ 43 PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ 44 PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ 45 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ 46 PARAM_STABLE_COUNT, /* PLL-U STABLE count */ 47 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ 48 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ 49 PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ 50 PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ 51 52 PARAM_COUNT 53 }; 54 55 /* Possible port types (dual role mode) */ 56 enum dr_mode { 57 DR_MODE_NONE = 0, 58 DR_MODE_HOST, /* supports host operation */ 59 DR_MODE_DEVICE, /* supports device operation */ 60 DR_MODE_OTG, /* supports both */ 61 }; 62 63 enum usb_ctlr_type { 64 USB_CTLR_T20, 65 USB_CTLR_T30, 66 USB_CTLR_T114, 67 68 USB_CTRL_COUNT, 69 }; 70 71 /* Information about a USB port */ 72 struct fdt_usb { 73 struct ehci_ctrl ehci; 74 struct usb_ctlr *reg; /* address of registers in physical memory */ 75 unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ 76 unsigned ulpi:1; /* 1 if port has external ULPI transceiver */ 77 unsigned enabled:1; /* 1 to enable, 0 to disable */ 78 unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ 79 enum usb_ctlr_type type; 80 enum usb_init_type init_type; 81 enum dr_mode dr_mode; /* dual role mode */ 82 enum periph_id periph_id;/* peripheral id */ 83 struct gpio_desc vbus_gpio; /* GPIO for vbus enable */ 84 struct gpio_desc phy_reset_gpio; /* GPIO to reset ULPI phy */ 85 }; 86 87 /* 88 * This table has USB timing parameters for each Oscillator frequency we 89 * support. There are four sets of values: 90 * 91 * 1. PLLU configuration information (reference clock is osc/clk_m and 92 * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). 93 * 94 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 95 * ---------------------------------------------------------------------- 96 * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) 97 * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) 98 * Filter frequency (MHz) 1 4.8 6 2 99 * CPCON 1100b 0011b 1100b 1100b 100 * LFCON0 0 0 0 0 101 * 102 * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: 103 * 104 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz 105 * --------------------------------------------------------------------------- 106 * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) 107 * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) 108 * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) 109 * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) 110 * 111 * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and 112 * SessEnd. Each of these signals have their own debouncer and for each of 113 * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or 114 * BIAS_DEBOUNCE_B). 115 * 116 * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: 117 * 0xffff -> No debouncing at all 118 * <n> ms = <n> *1000 / (1/19.2MHz) / 4 119 * 120 * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: 121 * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 122 * 123 * We need to use only DebounceA for BOOTROM. We don't need the DebounceB 124 * values, so we can keep those to default. 125 * 126 * 4. The 20 microsecond delay after bias cell operation. 127 */ 128 static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 129 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 130 { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, 131 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, 132 { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, 133 { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 134 }; 135 136 static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 137 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 138 { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 }, 139 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 }, 140 { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 141 { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } 142 }; 143 144 static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { 145 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ 146 { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 }, 147 { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 }, 148 { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, 149 { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB } 150 }; 151 152 /* UTMIP Idle Wait Delay */ 153 static const u8 utmip_idle_wait_delay = 17; 154 155 /* UTMIP Elastic limit */ 156 static const u8 utmip_elastic_limit = 16; 157 158 /* UTMIP High Speed Sync Start Delay */ 159 static const u8 utmip_hs_sync_start_delay = 9; 160 161 struct fdt_usb_controller { 162 /* flag to determine whether controller supports hostpc register */ 163 u32 has_hostpc:1; 164 const unsigned *pll_parameter; 165 }; 166 167 static struct fdt_usb_controller fdt_usb_controllers[USB_CTRL_COUNT] = { 168 { 169 .has_hostpc = 0, 170 .pll_parameter = (const unsigned *)T20_usb_pll, 171 }, 172 { 173 .has_hostpc = 1, 174 .pll_parameter = (const unsigned *)T30_usb_pll, 175 }, 176 { 177 .has_hostpc = 1, 178 .pll_parameter = (const unsigned *)T114_usb_pll, 179 }, 180 }; 181 182 /* 183 * A known hardware issue where Connect Status Change bit of PORTSC register 184 * of USB1 controller will be set after Port Reset. 185 * We have to clear it in order for later device enumeration to proceed. 186 */ 187 static void tegra_ehci_powerup_fixup(struct ehci_ctrl *ctrl, 188 uint32_t *status_reg, uint32_t *reg) 189 { 190 struct fdt_usb *config = ctrl->priv; 191 struct fdt_usb_controller *controller; 192 193 controller = &fdt_usb_controllers[config->type]; 194 mdelay(50); 195 /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */ 196 if (controller->has_hostpc) 197 *reg |= EHCI_PS_PE; 198 199 if (!config->has_legacy_mode) 200 return; 201 /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */ 202 if (ehci_readl(status_reg) & EHCI_PS_CSC) 203 *reg |= EHCI_PS_CSC; 204 } 205 206 static void tegra_ehci_set_usbmode(struct ehci_ctrl *ctrl) 207 { 208 struct fdt_usb *config = ctrl->priv; 209 struct usb_ctlr *usbctlr; 210 uint32_t tmp; 211 212 usbctlr = config->reg; 213 214 tmp = ehci_readl(&usbctlr->usb_mode); 215 tmp |= USBMODE_CM_HC; 216 ehci_writel(&usbctlr->usb_mode, tmp); 217 } 218 219 static int tegra_ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg) 220 { 221 struct fdt_usb *config = ctrl->priv; 222 struct fdt_usb_controller *controller; 223 uint32_t tmp; 224 uint32_t *reg_ptr; 225 226 controller = &fdt_usb_controllers[config->type]; 227 if (controller->has_hostpc) { 228 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + 229 HOSTPC1_DEVLC); 230 tmp = ehci_readl(reg_ptr); 231 return HOSTPC1_PSPD(tmp); 232 } else 233 return PORTSC_PSPD(reg); 234 } 235 236 /* Set up VBUS for host/device mode */ 237 static void set_up_vbus(struct fdt_usb *config, enum usb_init_type init) 238 { 239 /* 240 * If we are an OTG port initializing in host mode, 241 * check if remote host is driving VBus and bail out in this case. 242 */ 243 if (init == USB_INIT_HOST && 244 config->dr_mode == DR_MODE_OTG && 245 (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) { 246 printf("tegrausb: VBUS input active; not enabling as host\n"); 247 return; 248 } 249 250 if (dm_gpio_is_valid(&config->vbus_gpio)) { 251 int vbus_value; 252 253 vbus_value = (init == USB_INIT_HOST); 254 dm_gpio_set_value(&config->vbus_gpio, vbus_value); 255 256 debug("set_up_vbus: GPIO %d %d\n", 257 gpio_get_number(&config->vbus_gpio), vbus_value); 258 } 259 } 260 261 static void usbf_reset_controller(struct fdt_usb *config, 262 struct usb_ctlr *usbctlr) 263 { 264 /* Reset the USB controller with 2us delay */ 265 reset_periph(config->periph_id, 2); 266 267 /* 268 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under 269 * base address 270 */ 271 if (config->has_legacy_mode) 272 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); 273 274 /* Put UTMIP1/3 in reset */ 275 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 276 277 /* Enable the UTMIP PHY */ 278 if (config->utmi) 279 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); 280 } 281 282 static const unsigned *get_pll_timing(struct fdt_usb_controller *controller) 283 { 284 const unsigned *timing; 285 286 timing = controller->pll_parameter + 287 clock_get_osc_freq() * PARAM_COUNT; 288 289 return timing; 290 } 291 292 /* select the PHY to use with a USB controller */ 293 static void init_phy_mux(struct fdt_usb *config, uint pts, 294 enum usb_init_type init) 295 { 296 struct usb_ctlr *usbctlr = config->reg; 297 298 #if defined(CONFIG_TEGRA20) 299 if (config->periph_id == PERIPH_ID_USBD) { 300 clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, 301 pts << PTS1_SHIFT); 302 clrbits_le32(&usbctlr->port_sc1, STS1); 303 } else { 304 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, 305 pts << PTS_SHIFT); 306 clrbits_le32(&usbctlr->port_sc1, STS); 307 } 308 #else 309 /* Set to Host mode (if applicable) after Controller Reset was done */ 310 clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, 311 (init == USB_INIT_HOST) ? USBMODE_CM_HC : 0); 312 /* 313 * Select PHY interface after setting host mode. 314 * For device mode, the ordering requirement is not an issue, since 315 * only the first USB controller supports device mode, and that USB 316 * controller can only talk to a UTMI PHY, so the PHY selection is 317 * already made at reset time, so this write is a no-op. 318 */ 319 clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, 320 pts << PTS_SHIFT); 321 clrbits_le32(&usbctlr->hostpc1_devlc, STS); 322 #endif 323 } 324 325 /* set up the UTMI USB controller with the parameters provided */ 326 static int init_utmi_usb_controller(struct fdt_usb *config, 327 enum usb_init_type init) 328 { 329 struct fdt_usb_controller *controller; 330 u32 b_sess_valid_mask, val; 331 int loop_count; 332 const unsigned *timing; 333 struct usb_ctlr *usbctlr = config->reg; 334 struct clk_rst_ctlr *clkrst; 335 struct usb_ctlr *usb1ctlr; 336 337 clock_enable(config->periph_id); 338 339 /* Reset the usb controller */ 340 usbf_reset_controller(config, usbctlr); 341 342 /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ 343 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 344 345 /* Follow the crystal clock disable by >100ns delay */ 346 udelay(1); 347 348 b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN); 349 clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask, 350 (init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0); 351 352 /* 353 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP 354 * mux must be switched to actually use a_sess_vld threshold. 355 */ 356 if (config->dr_mode == DR_MODE_OTG && 357 dm_gpio_is_valid(&config->vbus_gpio)) 358 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, 359 VBUS_SENSE_CTL_MASK, 360 VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); 361 362 controller = &fdt_usb_controllers[config->type]; 363 debug("controller=%p, type=%d\n", controller, config->type); 364 365 /* 366 * PLL Delay CONFIGURATION settings. The following parameters control 367 * the bring up of the plls. 368 */ 369 timing = get_pll_timing(controller); 370 371 if (!controller->has_hostpc) { 372 val = readl(&usbctlr->utmip_misc_cfg1); 373 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 374 timing[PARAM_STABLE_COUNT] << 375 UTMIP_PLLU_STABLE_COUNT_SHIFT); 376 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 377 timing[PARAM_ACTIVE_DELAY_COUNT] << 378 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 379 writel(val, &usbctlr->utmip_misc_cfg1); 380 381 /* Set PLL enable delay count and crystal frequency count */ 382 val = readl(&usbctlr->utmip_pll_cfg1); 383 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 384 timing[PARAM_ENABLE_DELAY_COUNT] << 385 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 386 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 387 timing[PARAM_XTAL_FREQ_COUNT] << 388 UTMIP_XTAL_FREQ_COUNT_SHIFT); 389 writel(val, &usbctlr->utmip_pll_cfg1); 390 } else { 391 clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 392 393 val = readl(&clkrst->crc_utmip_pll_cfg2); 394 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, 395 timing[PARAM_STABLE_COUNT] << 396 UTMIP_PLLU_STABLE_COUNT_SHIFT); 397 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, 398 timing[PARAM_ACTIVE_DELAY_COUNT] << 399 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); 400 writel(val, &clkrst->crc_utmip_pll_cfg2); 401 402 /* Set PLL enable delay count and crystal frequency count */ 403 val = readl(&clkrst->crc_utmip_pll_cfg1); 404 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, 405 timing[PARAM_ENABLE_DELAY_COUNT] << 406 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); 407 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, 408 timing[PARAM_XTAL_FREQ_COUNT] << 409 UTMIP_XTAL_FREQ_COUNT_SHIFT); 410 writel(val, &clkrst->crc_utmip_pll_cfg1); 411 412 /* Disable Power Down state for PLL */ 413 clrbits_le32(&clkrst->crc_utmip_pll_cfg1, 414 PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN | 415 PLL_ACTIVE_POWERDOWN); 416 417 /* Recommended PHY settings for EYE diagram */ 418 val = readl(&usbctlr->utmip_xcvr_cfg0); 419 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK, 420 0x4 << UTMIP_XCVR_SETUP_SHIFT); 421 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK, 422 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT); 423 clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK, 424 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT); 425 writel(val, &usbctlr->utmip_xcvr_cfg0); 426 clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1, 427 UTMIP_XCVR_TERM_RANGE_ADJ_MASK, 428 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT); 429 430 /* Some registers can be controlled from USB1 only. */ 431 if (config->periph_id != PERIPH_ID_USBD) { 432 clock_enable(PERIPH_ID_USBD); 433 /* Disable Reset if in Reset state */ 434 reset_set_enable(PERIPH_ID_USBD, 0); 435 } 436 usb1ctlr = (struct usb_ctlr *) 437 ((unsigned long)config->reg & USB1_ADDR_MASK); 438 val = readl(&usb1ctlr->utmip_bias_cfg0); 439 setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB); 440 clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK, 441 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT); 442 clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK, 443 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT); 444 writel(val, &usb1ctlr->utmip_bias_cfg0); 445 446 /* Miscellaneous setting mentioned in Programming Guide */ 447 clrbits_le32(&usbctlr->utmip_misc_cfg0, 448 UTMIP_SUSPEND_EXIT_ON_EDGE); 449 } 450 451 /* Setting the tracking length time */ 452 clrsetbits_le32(&usbctlr->utmip_bias_cfg1, 453 UTMIP_BIAS_PDTRK_COUNT_MASK, 454 timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); 455 456 /* Program debounce time for VBUS to become valid */ 457 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, 458 UTMIP_DEBOUNCE_CFG0_MASK, 459 timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); 460 461 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); 462 463 /* Disable battery charge enabling bit */ 464 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); 465 466 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); 467 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); 468 469 /* 470 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT 471 * Setting these fields, together with default values of the 472 * other fields, results in programming the registers below as 473 * follows: 474 * UTMIP_HSRX_CFG0 = 0x9168c000 475 * UTMIP_HSRX_CFG1 = 0x13 476 */ 477 478 /* Set PLL enable delay count and Crystal frequency count */ 479 val = readl(&usbctlr->utmip_hsrx_cfg0); 480 clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, 481 utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); 482 clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, 483 utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); 484 writel(val, &usbctlr->utmip_hsrx_cfg0); 485 486 /* Configure the UTMIP_HS_SYNC_START_DLY */ 487 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, 488 UTMIP_HS_SYNC_START_DLY_MASK, 489 utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); 490 491 /* Preceed the crystal clock disable by >100ns delay. */ 492 udelay(1); 493 494 /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ 495 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); 496 497 if (controller->has_hostpc) { 498 if (config->periph_id == PERIPH_ID_USBD) 499 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 500 UTMIP_FORCE_PD_SAMP_A_POWERDOWN); 501 if (config->periph_id == PERIPH_ID_USB2) 502 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 503 UTMIP_FORCE_PD_SAMP_B_POWERDOWN); 504 if (config->periph_id == PERIPH_ID_USB3) 505 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, 506 UTMIP_FORCE_PD_SAMP_C_POWERDOWN); 507 } 508 /* Finished the per-controller init. */ 509 510 /* De-assert UTMIP_RESET to bring out of reset. */ 511 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); 512 513 /* Wait for the phy clock to become valid in 100 ms */ 514 for (loop_count = 100000; loop_count != 0; loop_count--) { 515 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 516 break; 517 udelay(1); 518 } 519 if (!loop_count) 520 return -ETIMEDOUT; 521 522 /* Disable ICUSB FS/LS transceiver */ 523 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); 524 525 /* Select UTMI parallel interface */ 526 init_phy_mux(config, PTS_UTMI, init); 527 528 /* Deassert power down state */ 529 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | 530 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); 531 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | 532 UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); 533 534 if (controller->has_hostpc) { 535 /* 536 * BIAS Pad Power Down is common among all 3 USB 537 * controllers and can be controlled from USB1 only. 538 */ 539 usb1ctlr = (struct usb_ctlr *) 540 ((unsigned long)config->reg & USB1_ADDR_MASK); 541 clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD); 542 udelay(25); 543 clrbits_le32(&usb1ctlr->utmip_bias_cfg1, 544 UTMIP_FORCE_PDTRK_POWERDOWN); 545 } 546 return 0; 547 } 548 549 #ifdef CONFIG_USB_ULPI 550 /* if board file does not set a ULPI reference frequency we default to 24MHz */ 551 #ifndef CONFIG_ULPI_REF_CLK 552 #define CONFIG_ULPI_REF_CLK 24000000 553 #endif 554 555 /* set up the ULPI USB controller with the parameters provided */ 556 static int init_ulpi_usb_controller(struct fdt_usb *config, 557 enum usb_init_type init) 558 { 559 u32 val; 560 int loop_count; 561 struct ulpi_viewport ulpi_vp; 562 struct usb_ctlr *usbctlr = config->reg; 563 int ret; 564 565 /* set up ULPI reference clock on pllp_out4 */ 566 clock_enable(PERIPH_ID_DEV2_OUT); 567 clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK); 568 569 /* reset ULPI phy */ 570 if (dm_gpio_is_valid(&config->phy_reset_gpio)) { 571 dm_gpio_set_value(&config->phy_reset_gpio, 0); 572 mdelay(5); 573 dm_gpio_set_value(&config->phy_reset_gpio, 1); 574 } 575 576 /* Reset the usb controller */ 577 clock_enable(config->periph_id); 578 usbf_reset_controller(config, usbctlr); 579 580 /* enable pinmux bypass */ 581 setbits_le32(&usbctlr->ulpi_timing_ctrl_0, 582 ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); 583 584 /* Select ULPI parallel interface */ 585 init_phy_mux(config, PTS_ULPI, init); 586 587 /* enable ULPI transceiver */ 588 setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); 589 590 /* configure ULPI transceiver timings */ 591 val = 0; 592 writel(val, &usbctlr->ulpi_timing_ctrl_1); 593 594 val |= ULPI_DATA_TRIMMER_SEL(4); 595 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); 596 val |= ULPI_DIR_TRIMMER_SEL(4); 597 writel(val, &usbctlr->ulpi_timing_ctrl_1); 598 udelay(10); 599 600 val |= ULPI_DATA_TRIMMER_LOAD; 601 val |= ULPI_STPDIRNXT_TRIMMER_LOAD; 602 val |= ULPI_DIR_TRIMMER_LOAD; 603 writel(val, &usbctlr->ulpi_timing_ctrl_1); 604 605 /* set up phy for host operation with external vbus supply */ 606 ulpi_vp.port_num = 0; 607 ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport; 608 609 ret = ulpi_init(&ulpi_vp); 610 if (ret) { 611 printf("Tegra ULPI viewport init failed\n"); 612 return ret; 613 } 614 615 ulpi_set_vbus(&ulpi_vp, 1, 1); 616 ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0); 617 618 /* enable wakeup events */ 619 setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC); 620 621 /* Enable and wait for the phy clock to become valid in 100 ms */ 622 setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 623 for (loop_count = 100000; loop_count != 0; loop_count--) { 624 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) 625 break; 626 udelay(1); 627 } 628 if (!loop_count) 629 return -ETIMEDOUT; 630 clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); 631 632 return 0; 633 } 634 #else 635 static int init_ulpi_usb_controller(struct fdt_usb *config, 636 enum usb_init_type init) 637 { 638 printf("No code to set up ULPI controller, please enable" 639 "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT"); 640 return -ENOSYS; 641 } 642 #endif 643 644 static void config_clock(const u32 timing[]) 645 { 646 clock_start_pll(CLOCK_ID_USB, 647 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], 648 timing[PARAM_CPCON], timing[PARAM_LFCON]); 649 } 650 651 static int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config) 652 { 653 const char *phy, *mode; 654 655 config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg"); 656 mode = fdt_getprop(blob, node, "dr_mode", NULL); 657 if (mode) { 658 if (0 == strcmp(mode, "host")) 659 config->dr_mode = DR_MODE_HOST; 660 else if (0 == strcmp(mode, "peripheral")) 661 config->dr_mode = DR_MODE_DEVICE; 662 else if (0 == strcmp(mode, "otg")) 663 config->dr_mode = DR_MODE_OTG; 664 else { 665 debug("%s: Cannot decode dr_mode '%s'\n", __func__, 666 mode); 667 return -EINVAL; 668 } 669 } else { 670 config->dr_mode = DR_MODE_HOST; 671 } 672 673 phy = fdt_getprop(blob, node, "phy_type", NULL); 674 config->utmi = phy && 0 == strcmp("utmi", phy); 675 config->ulpi = phy && 0 == strcmp("ulpi", phy); 676 config->enabled = fdtdec_get_is_enabled(blob, node); 677 config->has_legacy_mode = fdtdec_get_bool(blob, node, 678 "nvidia,has-legacy-mode"); 679 config->periph_id = clock_decode_periph_id(blob, node); 680 if (config->periph_id == PERIPH_ID_NONE) { 681 debug("%s: Missing/invalid peripheral ID\n", __func__); 682 return -EINVAL; 683 } 684 gpio_request_by_name_nodev(blob, node, "nvidia,vbus-gpio", 0, 685 &config->vbus_gpio, GPIOD_IS_OUT); 686 gpio_request_by_name_nodev(blob, node, "nvidia,phy-reset-gpio", 0, 687 &config->phy_reset_gpio, GPIOD_IS_OUT); 688 debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, " 689 "vbus=%d, phy_reset=%d, dr_mode=%d\n", 690 config->enabled, config->has_legacy_mode, config->utmi, 691 config->ulpi, config->periph_id, 692 gpio_get_number(&config->vbus_gpio), 693 gpio_get_number(&config->phy_reset_gpio), config->dr_mode); 694 695 return 0; 696 } 697 698 int usb_common_init(struct fdt_usb *config, enum usb_init_type init) 699 { 700 int ret = 0; 701 702 switch (init) { 703 case USB_INIT_HOST: 704 switch (config->dr_mode) { 705 case DR_MODE_HOST: 706 case DR_MODE_OTG: 707 break; 708 default: 709 printf("tegrausb: Invalid dr_mode %d for host mode\n", 710 config->dr_mode); 711 return -1; 712 } 713 break; 714 case USB_INIT_DEVICE: 715 if (config->periph_id != PERIPH_ID_USBD) { 716 printf("tegrausb: Device mode only supported on first USB controller\n"); 717 return -1; 718 } 719 if (!config->utmi) { 720 printf("tegrausb: Device mode only supported with UTMI PHY\n"); 721 return -1; 722 } 723 switch (config->dr_mode) { 724 case DR_MODE_DEVICE: 725 case DR_MODE_OTG: 726 break; 727 default: 728 printf("tegrausb: Invalid dr_mode %d for device mode\n", 729 config->dr_mode); 730 return -1; 731 } 732 break; 733 default: 734 printf("tegrausb: Unknown USB_INIT_* %d\n", init); 735 return -1; 736 } 737 738 debug("%d, %d\n", config->utmi, config->ulpi); 739 if (config->utmi) 740 ret = init_utmi_usb_controller(config, init); 741 else if (config->ulpi) 742 ret = init_ulpi_usb_controller(config, init); 743 if (ret) 744 return ret; 745 746 set_up_vbus(config, init); 747 748 config->init_type = init; 749 750 return 0; 751 } 752 753 void usb_common_uninit(struct fdt_usb *priv) 754 { 755 struct usb_ctlr *usbctlr; 756 757 usbctlr = priv->reg; 758 759 /* Stop controller */ 760 writel(0, &usbctlr->usb_cmd); 761 udelay(1000); 762 763 /* Initiate controller reset */ 764 writel(2, &usbctlr->usb_cmd); 765 udelay(1000); 766 } 767 768 static const struct ehci_ops tegra_ehci_ops = { 769 .set_usb_mode = tegra_ehci_set_usbmode, 770 .get_port_speed = tegra_ehci_get_port_speed, 771 .powerup_fixup = tegra_ehci_powerup_fixup, 772 }; 773 774 static int ehci_usb_ofdata_to_platdata(struct udevice *dev) 775 { 776 struct fdt_usb *priv = dev_get_priv(dev); 777 int ret; 778 779 ret = fdt_decode_usb(gd->fdt_blob, dev->of_offset, priv); 780 if (ret) 781 return ret; 782 783 priv->type = dev_get_driver_data(dev); 784 785 return 0; 786 } 787 788 static int ehci_usb_probe(struct udevice *dev) 789 { 790 struct usb_platdata *plat = dev_get_platdata(dev); 791 struct fdt_usb *priv = dev_get_priv(dev); 792 struct ehci_hccr *hccr; 793 struct ehci_hcor *hcor; 794 static bool clk_done; 795 int ret; 796 797 ret = usb_common_init(priv, plat->init_type); 798 if (ret) 799 return ret; 800 hccr = (struct ehci_hccr *)&priv->reg->cap_length; 801 hcor = (struct ehci_hcor *)&priv->reg->usb_cmd; 802 if (!clk_done) { 803 config_clock(get_pll_timing(&fdt_usb_controllers[priv->type])); 804 clk_done = true; 805 } 806 807 return ehci_register(dev, hccr, hcor, &tegra_ehci_ops, 0, 808 plat->init_type); 809 } 810 811 static int ehci_usb_remove(struct udevice *dev) 812 { 813 int ret; 814 815 ret = ehci_deregister(dev); 816 if (ret) 817 return ret; 818 819 return 0; 820 } 821 822 static const struct udevice_id ehci_usb_ids[] = { 823 { .compatible = "nvidia,tegra20-ehci", .data = USB_CTLR_T20 }, 824 { .compatible = "nvidia,tegra30-ehci", .data = USB_CTLR_T30 }, 825 { .compatible = "nvidia,tegra114-ehci", .data = USB_CTLR_T114 }, 826 { } 827 }; 828 829 U_BOOT_DRIVER(usb_ehci) = { 830 .name = "ehci_tegra", 831 .id = UCLASS_USB, 832 .of_match = ehci_usb_ids, 833 .ofdata_to_platdata = ehci_usb_ofdata_to_platdata, 834 .probe = ehci_usb_probe, 835 .remove = ehci_usb_remove, 836 .ops = &ehci_usb_ops, 837 .platdata_auto_alloc_size = sizeof(struct usb_platdata), 838 .priv_auto_alloc_size = sizeof(struct fdt_usb), 839 .flags = DM_FLAG_ALLOC_PRIV_DMA, 840 }; 841