1 /* 2 * EHCI HCD (Host Controller Driver) for USB. 3 * 4 * Copyright (C) 2013,2014 Renesas Electronics Corporation 5 * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0 8 */ 9 10 #include <common.h> 11 #include <asm/io.h> 12 #include <asm/arch/ehci-rmobile.h> 13 #include "ehci.h" 14 15 #if defined(CONFIG_R8A7740) 16 static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = { 17 0xC6700000 18 }; 19 #elif defined(CONFIG_R8A7790) 20 static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = { 21 0xEE080000, /* USB0 (EHCI) */ 22 0xEE0A0000, /* USB1 */ 23 0xEE0C0000, /* USB2 */ 24 0xEE000000 /* USB3 (USB3.0 Host)*/ 25 }; 26 #elif defined(CONFIG_R8A7791) 27 static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = { 28 0xEE080000, /* USB0 (EHCI) */ 29 0xEE0C0000, /* USB1 */ 30 0xEE000000 /* USB3 (USB3.0 Host)*/ 31 }; 32 #else 33 #error rmobile EHCI USB driver not supported on this platform 34 #endif 35 36 int ehci_hcd_stop(int index) 37 { 38 int i; 39 u32 base; 40 struct ahbcom_pci_bridge *ahbcom_pci; 41 42 base = usb_base_address[index]; 43 ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET); 44 writel(0, &ahbcom_pci->ahb_bus_ctr); 45 46 /* reset ehci */ 47 setbits_le32(base + EHCI_USBCMD, CMD_RESET); 48 for (i = 100; i > 0; i--) { 49 if (!(readl(base + EHCI_USBCMD) & CMD_RESET)) 50 break; 51 udelay(100); 52 } 53 54 if (!i) 55 printf("error : ehci(%d) reset failed.\n", index); 56 57 if (index == (CONFIG_USB_MAX_CONTROLLER_COUNT - 1)) 58 setbits_le32(SMSTPCR7, SMSTPCR703); 59 60 return 0; 61 } 62 63 int ehci_hcd_init(int index, enum usb_init_type init, 64 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 65 { 66 u32 base; 67 u32 phys_base; 68 struct rmobile_ehci_reg *rehci; 69 struct ahbcom_pci_bridge *ahbcom_pci; 70 struct ahbconf_pci_bridge *ahbconf_pci; 71 struct ahb_pciconf *ahb_pciconf_ohci; 72 struct ahb_pciconf *ahb_pciconf_ehci; 73 uint32_t cap_base; 74 75 base = usb_base_address[index]; 76 phys_base = base; 77 if (index == 0) 78 clrbits_le32(SMSTPCR7, SMSTPCR703); 79 80 rehci = (struct rmobile_ehci_reg *)(base + EHCI_OFFSET); 81 ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET); 82 ahbconf_pci = 83 (struct ahbconf_pci_bridge *)(base + PCI_CONF_AHBPCI_OFFSET); 84 ahb_pciconf_ohci = (struct ahb_pciconf *)(base + PCI_CONF_OHCI_OFFSET); 85 ahb_pciconf_ehci = (struct ahb_pciconf *)(base + PCI_CONF_EHCI_OFFSET); 86 87 /* Clock & Reset & Direct Power Down */ 88 clrsetbits_le32(&ahbcom_pci->usbctr, 89 (DIRPD | PCICLK_MASK | USBH_RST), USBCTR_WIN_SIZE_1GB); 90 clrbits_le32(&ahbcom_pci->usbctr, PLL_RST); 91 92 /* AHB-PCI Bridge Communication Registers */ 93 writel(AHB_BUS_CTR_INIT, &ahbcom_pci->ahb_bus_ctr); 94 writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH, 95 &ahbcom_pci->pciahb_win1_ctr); 96 writel(0xf0000000 | PCIAHB_WIN_PREFETCH, 97 &ahbcom_pci->pciahb_win2_ctr); 98 writel(phys_base | PCIWIN2_PCICMD, &ahbcom_pci->ahbpci_win2_ctr); 99 100 setbits_le32(&ahbcom_pci->pci_arbiter_ctr, 101 PCIBP_MODE | PCIREQ1 | PCIREQ0); 102 103 /* PCI Configuration Registers for AHBPCI */ 104 writel(PCIWIN1_PCICMD | AHB_CFG_AHBPCI, 105 &ahbcom_pci->ahbpci_win1_ctr); 106 writel(phys_base + AHBPCI_OFFSET, &ahbconf_pci->basead); 107 writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead); 108 writel(0xf0000000, &ahbconf_pci->win2_basead); 109 writel(SERREN | PERREN | MASTEREN | MEMEN, 110 &ahbconf_pci->cmnd_sts); 111 112 /* PCI Configuration Registers for EHCI */ 113 writel(PCIWIN1_PCICMD | AHB_CFG_HOST, &ahbcom_pci->ahbpci_win1_ctr); 114 writel(phys_base + OHCI_OFFSET, &ahb_pciconf_ohci->basead); 115 writel(phys_base + EHCI_OFFSET, &ahb_pciconf_ehci->basead); 116 writel(SERREN | PERREN | MASTEREN | MEMEN, 117 &ahb_pciconf_ohci->cmnd_sts); 118 writel(SERREN | PERREN | MASTEREN | MEMEN, 119 &ahb_pciconf_ehci->cmnd_sts); 120 121 /* Enable PCI interrupt */ 122 setbits_le32(&ahbcom_pci->pci_int_enable, 123 USBH_PMEEN | USBH_INTBEN | USBH_INTAEN); 124 125 *hccr = (struct ehci_hccr *)((uint32_t)&rehci->hciversion); 126 cap_base = ehci_readl(&(*hccr)->cr_capbase); 127 *hcor = (struct ehci_hcor *)((uint32_t)*hccr + HC_LENGTH(cap_base)); 128 129 return 0; 130 } 131