1 /* 2 * EHCI HCD (Host Controller Driver) for USB. 3 * 4 * Copyright (C) 2013,2014 Renesas Electronics Corporation 5 * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0 8 */ 9 10 #include <common.h> 11 #include <asm/io.h> 12 #include <asm/arch/ehci-rmobile.h> 13 #include "ehci.h" 14 15 #if defined(CONFIG_R8A7740) 16 static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = { 17 0xC6700000 18 }; 19 #elif defined(CONFIG_R8A7790) 20 static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = { 21 0xEE080000, /* USB0 (EHCI) */ 22 0xEE0A0000, /* USB1 */ 23 0xEE0C0000, /* USB2 */ 24 }; 25 #elif defined(CONFIG_R8A7791) 26 static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = { 27 0xEE080000, /* USB0 (EHCI) */ 28 0xEE0C0000, /* USB1 */ 29 }; 30 #elif defined(CONFIG_R8A7794) 31 static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = { 32 0xEE080000, /* USB0 (EHCI) */ 33 0xEE0C0000, /* USB1 */ 34 }; 35 #else 36 #error rmobile EHCI USB driver not supported on this platform 37 #endif 38 39 int ehci_hcd_stop(int index) 40 { 41 int i; 42 u32 base; 43 struct ahbcom_pci_bridge *ahbcom_pci; 44 45 base = usb_base_address[index]; 46 ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET); 47 writel(0, &ahbcom_pci->ahb_bus_ctr); 48 49 /* reset ehci */ 50 setbits_le32(base + EHCI_USBCMD, CMD_RESET); 51 for (i = 100; i > 0; i--) { 52 if (!(readl(base + EHCI_USBCMD) & CMD_RESET)) 53 break; 54 udelay(100); 55 } 56 57 if (!i) 58 printf("error : ehci(%d) reset failed.\n", index); 59 60 if (index == (CONFIG_USB_MAX_CONTROLLER_COUNT - 1)) 61 setbits_le32(SMSTPCR7, SMSTPCR703); 62 63 return 0; 64 } 65 66 int ehci_hcd_init(int index, enum usb_init_type init, 67 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 68 { 69 u32 base; 70 u32 phys_base; 71 struct rmobile_ehci_reg *rehci; 72 struct ahbcom_pci_bridge *ahbcom_pci; 73 struct ahbconf_pci_bridge *ahbconf_pci; 74 struct ahb_pciconf *ahb_pciconf_ohci; 75 struct ahb_pciconf *ahb_pciconf_ehci; 76 uint32_t cap_base; 77 78 base = usb_base_address[index]; 79 phys_base = base; 80 if (index == 0) 81 clrbits_le32(SMSTPCR7, SMSTPCR703); 82 83 rehci = (struct rmobile_ehci_reg *)(base + EHCI_OFFSET); 84 ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET); 85 ahbconf_pci = 86 (struct ahbconf_pci_bridge *)(base + PCI_CONF_AHBPCI_OFFSET); 87 ahb_pciconf_ohci = (struct ahb_pciconf *)(base + PCI_CONF_OHCI_OFFSET); 88 ahb_pciconf_ehci = (struct ahb_pciconf *)(base + PCI_CONF_EHCI_OFFSET); 89 90 /* Clock & Reset & Direct Power Down */ 91 clrsetbits_le32(&ahbcom_pci->usbctr, 92 (DIRPD | PCICLK_MASK | USBH_RST), USBCTR_WIN_SIZE_1GB); 93 clrbits_le32(&ahbcom_pci->usbctr, PLL_RST); 94 95 /* AHB-PCI Bridge Communication Registers */ 96 writel(AHB_BUS_CTR_INIT, &ahbcom_pci->ahb_bus_ctr); 97 writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH, 98 &ahbcom_pci->pciahb_win1_ctr); 99 writel(0xf0000000 | PCIAHB_WIN_PREFETCH, 100 &ahbcom_pci->pciahb_win2_ctr); 101 writel(phys_base | PCIWIN2_PCICMD, &ahbcom_pci->ahbpci_win2_ctr); 102 103 setbits_le32(&ahbcom_pci->pci_arbiter_ctr, 104 PCIBP_MODE | PCIREQ1 | PCIREQ0); 105 106 /* PCI Configuration Registers for AHBPCI */ 107 writel(PCIWIN1_PCICMD | AHB_CFG_AHBPCI, 108 &ahbcom_pci->ahbpci_win1_ctr); 109 writel(phys_base + AHBPCI_OFFSET, &ahbconf_pci->basead); 110 writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead); 111 writel(0xf0000000, &ahbconf_pci->win2_basead); 112 writel(SERREN | PERREN | MASTEREN | MEMEN, 113 &ahbconf_pci->cmnd_sts); 114 115 /* PCI Configuration Registers for EHCI */ 116 writel(PCIWIN1_PCICMD | AHB_CFG_HOST, &ahbcom_pci->ahbpci_win1_ctr); 117 writel(phys_base + OHCI_OFFSET, &ahb_pciconf_ohci->basead); 118 writel(phys_base + EHCI_OFFSET, &ahb_pciconf_ehci->basead); 119 writel(SERREN | PERREN | MASTEREN | MEMEN, 120 &ahb_pciconf_ohci->cmnd_sts); 121 writel(SERREN | PERREN | MASTEREN | MEMEN, 122 &ahb_pciconf_ehci->cmnd_sts); 123 124 /* Enable PCI interrupt */ 125 setbits_le32(&ahbcom_pci->pci_int_enable, 126 USBH_PMEEN | USBH_INTBEN | USBH_INTAEN); 127 128 *hccr = (struct ehci_hccr *)((uint32_t)&rehci->hciversion); 129 cap_base = ehci_readl(&(*hccr)->cr_capbase); 130 *hcor = (struct ehci_hcor *)((uint32_t)*hccr + HC_LENGTH(cap_base)); 131 132 return 0; 133 } 134