1 /* 2 * (C) Copyright 2011 Ilya Yanok, Emcraft Systems 3 * (C) Copyright 2004-2008 4 * Texas Instruments, <www.ti.com> 5 * 6 * Derived from Beagle Board code by 7 * Sunil Kumar <sunilsaini05@gmail.com> 8 * Shashi Ranjan <shashiranjanmca05@gmail.com> 9 * 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <usb.h> 16 #include <usb/ulpi.h> 17 #include <errno.h> 18 #include <asm/io.h> 19 #include <asm/gpio.h> 20 #include <asm/arch/ehci.h> 21 #include <asm/ehci-omap.h> 22 23 #include "ehci.h" 24 25 static struct omap_uhh *const uhh = (struct omap_uhh *)OMAP_UHH_BASE; 26 static struct omap_usbtll *const usbtll = (struct omap_usbtll *)OMAP_USBTLL_BASE; 27 static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE; 28 29 static int omap_uhh_reset(void) 30 { 31 /* 32 * Soft resetting the UHH module causes instability issues on 33 * all OMAPs so we just avoid it. 34 * 35 * See OMAP36xx Errata 36 * i571: USB host EHCI may stall when entering smart-standby mode 37 * i660: USBHOST Configured In Smart-Idle Can Lead To a Deadlock 38 * 39 * On OMAP4/5, soft-resetting the UHH module will put it into 40 * Smart-Idle mode and lead to a deadlock. 41 * 42 * On OMAP3, this doesn't seem to be the case but still instabilities 43 * are observed on beagle (3530 ES1.0) if soft-reset is used. 44 * e.g. NFS root failures with Linux kernel. 45 */ 46 return 0; 47 } 48 49 static int omap_ehci_tll_reset(void) 50 { 51 unsigned long init = get_timer(0); 52 53 /* perform TLL soft reset, and wait until reset is complete */ 54 writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, &usbtll->sysc); 55 56 /* Wait for TLL reset to complete */ 57 while (!(readl(&usbtll->syss) & OMAP_USBTLL_SYSSTATUS_RESETDONE)) 58 if (get_timer(init) > CONFIG_SYS_HZ) { 59 debug("OMAP EHCI error: timeout resetting TLL\n"); 60 return -EL3RST; 61 } 62 63 return 0; 64 } 65 66 static void omap_usbhs_hsic_init(int port) 67 { 68 unsigned int reg; 69 70 /* Enable channels now */ 71 reg = readl(&usbtll->channel_conf + port); 72 73 setbits_le32(®, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI 74 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF 75 | OMAP_TLL_CHANNEL_CONF_DRVVBUS 76 | OMAP_TLL_CHANNEL_CONF_CHRGVBUS 77 | OMAP_TLL_CHANNEL_CONF_CHANEN)); 78 79 writel(reg, &usbtll->channel_conf + port); 80 } 81 82 #ifdef CONFIG_USB_ULPI 83 static void omap_ehci_soft_phy_reset(int port) 84 { 85 struct ulpi_viewport ulpi_vp; 86 87 ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi; 88 ulpi_vp.port_num = port; 89 90 ulpi_reset(&ulpi_vp); 91 } 92 #else 93 static void omap_ehci_soft_phy_reset(int port) 94 { 95 return; 96 } 97 #endif 98 99 inline int __board_usb_init(void) 100 { 101 return 0; 102 } 103 int board_usb_init(void) __attribute__((weak, alias("__board_usb_init"))); 104 105 #if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \ 106 defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) || \ 107 defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO) 108 /* controls PHY(s) reset signal(s) */ 109 static inline void omap_ehci_phy_reset(int on, int delay) 110 { 111 /* 112 * Refer ISSUE1: 113 * Hold the PHY in RESET for enough time till 114 * PHY is settled and ready 115 */ 116 if (delay && !on) 117 udelay(delay); 118 #ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 119 gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset"); 120 gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on); 121 #endif 122 #ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 123 gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset"); 124 gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on); 125 #endif 126 #ifdef CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 127 gpio_request(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, "USB PHY3 reset"); 128 gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, !on); 129 #endif 130 131 /* Hold the PHY in RESET for enough time till DIR is high */ 132 /* Refer: ISSUE1 */ 133 if (delay && on) 134 udelay(delay); 135 } 136 #else 137 #define omap_ehci_phy_reset(on, delay) do {} while (0) 138 #endif 139 140 /* Reset is needed otherwise the kernel-driver will throw an error. */ 141 int omap_ehci_hcd_stop(void) 142 { 143 debug("Resetting OMAP EHCI\n"); 144 omap_ehci_phy_reset(1, 0); 145 146 if (omap_uhh_reset() < 0) 147 return -1; 148 149 if (omap_ehci_tll_reset() < 0) 150 return -1; 151 152 return 0; 153 } 154 155 /* 156 * Initialize the OMAP EHCI controller and PHY. 157 * Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1 158 * See there for additional Copyrights. 159 */ 160 int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata, 161 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 162 { 163 int ret; 164 unsigned int i, reg = 0, rev = 0; 165 166 debug("Initializing OMAP EHCI\n"); 167 168 ret = board_usb_init(); 169 if (ret < 0) 170 return ret; 171 172 /* Put the PHY in RESET */ 173 omap_ehci_phy_reset(1, 10); 174 175 ret = omap_uhh_reset(); 176 if (ret < 0) 177 return ret; 178 179 ret = omap_ehci_tll_reset(); 180 if (ret) 181 return ret; 182 183 writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP | 184 OMAP_USBTLL_SYSCONFIG_SIDLEMODE | 185 OMAP_USBTLL_SYSCONFIG_CACTIVITY, &usbtll->sysc); 186 187 /* Put UHH in NoIdle/NoStandby mode */ 188 writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc); 189 190 /* setup ULPI bypass and burst configurations */ 191 clrsetbits_le32(®, OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN, 192 (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN | 193 OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN | 194 OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN)); 195 196 rev = readl(&uhh->rev); 197 if (rev == OMAP_USBHS_REV1) { 198 if (is_ehci_phy_mode(usbhs_pdata->port_mode[0])) 199 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS); 200 else 201 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS); 202 203 if (is_ehci_phy_mode(usbhs_pdata->port_mode[1])) 204 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS); 205 else 206 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS); 207 208 if (is_ehci_phy_mode(usbhs_pdata->port_mode[2])) 209 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS); 210 else 211 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS); 212 } else if (rev == OMAP_USBHS_REV2) { 213 214 clrsetbits_le32(®, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR), 215 OMAP4_UHH_HOSTCONFIG_APP_START_CLK); 216 217 /* Clear port mode fields for PHY mode */ 218 219 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0])) 220 setbits_le32(®, OMAP_P1_MODE_HSIC); 221 222 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1])) 223 setbits_le32(®, OMAP_P2_MODE_HSIC); 224 225 } else if (rev == OMAP_USBHS_REV2_1) { 226 227 clrsetbits_le32(®, 228 (OMAP_P1_MODE_CLEAR | 229 OMAP_P2_MODE_CLEAR | 230 OMAP_P3_MODE_CLEAR), 231 OMAP4_UHH_HOSTCONFIG_APP_START_CLK); 232 233 /* Clear port mode fields for PHY mode */ 234 235 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0])) 236 setbits_le32(®, OMAP_P1_MODE_HSIC); 237 238 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1])) 239 setbits_le32(®, OMAP_P2_MODE_HSIC); 240 241 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[2])) 242 setbits_le32(®, OMAP_P3_MODE_HSIC); 243 } 244 245 debug("OMAP UHH_REVISION 0x%x\n", rev); 246 writel(reg, &uhh->hostconfig); 247 248 for (i = 0; i < OMAP_HS_USB_PORTS; i++) 249 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i])) 250 omap_usbhs_hsic_init(i); 251 252 omap_ehci_phy_reset(0, 10); 253 254 /* 255 * An undocumented "feature" in the OMAP3 EHCI controller, 256 * causes suspended ports to be taken out of suspend when 257 * the USBCMD.Run/Stop bit is cleared (for example when 258 * we do ehci_bus_suspend). 259 * This breaks suspend-resume if the root-hub is allowed 260 * to suspend. Writing 1 to this undocumented register bit 261 * disables this feature and restores normal behavior. 262 */ 263 writel(EHCI_INSNREG04_DISABLE_UNSUSPEND, &ehci->insreg04); 264 265 for (i = 0; i < OMAP_HS_USB_PORTS; i++) 266 if (is_ehci_phy_mode(usbhs_pdata->port_mode[i])) 267 omap_ehci_soft_phy_reset(i); 268 269 *hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE); 270 *hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10); 271 272 debug("OMAP EHCI init done\n"); 273 return 0; 274 } 275