1 /* 2 * (C) Copyright 2011 Ilya Yanok, Emcraft Systems 3 * (C) Copyright 2004-2008 4 * Texas Instruments, <www.ti.com> 5 * 6 * Derived from Beagle Board code by 7 * Sunil Kumar <sunilsaini05@gmail.com> 8 * Shashi Ranjan <shashiranjanmca05@gmail.com> 9 * 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <usb.h> 16 #include <usb/ulpi.h> 17 #include <errno.h> 18 #include <asm/io.h> 19 #include <asm/gpio.h> 20 #include <asm/arch/ehci.h> 21 #include <asm/ehci-omap.h> 22 23 #include "ehci.h" 24 25 static struct omap_uhh *const uhh = (struct omap_uhh *)OMAP_UHH_BASE; 26 static struct omap_usbtll *const usbtll = (struct omap_usbtll *)OMAP_USBTLL_BASE; 27 static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE; 28 29 static int omap_uhh_reset(void) 30 { 31 /* 32 * Soft resetting the UHH module causes instability issues on 33 * all OMAPs so we just avoid it. 34 * 35 * See OMAP36xx Errata 36 * i571: USB host EHCI may stall when entering smart-standby mode 37 * i660: USBHOST Configured In Smart-Idle Can Lead To a Deadlock 38 * 39 * On OMAP4/5, soft-resetting the UHH module will put it into 40 * Smart-Idle mode and lead to a deadlock. 41 * 42 * On OMAP3, this doesn't seem to be the case but still instabilities 43 * are observed on beagle (3530 ES1.0) if soft-reset is used. 44 * e.g. NFS root failures with Linux kernel. 45 */ 46 return 0; 47 } 48 49 static int omap_ehci_tll_reset(void) 50 { 51 unsigned long init = get_timer(0); 52 53 /* perform TLL soft reset, and wait until reset is complete */ 54 writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, &usbtll->sysc); 55 56 /* Wait for TLL reset to complete */ 57 while (!(readl(&usbtll->syss) & OMAP_USBTLL_SYSSTATUS_RESETDONE)) 58 if (get_timer(init) > CONFIG_SYS_HZ) { 59 debug("OMAP EHCI error: timeout resetting TLL\n"); 60 return -EL3RST; 61 } 62 63 return 0; 64 } 65 66 static void omap_usbhs_hsic_init(int port) 67 { 68 unsigned int reg; 69 70 /* Enable channels now */ 71 reg = readl(&usbtll->channel_conf + port); 72 73 setbits_le32(®, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI 74 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF 75 | OMAP_TLL_CHANNEL_CONF_DRVVBUS 76 | OMAP_TLL_CHANNEL_CONF_CHRGVBUS 77 | OMAP_TLL_CHANNEL_CONF_CHANEN)); 78 79 writel(reg, &usbtll->channel_conf + port); 80 } 81 82 #ifdef CONFIG_USB_ULPI 83 static void omap_ehci_soft_phy_reset(int port) 84 { 85 struct ulpi_viewport ulpi_vp; 86 87 ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi; 88 ulpi_vp.port_num = port; 89 90 ulpi_reset(&ulpi_vp); 91 } 92 #else 93 static void omap_ehci_soft_phy_reset(int port) 94 { 95 return; 96 } 97 #endif 98 99 #if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \ 100 defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) || \ 101 defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO) 102 /* controls PHY(s) reset signal(s) */ 103 static inline void omap_ehci_phy_reset(int on, int delay) 104 { 105 /* 106 * Refer ISSUE1: 107 * Hold the PHY in RESET for enough time till 108 * PHY is settled and ready 109 */ 110 if (delay && !on) 111 udelay(delay); 112 #ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 113 gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset"); 114 gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on); 115 #endif 116 #ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 117 gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset"); 118 gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on); 119 #endif 120 #ifdef CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 121 gpio_request(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, "USB PHY3 reset"); 122 gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, !on); 123 #endif 124 125 /* Hold the PHY in RESET for enough time till DIR is high */ 126 /* Refer: ISSUE1 */ 127 if (delay && on) 128 udelay(delay); 129 } 130 #else 131 #define omap_ehci_phy_reset(on, delay) do {} while (0) 132 #endif 133 134 /* Reset is needed otherwise the kernel-driver will throw an error. */ 135 int omap_ehci_hcd_stop(void) 136 { 137 debug("Resetting OMAP EHCI\n"); 138 omap_ehci_phy_reset(1, 0); 139 140 if (omap_uhh_reset() < 0) 141 return -1; 142 143 if (omap_ehci_tll_reset() < 0) 144 return -1; 145 146 return 0; 147 } 148 149 /* 150 * Initialize the OMAP EHCI controller and PHY. 151 * Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1 152 * See there for additional Copyrights. 153 */ 154 int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata, 155 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 156 { 157 int ret; 158 unsigned int i, reg = 0, rev = 0; 159 160 debug("Initializing OMAP EHCI\n"); 161 162 ret = board_usb_init(index, USB_INIT_HOST); 163 if (ret < 0) 164 return ret; 165 166 /* Put the PHY in RESET */ 167 omap_ehci_phy_reset(1, 10); 168 169 ret = omap_uhh_reset(); 170 if (ret < 0) 171 return ret; 172 173 ret = omap_ehci_tll_reset(); 174 if (ret) 175 return ret; 176 177 writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP | 178 OMAP_USBTLL_SYSCONFIG_SIDLEMODE | 179 OMAP_USBTLL_SYSCONFIG_CACTIVITY, &usbtll->sysc); 180 181 /* Put UHH in NoIdle/NoStandby mode */ 182 writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc); 183 184 /* setup ULPI bypass and burst configurations */ 185 clrsetbits_le32(®, OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN, 186 (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN | 187 OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN | 188 OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN)); 189 190 rev = readl(&uhh->rev); 191 if (rev == OMAP_USBHS_REV1) { 192 if (is_ehci_phy_mode(usbhs_pdata->port_mode[0])) 193 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS); 194 else 195 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS); 196 197 if (is_ehci_phy_mode(usbhs_pdata->port_mode[1])) 198 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS); 199 else 200 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS); 201 202 if (is_ehci_phy_mode(usbhs_pdata->port_mode[2])) 203 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS); 204 else 205 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS); 206 } else if (rev == OMAP_USBHS_REV2) { 207 208 clrsetbits_le32(®, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR), 209 OMAP4_UHH_HOSTCONFIG_APP_START_CLK); 210 211 /* Clear port mode fields for PHY mode */ 212 213 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0])) 214 setbits_le32(®, OMAP_P1_MODE_HSIC); 215 216 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1])) 217 setbits_le32(®, OMAP_P2_MODE_HSIC); 218 219 } else if (rev == OMAP_USBHS_REV2_1) { 220 221 clrsetbits_le32(®, 222 (OMAP_P1_MODE_CLEAR | 223 OMAP_P2_MODE_CLEAR | 224 OMAP_P3_MODE_CLEAR), 225 OMAP4_UHH_HOSTCONFIG_APP_START_CLK); 226 227 /* Clear port mode fields for PHY mode */ 228 229 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0])) 230 setbits_le32(®, OMAP_P1_MODE_HSIC); 231 232 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1])) 233 setbits_le32(®, OMAP_P2_MODE_HSIC); 234 235 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[2])) 236 setbits_le32(®, OMAP_P3_MODE_HSIC); 237 } 238 239 debug("OMAP UHH_REVISION 0x%x\n", rev); 240 writel(reg, &uhh->hostconfig); 241 242 for (i = 0; i < OMAP_HS_USB_PORTS; i++) 243 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i])) 244 omap_usbhs_hsic_init(i); 245 246 omap_ehci_phy_reset(0, 10); 247 248 /* 249 * An undocumented "feature" in the OMAP3 EHCI controller, 250 * causes suspended ports to be taken out of suspend when 251 * the USBCMD.Run/Stop bit is cleared (for example when 252 * we do ehci_bus_suspend). 253 * This breaks suspend-resume if the root-hub is allowed 254 * to suspend. Writing 1 to this undocumented register bit 255 * disables this feature and restores normal behavior. 256 */ 257 writel(EHCI_INSNREG04_DISABLE_UNSUSPEND, &ehci->insreg04); 258 259 for (i = 0; i < OMAP_HS_USB_PORTS; i++) 260 if (is_ehci_phy_mode(usbhs_pdata->port_mode[i])) 261 omap_ehci_soft_phy_reset(i); 262 263 *hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE); 264 *hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10); 265 266 debug("OMAP EHCI init done\n"); 267 return 0; 268 } 269