1 /* 2 * Freescale i.MX28 USB Host driver 3 * 4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 22 #include <common.h> 23 #include <asm/io.h> 24 #include <asm/arch/regs-common.h> 25 #include <asm/arch/regs-base.h> 26 #include <asm/arch/regs-clkctrl-mx28.h> 27 #include <asm/arch/regs-usb.h> 28 #include <asm/arch/regs-usbphy.h> 29 30 #include "ehci.h" 31 32 #if (CONFIG_EHCI_MXS_PORT != 0) && (CONFIG_EHCI_MXS_PORT != 1) 33 #error "MXS EHCI: Invalid port selected!" 34 #endif 35 36 #ifndef CONFIG_EHCI_MXS_PORT 37 #error "MXS EHCI: Please define correct port using CONFIG_EHCI_MXS_PORT!" 38 #endif 39 40 static struct ehci_mxs { 41 struct mxs_usb_regs *usb_regs; 42 struct mxs_usbphy_regs *phy_regs; 43 } ehci_mxs; 44 45 int mxs_ehci_get_port(struct ehci_mxs *mxs_usb, int port) 46 { 47 uint32_t usb_base, phy_base; 48 switch (port) { 49 case 0: 50 usb_base = MXS_USBCTRL0_BASE; 51 phy_base = MXS_USBPHY0_BASE; 52 break; 53 case 1: 54 usb_base = MXS_USBCTRL1_BASE; 55 phy_base = MXS_USBPHY1_BASE; 56 break; 57 default: 58 printf("CONFIG_EHCI_MXS_PORT (port = %d)\n", port); 59 return -1; 60 } 61 62 mxs_usb->usb_regs = (struct mxs_usb_regs *)usb_base; 63 mxs_usb->phy_regs = (struct mxs_usbphy_regs *)phy_base; 64 return 0; 65 } 66 67 /* This DIGCTL register ungates clock to USB */ 68 #define HW_DIGCTL_CTRL 0x8001c000 69 #define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2) 70 #define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16) 71 72 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) 73 { 74 75 int ret; 76 uint32_t usb_base, cap_base; 77 struct mxs_register_32 *digctl_ctrl = 78 (struct mxs_register_32 *)HW_DIGCTL_CTRL; 79 struct mxs_clkctrl_regs *clkctrl_regs = 80 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 81 82 ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT); 83 if (ret) 84 return ret; 85 86 /* Reset the PHY block */ 87 writel(USBPHY_CTRL_SFTRST, &ehci_mxs.phy_regs->hw_usbphy_ctrl_set); 88 udelay(10); 89 writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE, 90 &ehci_mxs.phy_regs->hw_usbphy_ctrl_clr); 91 92 /* Enable USB clock */ 93 writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER, 94 &clkctrl_regs->hw_clkctrl_pll0ctrl0_set); 95 writel(CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER, 96 &clkctrl_regs->hw_clkctrl_pll1ctrl0_set); 97 98 writel(HW_DIGCTL_CTRL_USB0_CLKGATE | HW_DIGCTL_CTRL_USB1_CLKGATE, 99 &digctl_ctrl->reg_clr); 100 101 /* Start USB PHY */ 102 writel(0, &ehci_mxs.phy_regs->hw_usbphy_pwd); 103 104 /* Enable UTMI+ Level 2 and Level 3 compatibility */ 105 writel(USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2 | 1, 106 &ehci_mxs.phy_regs->hw_usbphy_ctrl_set); 107 108 usb_base = ((uint32_t)ehci_mxs.usb_regs) + 0x100; 109 *hccr = (struct ehci_hccr *)usb_base; 110 111 cap_base = ehci_readl(&(*hccr)->cr_capbase); 112 *hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base)); 113 114 return 0; 115 } 116 117 int ehci_hcd_stop(int index) 118 { 119 int ret; 120 uint32_t usb_base, cap_base, tmp; 121 struct mxs_register_32 *digctl_ctrl = 122 (struct mxs_register_32 *)HW_DIGCTL_CTRL; 123 struct mxs_clkctrl_regs *clkctrl_regs = 124 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; 125 struct ehci_hccr *hccr; 126 struct ehci_hcor *hcor; 127 128 ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT); 129 if (ret) 130 return ret; 131 132 /* Stop the USB port */ 133 usb_base = ((uint32_t)ehci_mxs.usb_regs) + 0x100; 134 hccr = (struct ehci_hccr *)usb_base; 135 cap_base = ehci_readl(&hccr->cr_capbase); 136 hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base)); 137 138 tmp = ehci_readl(&hcor->or_usbcmd); 139 tmp &= ~CMD_RUN; 140 ehci_writel(tmp, &hcor->or_usbcmd); 141 142 /* Disable the PHY */ 143 tmp = USBPHY_PWD_RXPWDRX | USBPHY_PWD_RXPWDDIFF | 144 USBPHY_PWD_RXPWD1PT1 | USBPHY_PWD_RXPWDENV | 145 USBPHY_PWD_TXPWDV2I | USBPHY_PWD_TXPWDIBIAS | 146 USBPHY_PWD_TXPWDFS; 147 writel(tmp, &ehci_mxs.phy_regs->hw_usbphy_pwd); 148 149 /* Disable USB clock */ 150 writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS, 151 &clkctrl_regs->hw_clkctrl_pll0ctrl0_clr); 152 writel(CLKCTRL_PLL1CTRL0_EN_USB_CLKS, 153 &clkctrl_regs->hw_clkctrl_pll1ctrl0_clr); 154 155 /* Gate off the USB clock */ 156 writel(HW_DIGCTL_CTRL_USB0_CLKGATE | HW_DIGCTL_CTRL_USB1_CLKGATE, 157 &digctl_ctrl->reg_set); 158 159 return 0; 160 } 161