1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Freescale i.MX28 USB Host driver 4 * 5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 6 * on behalf of DENX Software Engineering GmbH 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <asm/arch/imx-regs.h> 12 #include <errno.h> 13 14 #include "ehci.h" 15 16 /* This DIGCTL register ungates clock to USB */ 17 #define HW_DIGCTL_CTRL 0x8001c000 18 #define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2) 19 #define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16) 20 21 struct ehci_mxs_port { 22 uint32_t usb_regs; 23 struct mxs_usbphy_regs *phy_regs; 24 25 struct mxs_register_32 *pll; 26 uint32_t pll_en_bits; 27 uint32_t pll_dis_bits; 28 uint32_t gate_bits; 29 }; 30 31 static const struct ehci_mxs_port mxs_port[] = { 32 #ifdef CONFIG_EHCI_MXS_PORT0 33 { 34 MXS_USBCTRL0_BASE, 35 (struct mxs_usbphy_regs *)MXS_USBPHY0_BASE, 36 (struct mxs_register_32 *)(MXS_CLKCTRL_BASE + 37 offsetof(struct mxs_clkctrl_regs, 38 hw_clkctrl_pll0ctrl0_reg)), 39 CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER, 40 CLKCTRL_PLL0CTRL0_EN_USB_CLKS, 41 HW_DIGCTL_CTRL_USB0_CLKGATE, 42 }, 43 #endif 44 #ifdef CONFIG_EHCI_MXS_PORT1 45 { 46 MXS_USBCTRL1_BASE, 47 (struct mxs_usbphy_regs *)MXS_USBPHY1_BASE, 48 (struct mxs_register_32 *)(MXS_CLKCTRL_BASE + 49 offsetof(struct mxs_clkctrl_regs, 50 hw_clkctrl_pll1ctrl0_reg)), 51 CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER, 52 CLKCTRL_PLL1CTRL0_EN_USB_CLKS, 53 HW_DIGCTL_CTRL_USB1_CLKGATE, 54 }, 55 #endif 56 }; 57 58 static int ehci_mxs_toggle_clock(const struct ehci_mxs_port *port, int enable) 59 { 60 struct mxs_register_32 *digctl_ctrl = 61 (struct mxs_register_32 *)HW_DIGCTL_CTRL; 62 int pll_offset, dig_offset; 63 64 if (enable) { 65 pll_offset = offsetof(struct mxs_register_32, reg_set); 66 dig_offset = offsetof(struct mxs_register_32, reg_clr); 67 writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset); 68 writel(port->pll_en_bits, (u32)port->pll + pll_offset); 69 } else { 70 pll_offset = offsetof(struct mxs_register_32, reg_clr); 71 dig_offset = offsetof(struct mxs_register_32, reg_set); 72 writel(port->pll_dis_bits, (u32)port->pll + pll_offset); 73 writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset); 74 } 75 76 return 0; 77 } 78 79 int __weak board_ehci_hcd_init(int port) 80 { 81 return 0; 82 } 83 84 int __weak board_ehci_hcd_exit(int port) 85 { 86 return 0; 87 } 88 89 int ehci_hcd_init(int index, enum usb_init_type init, 90 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 91 { 92 93 int ret; 94 uint32_t usb_base, cap_base; 95 const struct ehci_mxs_port *port; 96 97 if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) { 98 printf("Invalid port index (index = %d)!\n", index); 99 return -EINVAL; 100 } 101 102 ret = board_ehci_hcd_init(index); 103 if (ret) 104 return ret; 105 106 port = &mxs_port[index]; 107 108 /* Reset the PHY block */ 109 writel(USBPHY_CTRL_SFTRST, &port->phy_regs->hw_usbphy_ctrl_set); 110 udelay(10); 111 writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE, 112 &port->phy_regs->hw_usbphy_ctrl_clr); 113 114 /* Enable USB clock */ 115 ret = ehci_mxs_toggle_clock(port, 1); 116 if (ret) 117 return ret; 118 119 /* Start USB PHY */ 120 writel(0, &port->phy_regs->hw_usbphy_pwd); 121 122 /* Enable UTMI+ Level 2 and Level 3 compatibility */ 123 writel(USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2 | 1, 124 &port->phy_regs->hw_usbphy_ctrl_set); 125 126 usb_base = port->usb_regs + 0x100; 127 *hccr = (struct ehci_hccr *)usb_base; 128 129 cap_base = ehci_readl(&(*hccr)->cr_capbase); 130 *hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base)); 131 132 return 0; 133 } 134 135 int ehci_hcd_stop(int index) 136 { 137 int ret; 138 uint32_t usb_base, cap_base, tmp; 139 struct ehci_hccr *hccr; 140 struct ehci_hcor *hcor; 141 const struct ehci_mxs_port *port; 142 143 if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) { 144 printf("Invalid port index (index = %d)!\n", index); 145 return -EINVAL; 146 } 147 148 port = &mxs_port[index]; 149 150 /* Stop the USB port */ 151 usb_base = port->usb_regs + 0x100; 152 hccr = (struct ehci_hccr *)usb_base; 153 cap_base = ehci_readl(&hccr->cr_capbase); 154 hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base)); 155 156 tmp = ehci_readl(&hcor->or_usbcmd); 157 tmp &= ~CMD_RUN; 158 ehci_writel(&hcor->or_usbcmd, tmp); 159 160 /* Disable the PHY */ 161 tmp = USBPHY_PWD_RXPWDRX | USBPHY_PWD_RXPWDDIFF | 162 USBPHY_PWD_RXPWD1PT1 | USBPHY_PWD_RXPWDENV | 163 USBPHY_PWD_TXPWDV2I | USBPHY_PWD_TXPWDIBIAS | 164 USBPHY_PWD_TXPWDFS; 165 writel(tmp, &port->phy_regs->hw_usbphy_pwd); 166 167 /* Disable USB clock */ 168 ret = ehci_mxs_toggle_clock(port, 0); 169 170 board_ehci_hcd_exit(index); 171 172 return ret; 173 } 174