1dbb8f279SMarek Vasut /* 2dbb8f279SMarek Vasut * Freescale i.MX28 USB Host driver 3dbb8f279SMarek Vasut * 4dbb8f279SMarek Vasut * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 5dbb8f279SMarek Vasut * on behalf of DENX Software Engineering GmbH 6dbb8f279SMarek Vasut * 71a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 8dbb8f279SMarek Vasut */ 9dbb8f279SMarek Vasut 10dbb8f279SMarek Vasut #include <common.h> 11dbb8f279SMarek Vasut #include <asm/io.h> 1247f13315SMarek Vasut #include <asm/arch/imx-regs.h> 13afa87210SMarek Vasut #include <errno.h> 14dbb8f279SMarek Vasut 15dbb8f279SMarek Vasut #include "ehci.h" 16dbb8f279SMarek Vasut 17dbb8f279SMarek Vasut /* This DIGCTL register ungates clock to USB */ 18dbb8f279SMarek Vasut #define HW_DIGCTL_CTRL 0x8001c000 19dbb8f279SMarek Vasut #define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2) 20dbb8f279SMarek Vasut #define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16) 21dbb8f279SMarek Vasut 22afa87210SMarek Vasut struct ehci_mxs_port { 23afa87210SMarek Vasut uint32_t usb_regs; 24afa87210SMarek Vasut struct mxs_usbphy_regs *phy_regs; 25afa87210SMarek Vasut 26afa87210SMarek Vasut struct mxs_register_32 *pll; 27afa87210SMarek Vasut uint32_t pll_en_bits; 28afa87210SMarek Vasut uint32_t pll_dis_bits; 29afa87210SMarek Vasut uint32_t gate_bits; 30afa87210SMarek Vasut }; 31afa87210SMarek Vasut 32afa87210SMarek Vasut static const struct ehci_mxs_port mxs_port[] = { 33afa87210SMarek Vasut #ifdef CONFIG_EHCI_MXS_PORT0 34afa87210SMarek Vasut { 35afa87210SMarek Vasut MXS_USBCTRL0_BASE, 36afa87210SMarek Vasut (struct mxs_usbphy_regs *)MXS_USBPHY0_BASE, 37afa87210SMarek Vasut (struct mxs_register_32 *)(MXS_CLKCTRL_BASE + 38afa87210SMarek Vasut offsetof(struct mxs_clkctrl_regs, 39afa87210SMarek Vasut hw_clkctrl_pll0ctrl0_reg)), 40afa87210SMarek Vasut CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER, 41afa87210SMarek Vasut CLKCTRL_PLL0CTRL0_EN_USB_CLKS, 42afa87210SMarek Vasut HW_DIGCTL_CTRL_USB0_CLKGATE, 43afa87210SMarek Vasut }, 44afa87210SMarek Vasut #endif 45afa87210SMarek Vasut #ifdef CONFIG_EHCI_MXS_PORT1 46afa87210SMarek Vasut { 47afa87210SMarek Vasut MXS_USBCTRL1_BASE, 48afa87210SMarek Vasut (struct mxs_usbphy_regs *)MXS_USBPHY1_BASE, 49afa87210SMarek Vasut (struct mxs_register_32 *)(MXS_CLKCTRL_BASE + 50afa87210SMarek Vasut offsetof(struct mxs_clkctrl_regs, 51afa87210SMarek Vasut hw_clkctrl_pll1ctrl0_reg)), 52afa87210SMarek Vasut CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER, 53afa87210SMarek Vasut CLKCTRL_PLL1CTRL0_EN_USB_CLKS, 54afa87210SMarek Vasut HW_DIGCTL_CTRL_USB1_CLKGATE, 55afa87210SMarek Vasut }, 56afa87210SMarek Vasut #endif 57afa87210SMarek Vasut }; 58afa87210SMarek Vasut 59afa87210SMarek Vasut static int ehci_mxs_toggle_clock(const struct ehci_mxs_port *port, int enable) 60afa87210SMarek Vasut { 61afa87210SMarek Vasut struct mxs_register_32 *digctl_ctrl = 62afa87210SMarek Vasut (struct mxs_register_32 *)HW_DIGCTL_CTRL; 63afa87210SMarek Vasut int pll_offset, dig_offset; 64afa87210SMarek Vasut 65afa87210SMarek Vasut if (enable) { 66afa87210SMarek Vasut pll_offset = offsetof(struct mxs_register_32, reg_set); 67afa87210SMarek Vasut dig_offset = offsetof(struct mxs_register_32, reg_clr); 68afa87210SMarek Vasut writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset); 69afa87210SMarek Vasut writel(port->pll_en_bits, (u32)port->pll + pll_offset); 70afa87210SMarek Vasut } else { 71afa87210SMarek Vasut pll_offset = offsetof(struct mxs_register_32, reg_clr); 72afa87210SMarek Vasut dig_offset = offsetof(struct mxs_register_32, reg_set); 73afa87210SMarek Vasut writel(port->pll_dis_bits, (u32)port->pll + pll_offset); 74afa87210SMarek Vasut writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset); 75afa87210SMarek Vasut } 76afa87210SMarek Vasut 77afa87210SMarek Vasut return 0; 78afa87210SMarek Vasut } 79afa87210SMarek Vasut 80*127efc4fSTroy Kisky int ehci_hcd_init(int index, enum usb_init_type init, 81*127efc4fSTroy Kisky struct ehci_hccr **hccr, struct ehci_hcor **hcor) 82dbb8f279SMarek Vasut { 83dbb8f279SMarek Vasut 84dbb8f279SMarek Vasut int ret; 85dbb8f279SMarek Vasut uint32_t usb_base, cap_base; 86afa87210SMarek Vasut const struct ehci_mxs_port *port; 87dbb8f279SMarek Vasut 88afa87210SMarek Vasut if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) { 89afa87210SMarek Vasut printf("Invalid port index (index = %d)!\n", index); 90afa87210SMarek Vasut return -EINVAL; 91afa87210SMarek Vasut } 92afa87210SMarek Vasut 93afa87210SMarek Vasut port = &mxs_port[index]; 94afa87210SMarek Vasut 95afa87210SMarek Vasut /* Reset the PHY block */ 96afa87210SMarek Vasut writel(USBPHY_CTRL_SFTRST, &port->phy_regs->hw_usbphy_ctrl_set); 97afa87210SMarek Vasut udelay(10); 98afa87210SMarek Vasut writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE, 99afa87210SMarek Vasut &port->phy_regs->hw_usbphy_ctrl_clr); 100afa87210SMarek Vasut 101afa87210SMarek Vasut /* Enable USB clock */ 102afa87210SMarek Vasut ret = ehci_mxs_toggle_clock(port, 1); 103dbb8f279SMarek Vasut if (ret) 104dbb8f279SMarek Vasut return ret; 105dbb8f279SMarek Vasut 106dbb8f279SMarek Vasut /* Start USB PHY */ 107afa87210SMarek Vasut writel(0, &port->phy_regs->hw_usbphy_pwd); 108dbb8f279SMarek Vasut 109dbb8f279SMarek Vasut /* Enable UTMI+ Level 2 and Level 3 compatibility */ 110dbb8f279SMarek Vasut writel(USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2 | 1, 111afa87210SMarek Vasut &port->phy_regs->hw_usbphy_ctrl_set); 112dbb8f279SMarek Vasut 113afa87210SMarek Vasut usb_base = port->usb_regs + 0x100; 114676ae068SLucas Stach *hccr = (struct ehci_hccr *)usb_base; 115dbb8f279SMarek Vasut 116676ae068SLucas Stach cap_base = ehci_readl(&(*hccr)->cr_capbase); 117676ae068SLucas Stach *hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base)); 118dbb8f279SMarek Vasut 119dbb8f279SMarek Vasut return 0; 120dbb8f279SMarek Vasut } 121dbb8f279SMarek Vasut 122676ae068SLucas Stach int ehci_hcd_stop(int index) 123dbb8f279SMarek Vasut { 124dbb8f279SMarek Vasut int ret; 125676ae068SLucas Stach uint32_t usb_base, cap_base, tmp; 126676ae068SLucas Stach struct ehci_hccr *hccr; 127676ae068SLucas Stach struct ehci_hcor *hcor; 128afa87210SMarek Vasut const struct ehci_mxs_port *port; 129dbb8f279SMarek Vasut 130afa87210SMarek Vasut if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) { 131afa87210SMarek Vasut printf("Invalid port index (index = %d)!\n", index); 132afa87210SMarek Vasut return -EINVAL; 133afa87210SMarek Vasut } 134afa87210SMarek Vasut 135afa87210SMarek Vasut port = &mxs_port[index]; 136dbb8f279SMarek Vasut 137dbb8f279SMarek Vasut /* Stop the USB port */ 138afa87210SMarek Vasut usb_base = port->usb_regs + 0x100; 139676ae068SLucas Stach hccr = (struct ehci_hccr *)usb_base; 140676ae068SLucas Stach cap_base = ehci_readl(&hccr->cr_capbase); 141676ae068SLucas Stach hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base)); 142676ae068SLucas Stach 143dbb8f279SMarek Vasut tmp = ehci_readl(&hcor->or_usbcmd); 144dbb8f279SMarek Vasut tmp &= ~CMD_RUN; 145dbb8f279SMarek Vasut ehci_writel(tmp, &hcor->or_usbcmd); 146dbb8f279SMarek Vasut 147dbb8f279SMarek Vasut /* Disable the PHY */ 148dbb8f279SMarek Vasut tmp = USBPHY_PWD_RXPWDRX | USBPHY_PWD_RXPWDDIFF | 149dbb8f279SMarek Vasut USBPHY_PWD_RXPWD1PT1 | USBPHY_PWD_RXPWDENV | 150dbb8f279SMarek Vasut USBPHY_PWD_TXPWDV2I | USBPHY_PWD_TXPWDIBIAS | 151dbb8f279SMarek Vasut USBPHY_PWD_TXPWDFS; 152afa87210SMarek Vasut writel(tmp, &port->phy_regs->hw_usbphy_pwd); 153dbb8f279SMarek Vasut 154dbb8f279SMarek Vasut /* Disable USB clock */ 155afa87210SMarek Vasut ret = ehci_mxs_toggle_clock(port, 0); 156dbb8f279SMarek Vasut 157afa87210SMarek Vasut return ret; 158dbb8f279SMarek Vasut } 159