1 /* 2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 8 #include <common.h> 9 #include <usb.h> 10 #include <asm/io.h> 11 #include <asm/arch/imx-regs.h> 12 #include <usb/ehci-ci.h> 13 #include <errno.h> 14 15 #include "ehci.h" 16 17 #define USBCTRL_OTGBASE_OFFSET 0x600 18 19 #define MX25_OTG_SIC_SHIFT 29 20 #define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT) 21 #define MX25_OTG_PM_BIT (1 << 24) 22 #define MX25_OTG_PP_BIT (1 << 11) 23 #define MX25_OTG_OCPOL_BIT (1 << 3) 24 25 #define MX25_H1_SIC_SHIFT 21 26 #define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT) 27 #define MX25_H1_PP_BIT (1 << 18) 28 #define MX25_H1_PM_BIT (1 << 16) 29 #define MX25_H1_IPPUE_UP_BIT (1 << 7) 30 #define MX25_H1_IPPUE_DOWN_BIT (1 << 6) 31 #define MX25_H1_TLL_BIT (1 << 5) 32 #define MX25_H1_USBTE_BIT (1 << 4) 33 #define MX25_H1_OCPOL_BIT (1 << 2) 34 35 #define MX31_OTG_SIC_SHIFT 29 36 #define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) 37 #define MX31_OTG_PM_BIT (1 << 24) 38 39 #define MX31_H2_SIC_SHIFT 21 40 #define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT) 41 #define MX31_H2_PM_BIT (1 << 16) 42 #define MX31_H2_DT_BIT (1 << 5) 43 44 #define MX31_H1_SIC_SHIFT 13 45 #define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) 46 #define MX31_H1_PM_BIT (1 << 8) 47 #define MX31_H1_DT_BIT (1 << 4) 48 49 #define MX35_OTG_SIC_SHIFT 29 50 #define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT) 51 #define MX35_OTG_PM_BIT (1 << 24) 52 #define MX35_OTG_PP_BIT (1 << 11) 53 #define MX35_OTG_OCPOL_BIT (1 << 3) 54 55 #define MX35_H1_SIC_SHIFT 21 56 #define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) 57 #define MX35_H1_PP_BIT (1 << 18) 58 #define MX35_H1_PM_BIT (1 << 16) 59 #define MX35_H1_IPPUE_UP_BIT (1 << 7) 60 #define MX35_H1_IPPUE_DOWN_BIT (1 << 6) 61 #define MX35_H1_TLL_BIT (1 << 5) 62 #define MX35_H1_USBTE_BIT (1 << 4) 63 #define MX35_H1_OCPOL_BIT (1 << 2) 64 65 static int mxc_set_usbcontrol(int port, unsigned int flags) 66 { 67 unsigned int v; 68 69 v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); 70 #if defined(CONFIG_MX25) 71 switch (port) { 72 case 0: /* OTG port */ 73 v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT | 74 MX25_OTG_OCPOL_BIT); 75 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT; 76 77 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 78 v |= MX25_OTG_PM_BIT; 79 80 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 81 v |= MX25_OTG_PP_BIT; 82 83 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) 84 v |= MX25_OTG_OCPOL_BIT; 85 86 break; 87 case 1: /* H1 port */ 88 v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT | 89 MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | 90 MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT | 91 MX25_H1_IPPUE_UP_BIT); 92 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT; 93 94 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 95 v |= MX25_H1_PM_BIT; 96 97 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 98 v |= MX25_H1_PP_BIT; 99 100 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) 101 v |= MX25_H1_OCPOL_BIT; 102 103 if (!(flags & MXC_EHCI_TTL_ENABLED)) 104 v |= MX25_H1_TLL_BIT; 105 106 if (flags & MXC_EHCI_INTERNAL_PHY) 107 v |= MX25_H1_USBTE_BIT; 108 109 if (flags & MXC_EHCI_IPPUE_DOWN) 110 v |= MX25_H1_IPPUE_DOWN_BIT; 111 112 if (flags & MXC_EHCI_IPPUE_UP) 113 v |= MX25_H1_IPPUE_UP_BIT; 114 115 break; 116 default: 117 return -EINVAL; 118 } 119 #elif defined(CONFIG_MX31) 120 switch (port) { 121 case 0: /* OTG port */ 122 v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); 123 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT; 124 125 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 126 v |= MX31_OTG_PM_BIT; 127 128 break; 129 case 1: /* H1 port */ 130 v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT); 131 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT; 132 133 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 134 v |= MX31_H1_PM_BIT; 135 136 if (!(flags & MXC_EHCI_TTL_ENABLED)) 137 v |= MX31_H1_DT_BIT; 138 139 break; 140 case 2: /* H2 port */ 141 v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT); 142 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT; 143 144 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 145 v |= MX31_H2_PM_BIT; 146 147 if (!(flags & MXC_EHCI_TTL_ENABLED)) 148 v |= MX31_H2_DT_BIT; 149 150 break; 151 default: 152 return -EINVAL; 153 } 154 #elif defined(CONFIG_MX35) 155 switch (port) { 156 case 0: /* OTG port */ 157 v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT | 158 MX35_OTG_OCPOL_BIT); 159 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT; 160 161 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 162 v |= MX35_OTG_PM_BIT; 163 164 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 165 v |= MX35_OTG_PP_BIT; 166 167 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) 168 v |= MX35_OTG_OCPOL_BIT; 169 170 break; 171 case 1: /* H1 port */ 172 v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT | 173 MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | 174 MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | 175 MX35_H1_IPPUE_UP_BIT); 176 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT; 177 178 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 179 v |= MX35_H1_PM_BIT; 180 181 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 182 v |= MX35_H1_PP_BIT; 183 184 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) 185 v |= MX35_H1_OCPOL_BIT; 186 187 if (!(flags & MXC_EHCI_TTL_ENABLED)) 188 v |= MX35_H1_TLL_BIT; 189 190 if (flags & MXC_EHCI_INTERNAL_PHY) 191 v |= MX35_H1_USBTE_BIT; 192 193 if (flags & MXC_EHCI_IPPUE_DOWN) 194 v |= MX35_H1_IPPUE_DOWN_BIT; 195 196 if (flags & MXC_EHCI_IPPUE_UP) 197 v |= MX35_H1_IPPUE_UP_BIT; 198 199 break; 200 default: 201 return -EINVAL; 202 } 203 #else 204 #error MXC EHCI USB driver not supported on this platform 205 #endif 206 writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); 207 208 return 0; 209 } 210 211 int ehci_hcd_init(int index, enum usb_init_type init, 212 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 213 { 214 struct usb_ehci *ehci; 215 #ifdef CONFIG_MX31 216 struct clock_control_regs *sc_regs = 217 (struct clock_control_regs *)CCM_BASE; 218 219 __raw_readl(&sc_regs->ccmr); 220 __raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ; 221 #endif 222 223 udelay(80); 224 225 ehci = (struct usb_ehci *)(IMX_USB_BASE + 226 IMX_USB_PORT_OFFSET * CONFIG_MXC_USB_PORT); 227 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 228 *hcor = (struct ehci_hcor *)((uint32_t) *hccr + 229 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 230 setbits_le32(&ehci->usbmode, CM_HOST); 231 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); 232 mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); 233 #ifdef CONFIG_MX35 234 /* Workaround for ENGcm11601 */ 235 __raw_writel(0, &ehci->sbuscfg); 236 #endif 237 238 udelay(10000); 239 240 return 0; 241 } 242 243 /* 244 * Destroy the appropriate control structures corresponding 245 * the the EHCI host controller. 246 */ 247 int ehci_hcd_stop(int index) 248 { 249 return 0; 250 } 251