1 /* 2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19 20 #include <common.h> 21 #include <usb.h> 22 #include <asm/io.h> 23 #include <asm/arch/mx31-regs.h> 24 #include <usb/ehci-fsl.h> 25 #include <errno.h> 26 27 #include "ehci.h" 28 #include "ehci-core.h" 29 30 #define USBCTRL_OTGBASE_OFFSET 0x600 31 32 #define MX31_OTG_SIC_SHIFT 29 33 #define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) 34 #define MX31_OTG_PM_BIT (1 << 24) 35 36 #define MX31_H2_SIC_SHIFT 21 37 #define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT) 38 #define MX31_H2_PM_BIT (1 << 16) 39 #define MX31_H2_DT_BIT (1 << 5) 40 41 #define MX31_H1_SIC_SHIFT 13 42 #define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) 43 #define MX31_H1_PM_BIT (1 << 8) 44 #define MX31_H1_DT_BIT (1 << 4) 45 46 static int mxc_set_usbcontrol(int port, unsigned int flags) 47 { 48 unsigned int v; 49 #ifdef CONFIG_MX31 50 v = readl(MX31_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET); 51 52 switch (port) { 53 case 0: /* OTG port */ 54 v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); 55 v |= (flags & MXC_EHCI_INTERFACE_MASK) 56 << MX31_OTG_SIC_SHIFT; 57 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 58 v |= MX31_OTG_PM_BIT; 59 60 break; 61 case 1: /* H1 port */ 62 v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | 63 MX31_H1_DT_BIT); 64 v |= (flags & MXC_EHCI_INTERFACE_MASK) 65 << MX31_H1_SIC_SHIFT; 66 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 67 v |= MX31_H1_PM_BIT; 68 69 if (!(flags & MXC_EHCI_TTL_ENABLED)) 70 v |= MX31_H1_DT_BIT; 71 72 break; 73 case 2: /* H2 port */ 74 v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | 75 MX31_H2_DT_BIT); 76 v |= (flags & MXC_EHCI_INTERFACE_MASK) 77 << MX31_H2_SIC_SHIFT; 78 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 79 v |= MX31_H2_PM_BIT; 80 81 if (!(flags & MXC_EHCI_TTL_ENABLED)) 82 v |= MX31_H2_DT_BIT; 83 84 break; 85 default: 86 return -EINVAL; 87 } 88 89 writel(v, MX31_OTG_BASE_ADDR + 90 USBCTRL_OTGBASE_OFFSET); 91 #endif 92 return 0; 93 } 94 95 int ehci_hcd_init(void) 96 { 97 u32 tmp; 98 struct usb_ehci *ehci; 99 struct clock_control_regs *sc_regs = 100 (struct clock_control_regs *)CCM_BASE; 101 102 tmp = __raw_readl(&sc_regs->ccmr); 103 __raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ; 104 105 udelay(80); 106 107 /* Take USB2 */ 108 ehci = (struct usb_ehci *)(MX31_OTG_BASE_ADDR + 109 (0x200 * CONFIG_MXC_USB_PORT)); 110 hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 111 hcor = (struct ehci_hcor *)((uint32_t) hccr + 112 HC_LENGTH(ehci_readl(&hccr->cr_capbase))); 113 setbits_le32(&ehci->usbmode, CM_HOST); 114 setbits_le32(&ehci->control, USB_EN); 115 116 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); 117 118 mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); 119 120 udelay(10000); 121 122 return 0; 123 } 124 125 /* 126 * Destroy the appropriate control structures corresponding 127 * the the EHCI host controller. 128 */ 129 int ehci_hcd_stop(void) 130 { 131 return 0; 132 } 133