1 /* 2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19 20 #include <common.h> 21 #include <usb.h> 22 #include <asm/io.h> 23 #include <asm/arch/imx-regs.h> 24 #include <usb/ehci-fsl.h> 25 #include <errno.h> 26 27 #include "ehci.h" 28 29 #define USBCTRL_OTGBASE_OFFSET 0x600 30 31 #ifdef CONFIG_MX25 32 #define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6) 33 #define MX25_USB_CTRL_HSTD_BIT (1<<5) 34 #define MX25_USB_CTRL_USBTE_BIT (1<<4) 35 #define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3) 36 #endif 37 38 #ifdef CONFIG_MX31 39 #define MX31_OTG_SIC_SHIFT 29 40 #define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) 41 #define MX31_OTG_PM_BIT (1 << 24) 42 43 #define MX31_H2_SIC_SHIFT 21 44 #define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT) 45 #define MX31_H2_PM_BIT (1 << 16) 46 #define MX31_H2_DT_BIT (1 << 5) 47 48 #define MX31_H1_SIC_SHIFT 13 49 #define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) 50 #define MX31_H1_PM_BIT (1 << 8) 51 #define MX31_H1_DT_BIT (1 << 4) 52 #endif 53 54 static int mxc_set_usbcontrol(int port, unsigned int flags) 55 { 56 unsigned int v; 57 58 #ifdef CONFIG_MX25 59 v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT | 60 MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT; 61 #endif 62 63 #ifdef CONFIG_MX31 64 v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); 65 66 switch (port) { 67 case 0: /* OTG port */ 68 v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); 69 v |= (flags & MXC_EHCI_INTERFACE_MASK) 70 << MX31_OTG_SIC_SHIFT; 71 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 72 v |= MX31_OTG_PM_BIT; 73 74 break; 75 case 1: /* H1 port */ 76 v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | 77 MX31_H1_DT_BIT); 78 v |= (flags & MXC_EHCI_INTERFACE_MASK) 79 << MX31_H1_SIC_SHIFT; 80 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 81 v |= MX31_H1_PM_BIT; 82 83 if (!(flags & MXC_EHCI_TTL_ENABLED)) 84 v |= MX31_H1_DT_BIT; 85 86 break; 87 case 2: /* H2 port */ 88 v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | 89 MX31_H2_DT_BIT); 90 v |= (flags & MXC_EHCI_INTERFACE_MASK) 91 << MX31_H2_SIC_SHIFT; 92 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 93 v |= MX31_H2_PM_BIT; 94 95 if (!(flags & MXC_EHCI_TTL_ENABLED)) 96 v |= MX31_H2_DT_BIT; 97 98 break; 99 default: 100 return -EINVAL; 101 } 102 #endif 103 104 writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); 105 return 0; 106 } 107 108 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) 109 { 110 struct usb_ehci *ehci; 111 #ifdef CONFIG_MX31 112 struct clock_control_regs *sc_regs = 113 (struct clock_control_regs *)CCM_BASE; 114 115 __raw_readl(&sc_regs->ccmr); 116 __raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ; 117 #endif 118 119 udelay(80); 120 121 ehci = (struct usb_ehci *)(IMX_USB_BASE + 122 (0x200 * CONFIG_MXC_USB_PORT)); 123 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 124 *hcor = (struct ehci_hcor *)((uint32_t) *hccr + 125 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 126 setbits_le32(&ehci->usbmode, CM_HOST); 127 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); 128 mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); 129 130 udelay(10000); 131 132 return 0; 133 } 134 135 /* 136 * Destroy the appropriate control structures corresponding 137 * the the EHCI host controller. 138 */ 139 int ehci_hcd_stop(int index) 140 { 141 return 0; 142 } 143