1 /* 2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> 3 * Copyright (C) 2010 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <usb.h> 10 #include <errno.h> 11 #include <linux/compiler.h> 12 #include <usb/ehci-fsl.h> 13 #include <asm/io.h> 14 #include <asm/arch/imx-regs.h> 15 #include <asm/arch/clock.h> 16 #include <asm/imx-common/iomux-v3.h> 17 18 #include "ehci.h" 19 20 #define USB_OTGREGS_OFFSET 0x000 21 #define USB_H1REGS_OFFSET 0x200 22 #define USB_H2REGS_OFFSET 0x400 23 #define USB_H3REGS_OFFSET 0x600 24 #define USB_OTHERREGS_OFFSET 0x800 25 26 #define USB_H1_CTRL_OFFSET 0x04 27 28 #define USBPHY_CTRL 0x00000030 29 #define USBPHY_CTRL_SET 0x00000034 30 #define USBPHY_CTRL_CLR 0x00000038 31 #define USBPHY_CTRL_TOG 0x0000003c 32 33 #define USBPHY_PWD 0x00000000 34 #define USBPHY_CTRL_SFTRST 0x80000000 35 #define USBPHY_CTRL_CLKGATE 0x40000000 36 #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000 37 #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000 38 #define USBPHY_CTRL_OTG_ID 0x08000000 39 40 #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000 41 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000 42 43 #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000 44 #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000 45 #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000 46 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040 47 48 #define USBNC_OFFSET 0x200 49 #define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */ 50 #define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */ 51 #define UCTRL_PM (1 << 9) /* OTG Power Mask */ 52 #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */ 53 #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */ 54 55 /* USBCMD */ 56 #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */ 57 #define UCMD_RESET (1 << 1) /* controller reset */ 58 59 #if defined(CONFIG_MX6) 60 static const unsigned phy_bases[] = { 61 USB_PHY0_BASE_ADDR, 62 USB_PHY1_BASE_ADDR, 63 }; 64 65 static void usb_internal_phy_clock_gate(int index, int on) 66 { 67 void __iomem *phy_reg; 68 69 if (index >= ARRAY_SIZE(phy_bases)) 70 return; 71 72 phy_reg = (void __iomem *)phy_bases[index]; 73 phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET; 74 writel(USBPHY_CTRL_CLKGATE, phy_reg); 75 } 76 77 static void usb_power_config(int index) 78 { 79 struct anatop_regs __iomem *anatop = 80 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; 81 void __iomem *chrg_detect; 82 void __iomem *pll_480_ctrl_clr; 83 void __iomem *pll_480_ctrl_set; 84 85 switch (index) { 86 case 0: 87 chrg_detect = &anatop->usb1_chrg_detect; 88 pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr; 89 pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set; 90 break; 91 case 1: 92 chrg_detect = &anatop->usb2_chrg_detect; 93 pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr; 94 pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set; 95 break; 96 default: 97 return; 98 } 99 /* 100 * Some phy and power's special controls 101 * 1. The external charger detector needs to be disabled 102 * or the signal at DP will be poor 103 * 2. The PLL's power and output to usb 104 * is totally controlled by IC, so the Software only needs 105 * to enable them at initializtion. 106 */ 107 writel(ANADIG_USB2_CHRG_DETECT_EN_B | 108 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B, 109 chrg_detect); 110 111 writel(ANADIG_USB2_PLL_480_CTRL_BYPASS, 112 pll_480_ctrl_clr); 113 114 writel(ANADIG_USB2_PLL_480_CTRL_ENABLE | 115 ANADIG_USB2_PLL_480_CTRL_POWER | 116 ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS, 117 pll_480_ctrl_set); 118 } 119 120 static int wait_for_bit(u32 *reg, const u32 mask, bool set) 121 { 122 u32 val; 123 const unsigned int timeout = 10000; 124 unsigned long start = get_timer(0); 125 126 while(1) { 127 val = readl(reg); 128 if (!set) 129 val = ~val; 130 131 if ((val & mask) == mask) 132 return 0; 133 134 if (get_timer(start) > timeout) 135 break; 136 137 udelay(1); 138 } 139 140 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", 141 __func__, reg, mask, set); 142 143 return -ETIMEDOUT; 144 } 145 146 /* Return 0 : host node, <>0 : device mode */ 147 static int usb_phy_enable(int index, struct usb_ehci *ehci) 148 { 149 void __iomem *phy_reg; 150 void __iomem *phy_ctrl; 151 void __iomem *usb_cmd; 152 int ret; 153 154 if (index >= ARRAY_SIZE(phy_bases)) 155 return 0; 156 157 phy_reg = (void __iomem *)phy_bases[index]; 158 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); 159 usb_cmd = (void __iomem *)&ehci->usbcmd; 160 161 /* Stop then Reset */ 162 clrbits_le32(usb_cmd, UCMD_RUN_STOP); 163 ret = wait_for_bit(usb_cmd, UCMD_RUN_STOP, 0); 164 if (ret) 165 return ret; 166 167 setbits_le32(usb_cmd, UCMD_RESET); 168 ret = wait_for_bit(usb_cmd, UCMD_RESET, 0); 169 if (ret) 170 return ret; 171 172 /* Reset USBPHY module */ 173 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); 174 udelay(10); 175 176 /* Remove CLKGATE and SFTRST */ 177 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); 178 udelay(10); 179 180 /* Power up the PHY */ 181 writel(0, phy_reg + USBPHY_PWD); 182 /* enable FS/LS device */ 183 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | 184 USBPHY_CTRL_ENUTMILEVEL3); 185 186 return 0; 187 } 188 189 int usb_phy_mode(int port) 190 { 191 void __iomem *phy_reg; 192 void __iomem *phy_ctrl; 193 u32 val; 194 195 phy_reg = (void __iomem *)phy_bases[port]; 196 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); 197 198 val = readl(phy_ctrl); 199 200 if (val & USBPHY_CTRL_OTG_ID) 201 return USB_INIT_DEVICE; 202 else 203 return USB_INIT_HOST; 204 } 205 206 /* Base address for this IP block is 0x02184800 */ 207 struct usbnc_regs { 208 u32 ctrl[4]; /* otg/host1-3 */ 209 u32 uh2_hsic_ctrl; 210 u32 uh3_hsic_ctrl; 211 u32 otg_phy_ctrl_0; 212 u32 uh1_phy_ctrl_0; 213 }; 214 #elif defined(CONFIG_MX7) 215 struct usbnc_regs { 216 u32 ctrl1; 217 u32 ctrl2; 218 u32 reserve1[10]; 219 u32 phy_cfg1; 220 u32 phy_cfg2; 221 u32 phy_status; 222 u32 reserve2[4]; 223 u32 adp_cfg1; 224 u32 adp_cfg2; 225 u32 adp_status; 226 }; 227 228 static void usb_power_config(int index) 229 { 230 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + 231 (0x10000 * index) + USBNC_OFFSET); 232 void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2); 233 234 /* Enable usb_otg_id detection */ 235 setbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB); 236 } 237 238 int usb_phy_mode(int port) 239 { 240 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + 241 (0x10000 * port) + USBNC_OFFSET); 242 void __iomem *status = (void __iomem *)(&usbnc->phy_status); 243 u32 val; 244 245 val = readl(status); 246 247 if (val & USBNC_PHYSTATUS_ID_DIG) 248 return USB_INIT_DEVICE; 249 else 250 return USB_INIT_HOST; 251 } 252 #endif 253 254 static void usb_oc_config(int index) 255 { 256 #if defined(CONFIG_MX6) 257 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + 258 USB_OTHERREGS_OFFSET); 259 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]); 260 #elif defined(CONFIG_MX7) 261 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + 262 (0x10000 * index) + USBNC_OFFSET); 263 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1); 264 #endif 265 266 #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2 267 /* mx6qarm2 seems to required a different setting*/ 268 clrbits_le32(ctrl, UCTRL_OVER_CUR_POL); 269 #else 270 setbits_le32(ctrl, UCTRL_OVER_CUR_POL); 271 #endif 272 273 #if defined(CONFIG_MX6) 274 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS); 275 #elif defined(CONFIG_MX7) 276 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS | UCTRL_PM); 277 #endif 278 } 279 280 /** 281 * board_ehci_hcd_init - override usb phy mode 282 * @port: usb host/otg port 283 * 284 * Target board specific, override usb_phy_mode. 285 * When usb-otg is used as usb host port, iomux pad usb_otg_id can be 286 * left disconnected in this case usb_phy_mode will not be able to identify 287 * the phy mode that usb port is used. 288 * Machine file overrides board_usb_phy_mode. 289 * 290 * Return: USB_INIT_DEVICE or USB_INIT_HOST 291 */ 292 int __weak board_usb_phy_mode(int port) 293 { 294 return usb_phy_mode(port); 295 } 296 297 /** 298 * board_ehci_hcd_init - set usb vbus voltage 299 * @port: usb otg port 300 * 301 * Target board specific, setup iomux pad to setup supply vbus voltage 302 * for usb otg port. Machine board file overrides board_ehci_hcd_init 303 * 304 * Return: 0 Success 305 */ 306 int __weak board_ehci_hcd_init(int port) 307 { 308 return 0; 309 } 310 311 /** 312 * board_ehci_power - enables/disables usb vbus voltage 313 * @port: usb otg port 314 * @on: on/off vbus voltage 315 * 316 * Enables/disables supply vbus voltage for usb otg port. 317 * Machine board file overrides board_ehci_power 318 * 319 * Return: 0 Success 320 */ 321 int __weak board_ehci_power(int port, int on) 322 { 323 return 0; 324 } 325 326 int ehci_hcd_init(int index, enum usb_init_type init, 327 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 328 { 329 enum usb_init_type type; 330 #if defined(CONFIG_MX6) 331 u32 controller_spacing = 0x200; 332 #elif defined(CONFIG_MX7) 333 u32 controller_spacing = 0x10000; 334 #endif 335 struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR + 336 (controller_spacing * index)); 337 338 if (index > 3) 339 return -EINVAL; 340 enable_usboh3_clk(1); 341 mdelay(1); 342 343 /* Do board specific initialization */ 344 board_ehci_hcd_init(index); 345 346 usb_power_config(index); 347 usb_oc_config(index); 348 349 #if defined(CONFIG_MX6) 350 usb_internal_phy_clock_gate(index, 1); 351 usb_phy_enable(index, ehci); 352 #endif 353 type = board_usb_phy_mode(index); 354 355 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 356 *hcor = (struct ehci_hcor *)((uint32_t)*hccr + 357 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 358 359 if ((type == init) || (type == USB_INIT_DEVICE)) 360 board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1); 361 if (type != init) 362 return -ENODEV; 363 if (type == USB_INIT_DEVICE) 364 return 0; 365 366 setbits_le32(&ehci->usbmode, CM_HOST); 367 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); 368 setbits_le32(&ehci->portsc, USB_EN); 369 370 mdelay(10); 371 372 return 0; 373 } 374 375 int ehci_hcd_stop(int index) 376 { 377 return 0; 378 } 379