1 /* 2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> 3 * Copyright (C) 2010 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <usb.h> 10 #include <errno.h> 11 #include <wait_bit.h> 12 #include <linux/compiler.h> 13 #include <usb/ehci-ci.h> 14 #include <asm/io.h> 15 #include <asm/arch/imx-regs.h> 16 #include <asm/arch/clock.h> 17 #include <asm/mach-imx/iomux-v3.h> 18 #include <asm/mach-imx/sys_proto.h> 19 #include <dm.h> 20 #include <asm/mach-types.h> 21 #include <power/regulator.h> 22 23 #include "ehci.h" 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 #define USB_OTGREGS_OFFSET 0x000 28 #define USB_H1REGS_OFFSET 0x200 29 #define USB_H2REGS_OFFSET 0x400 30 #define USB_H3REGS_OFFSET 0x600 31 #define USB_OTHERREGS_OFFSET 0x800 32 33 #define USB_H1_CTRL_OFFSET 0x04 34 35 #define USBPHY_CTRL 0x00000030 36 #define USBPHY_CTRL_SET 0x00000034 37 #define USBPHY_CTRL_CLR 0x00000038 38 #define USBPHY_CTRL_TOG 0x0000003c 39 40 #define USBPHY_PWD 0x00000000 41 #define USBPHY_CTRL_SFTRST 0x80000000 42 #define USBPHY_CTRL_CLKGATE 0x40000000 43 #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000 44 #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000 45 #define USBPHY_CTRL_OTG_ID 0x08000000 46 47 #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000 48 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000 49 50 #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000 51 #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000 52 #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000 53 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040 54 55 #define USBNC_OFFSET 0x200 56 #define USBNC_PHY_STATUS_OFFSET 0x23C 57 #define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */ 58 #define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */ 59 #define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */ 60 #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */ 61 #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */ 62 63 /* USBCMD */ 64 #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */ 65 #define UCMD_RESET (1 << 1) /* controller reset */ 66 67 #if defined(CONFIG_MX6) 68 static const unsigned phy_bases[] = { 69 USB_PHY0_BASE_ADDR, 70 USB_PHY1_BASE_ADDR, 71 }; 72 73 static void usb_internal_phy_clock_gate(int index, int on) 74 { 75 void __iomem *phy_reg; 76 77 if (index >= ARRAY_SIZE(phy_bases)) 78 return; 79 80 phy_reg = (void __iomem *)phy_bases[index]; 81 phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET; 82 writel(USBPHY_CTRL_CLKGATE, phy_reg); 83 } 84 85 static void usb_power_config(int index) 86 { 87 struct anatop_regs __iomem *anatop = 88 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; 89 void __iomem *chrg_detect; 90 void __iomem *pll_480_ctrl_clr; 91 void __iomem *pll_480_ctrl_set; 92 93 switch (index) { 94 case 0: 95 chrg_detect = &anatop->usb1_chrg_detect; 96 pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr; 97 pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set; 98 break; 99 case 1: 100 chrg_detect = &anatop->usb2_chrg_detect; 101 pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr; 102 pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set; 103 break; 104 default: 105 return; 106 } 107 /* 108 * Some phy and power's special controls 109 * 1. The external charger detector needs to be disabled 110 * or the signal at DP will be poor 111 * 2. The PLL's power and output to usb 112 * is totally controlled by IC, so the Software only needs 113 * to enable them at initializtion. 114 */ 115 writel(ANADIG_USB2_CHRG_DETECT_EN_B | 116 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B, 117 chrg_detect); 118 119 writel(ANADIG_USB2_PLL_480_CTRL_BYPASS, 120 pll_480_ctrl_clr); 121 122 writel(ANADIG_USB2_PLL_480_CTRL_ENABLE | 123 ANADIG_USB2_PLL_480_CTRL_POWER | 124 ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS, 125 pll_480_ctrl_set); 126 } 127 128 /* Return 0 : host node, <>0 : device mode */ 129 static int usb_phy_enable(int index, struct usb_ehci *ehci) 130 { 131 void __iomem *phy_reg; 132 void __iomem *phy_ctrl; 133 void __iomem *usb_cmd; 134 int ret; 135 136 if (index >= ARRAY_SIZE(phy_bases)) 137 return 0; 138 139 phy_reg = (void __iomem *)phy_bases[index]; 140 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); 141 usb_cmd = (void __iomem *)&ehci->usbcmd; 142 143 /* Stop then Reset */ 144 clrbits_le32(usb_cmd, UCMD_RUN_STOP); 145 ret = wait_for_bit(__func__, usb_cmd, UCMD_RUN_STOP, false, 10000, 146 false); 147 if (ret) 148 return ret; 149 150 setbits_le32(usb_cmd, UCMD_RESET); 151 ret = wait_for_bit(__func__, usb_cmd, UCMD_RESET, false, 10000, false); 152 if (ret) 153 return ret; 154 155 /* Reset USBPHY module */ 156 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); 157 udelay(10); 158 159 /* Remove CLKGATE and SFTRST */ 160 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); 161 udelay(10); 162 163 /* Power up the PHY */ 164 writel(0, phy_reg + USBPHY_PWD); 165 /* enable FS/LS device */ 166 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | 167 USBPHY_CTRL_ENUTMILEVEL3); 168 169 return 0; 170 } 171 172 int usb_phy_mode(int port) 173 { 174 void __iomem *phy_reg; 175 void __iomem *phy_ctrl; 176 u32 val; 177 178 phy_reg = (void __iomem *)phy_bases[port]; 179 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); 180 181 val = readl(phy_ctrl); 182 183 if (val & USBPHY_CTRL_OTG_ID) 184 return USB_INIT_DEVICE; 185 else 186 return USB_INIT_HOST; 187 } 188 189 /* Base address for this IP block is 0x02184800 */ 190 struct usbnc_regs { 191 u32 ctrl[4]; /* otg/host1-3 */ 192 u32 uh2_hsic_ctrl; 193 u32 uh3_hsic_ctrl; 194 u32 otg_phy_ctrl_0; 195 u32 uh1_phy_ctrl_0; 196 }; 197 #elif defined(CONFIG_MX7) 198 struct usbnc_regs { 199 u32 ctrl1; 200 u32 ctrl2; 201 u32 reserve1[10]; 202 u32 phy_cfg1; 203 u32 phy_cfg2; 204 u32 reserve2; 205 u32 phy_status; 206 u32 reserve3[4]; 207 u32 adp_cfg1; 208 u32 adp_cfg2; 209 u32 adp_status; 210 }; 211 212 static void usb_power_config(int index) 213 { 214 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + 215 (0x10000 * index) + USBNC_OFFSET); 216 void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2); 217 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1); 218 219 /* 220 * Clear the ACAENB to enable usb_otg_id detection, 221 * otherwise it is the ACA detection enabled. 222 */ 223 clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB); 224 225 /* Set power polarity to high active */ 226 #ifdef CONFIG_MXC_USB_OTG_HACTIVE 227 setbits_le32(ctrl, UCTRL_PWR_POL); 228 #else 229 clrbits_le32(ctrl, UCTRL_PWR_POL); 230 #endif 231 } 232 233 int usb_phy_mode(int port) 234 { 235 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + 236 (0x10000 * port) + USBNC_OFFSET); 237 void __iomem *status = (void __iomem *)(&usbnc->phy_status); 238 u32 val; 239 240 val = readl(status); 241 242 if (val & USBNC_PHYSTATUS_ID_DIG) 243 return USB_INIT_DEVICE; 244 else 245 return USB_INIT_HOST; 246 } 247 #endif 248 249 static void usb_oc_config(int index) 250 { 251 #if defined(CONFIG_MX6) 252 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + 253 USB_OTHERREGS_OFFSET); 254 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]); 255 #elif defined(CONFIG_MX7) 256 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + 257 (0x10000 * index) + USBNC_OFFSET); 258 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1); 259 #endif 260 261 #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2 262 /* mx6qarm2 seems to required a different setting*/ 263 clrbits_le32(ctrl, UCTRL_OVER_CUR_POL); 264 #else 265 setbits_le32(ctrl, UCTRL_OVER_CUR_POL); 266 #endif 267 268 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS); 269 } 270 271 /** 272 * board_usb_phy_mode - override usb phy mode 273 * @port: usb host/otg port 274 * 275 * Target board specific, override usb_phy_mode. 276 * When usb-otg is used as usb host port, iomux pad usb_otg_id can be 277 * left disconnected in this case usb_phy_mode will not be able to identify 278 * the phy mode that usb port is used. 279 * Machine file overrides board_usb_phy_mode. 280 * 281 * Return: USB_INIT_DEVICE or USB_INIT_HOST 282 */ 283 int __weak board_usb_phy_mode(int port) 284 { 285 return usb_phy_mode(port); 286 } 287 288 /** 289 * board_ehci_hcd_init - set usb vbus voltage 290 * @port: usb otg port 291 * 292 * Target board specific, setup iomux pad to setup supply vbus voltage 293 * for usb otg port. Machine board file overrides board_ehci_hcd_init 294 * 295 * Return: 0 Success 296 */ 297 int __weak board_ehci_hcd_init(int port) 298 { 299 return 0; 300 } 301 302 /** 303 * board_ehci_power - enables/disables usb vbus voltage 304 * @port: usb otg port 305 * @on: on/off vbus voltage 306 * 307 * Enables/disables supply vbus voltage for usb otg port. 308 * Machine board file overrides board_ehci_power 309 * 310 * Return: 0 Success 311 */ 312 int __weak board_ehci_power(int port, int on) 313 { 314 return 0; 315 } 316 317 int ehci_mx6_common_init(struct usb_ehci *ehci, int index) 318 { 319 int ret; 320 321 enable_usboh3_clk(1); 322 mdelay(1); 323 324 /* Do board specific initialization */ 325 ret = board_ehci_hcd_init(index); 326 if (ret) 327 return ret; 328 329 usb_power_config(index); 330 usb_oc_config(index); 331 332 #if defined(CONFIG_MX6) 333 usb_internal_phy_clock_gate(index, 1); 334 usb_phy_enable(index, ehci); 335 #endif 336 337 return 0; 338 } 339 340 #ifndef CONFIG_DM_USB 341 int ehci_hcd_init(int index, enum usb_init_type init, 342 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 343 { 344 enum usb_init_type type; 345 #if defined(CONFIG_MX6) 346 u32 controller_spacing = 0x200; 347 #elif defined(CONFIG_MX7) 348 u32 controller_spacing = 0x10000; 349 #endif 350 struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR + 351 (controller_spacing * index)); 352 int ret; 353 354 if (index > 3) 355 return -EINVAL; 356 357 ret = ehci_mx6_common_init(ehci, index); 358 if (ret) 359 return ret; 360 361 type = board_usb_phy_mode(index); 362 363 if (hccr && hcor) { 364 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 365 *hcor = (struct ehci_hcor *)((uint32_t)*hccr + 366 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 367 } 368 369 if ((type == init) || (type == USB_INIT_DEVICE)) 370 board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1); 371 if (type != init) 372 return -ENODEV; 373 if (type == USB_INIT_DEVICE) 374 return 0; 375 376 setbits_le32(&ehci->usbmode, CM_HOST); 377 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); 378 setbits_le32(&ehci->portsc, USB_EN); 379 380 mdelay(10); 381 382 return 0; 383 } 384 385 int ehci_hcd_stop(int index) 386 { 387 return 0; 388 } 389 #else 390 struct ehci_mx6_priv_data { 391 struct ehci_ctrl ctrl; 392 struct usb_ehci *ehci; 393 struct udevice *vbus_supply; 394 enum usb_init_type init_type; 395 int portnr; 396 }; 397 398 static int mx6_init_after_reset(struct ehci_ctrl *dev) 399 { 400 struct ehci_mx6_priv_data *priv = dev->priv; 401 enum usb_init_type type = priv->init_type; 402 struct usb_ehci *ehci = priv->ehci; 403 int ret; 404 405 ret = ehci_mx6_common_init(priv->ehci, priv->portnr); 406 if (ret) 407 return ret; 408 409 if (priv->vbus_supply) { 410 ret = regulator_set_enable(priv->vbus_supply, 411 (type == USB_INIT_DEVICE) ? 412 false : true); 413 if (ret) { 414 puts("Error enabling VBUS supply\n"); 415 return ret; 416 } 417 } 418 419 if (type == USB_INIT_DEVICE) 420 return 0; 421 422 setbits_le32(&ehci->usbmode, CM_HOST); 423 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); 424 setbits_le32(&ehci->portsc, USB_EN); 425 426 mdelay(10); 427 428 return 0; 429 } 430 431 static const struct ehci_ops mx6_ehci_ops = { 432 .init_after_reset = mx6_init_after_reset 433 }; 434 435 static int ehci_usb_phy_mode(struct udevice *dev) 436 { 437 struct usb_platdata *plat = dev_get_platdata(dev); 438 void *__iomem addr = (void *__iomem)devfdt_get_addr(dev); 439 void *__iomem phy_ctrl, *__iomem phy_status; 440 const void *blob = gd->fdt_blob; 441 int offset = dev_of_offset(dev), phy_off; 442 u32 val; 443 444 /* 445 * About fsl,usbphy, Refer to 446 * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt. 447 */ 448 if (is_mx6()) { 449 phy_off = fdtdec_lookup_phandle(blob, 450 offset, 451 "fsl,usbphy"); 452 if (phy_off < 0) 453 return -EINVAL; 454 455 addr = (void __iomem *)fdtdec_get_addr(blob, phy_off, 456 "reg"); 457 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE) 458 return -EINVAL; 459 460 phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL); 461 val = readl(phy_ctrl); 462 463 if (val & USBPHY_CTRL_OTG_ID) 464 plat->init_type = USB_INIT_DEVICE; 465 else 466 plat->init_type = USB_INIT_HOST; 467 } else if (is_mx7()) { 468 phy_status = (void __iomem *)(addr + 469 USBNC_PHY_STATUS_OFFSET); 470 val = readl(phy_status); 471 472 if (val & USBNC_PHYSTATUS_ID_DIG) 473 plat->init_type = USB_INIT_DEVICE; 474 else 475 plat->init_type = USB_INIT_HOST; 476 } else { 477 return -EINVAL; 478 } 479 480 return 0; 481 } 482 483 static int ehci_usb_ofdata_to_platdata(struct udevice *dev) 484 { 485 struct usb_platdata *plat = dev_get_platdata(dev); 486 const char *mode; 487 488 mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL); 489 if (mode) { 490 if (strcmp(mode, "peripheral") == 0) 491 plat->init_type = USB_INIT_DEVICE; 492 else if (strcmp(mode, "host") == 0) 493 plat->init_type = USB_INIT_HOST; 494 else if (strcmp(mode, "otg") == 0) 495 return ehci_usb_phy_mode(dev); 496 else 497 return -EINVAL; 498 499 return 0; 500 } 501 502 return ehci_usb_phy_mode(dev); 503 } 504 505 static int ehci_usb_probe(struct udevice *dev) 506 { 507 struct usb_platdata *plat = dev_get_platdata(dev); 508 struct usb_ehci *ehci = (struct usb_ehci *)devfdt_get_addr(dev); 509 struct ehci_mx6_priv_data *priv = dev_get_priv(dev); 510 enum usb_init_type type = plat->init_type; 511 struct ehci_hccr *hccr; 512 struct ehci_hcor *hcor; 513 int ret; 514 515 priv->ehci = ehci; 516 priv->portnr = dev->seq; 517 priv->init_type = type; 518 519 ret = device_get_supply_regulator(dev, "vbus-supply", 520 &priv->vbus_supply); 521 if (ret) 522 debug("%s: No vbus supply\n", dev->name); 523 524 ret = ehci_mx6_common_init(ehci, priv->portnr); 525 if (ret) 526 return ret; 527 528 if (priv->vbus_supply) { 529 ret = regulator_set_enable(priv->vbus_supply, 530 (type == USB_INIT_DEVICE) ? 531 false : true); 532 if (ret) { 533 puts("Error enabling VBUS supply\n"); 534 return ret; 535 } 536 } 537 538 if (priv->init_type == USB_INIT_HOST) { 539 setbits_le32(&ehci->usbmode, CM_HOST); 540 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); 541 setbits_le32(&ehci->portsc, USB_EN); 542 } 543 544 mdelay(10); 545 546 hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 547 hcor = (struct ehci_hcor *)((uint32_t)hccr + 548 HC_LENGTH(ehci_readl(&(hccr)->cr_capbase))); 549 550 return ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type); 551 } 552 553 static const struct udevice_id mx6_usb_ids[] = { 554 { .compatible = "fsl,imx27-usb" }, 555 { } 556 }; 557 558 U_BOOT_DRIVER(usb_mx6) = { 559 .name = "ehci_mx6", 560 .id = UCLASS_USB, 561 .of_match = mx6_usb_ids, 562 .ofdata_to_platdata = ehci_usb_ofdata_to_platdata, 563 .probe = ehci_usb_probe, 564 .remove = ehci_deregister, 565 .ops = &ehci_usb_ops, 566 .platdata_auto_alloc_size = sizeof(struct usb_platdata), 567 .priv_auto_alloc_size = sizeof(struct ehci_mx6_priv_data), 568 .flags = DM_FLAG_ALLOC_PRIV_DMA, 569 }; 570 #endif 571