1 /* 2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> 3 * Copyright (C) 2010 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <usb.h> 10 #include <errno.h> 11 #include <wait_bit.h> 12 #include <linux/compiler.h> 13 #include <usb/ehci-ci.h> 14 #include <asm/io.h> 15 #include <asm/arch/imx-regs.h> 16 #include <asm/arch/clock.h> 17 #include <asm/imx-common/iomux-v3.h> 18 #include <dm.h> 19 20 #include "ehci.h" 21 22 #define USB_OTGREGS_OFFSET 0x000 23 #define USB_H1REGS_OFFSET 0x200 24 #define USB_H2REGS_OFFSET 0x400 25 #define USB_H3REGS_OFFSET 0x600 26 #define USB_OTHERREGS_OFFSET 0x800 27 28 #define USB_H1_CTRL_OFFSET 0x04 29 30 #define USBPHY_CTRL 0x00000030 31 #define USBPHY_CTRL_SET 0x00000034 32 #define USBPHY_CTRL_CLR 0x00000038 33 #define USBPHY_CTRL_TOG 0x0000003c 34 35 #define USBPHY_PWD 0x00000000 36 #define USBPHY_CTRL_SFTRST 0x80000000 37 #define USBPHY_CTRL_CLKGATE 0x40000000 38 #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000 39 #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000 40 #define USBPHY_CTRL_OTG_ID 0x08000000 41 42 #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000 43 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000 44 45 #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000 46 #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000 47 #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000 48 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040 49 50 #define USBNC_OFFSET 0x200 51 #define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */ 52 #define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */ 53 #define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */ 54 #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */ 55 #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */ 56 57 /* USBCMD */ 58 #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */ 59 #define UCMD_RESET (1 << 1) /* controller reset */ 60 61 #if defined(CONFIG_MX6) 62 static const unsigned phy_bases[] = { 63 USB_PHY0_BASE_ADDR, 64 USB_PHY1_BASE_ADDR, 65 }; 66 67 static void usb_internal_phy_clock_gate(int index, int on) 68 { 69 void __iomem *phy_reg; 70 71 if (index >= ARRAY_SIZE(phy_bases)) 72 return; 73 74 phy_reg = (void __iomem *)phy_bases[index]; 75 phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET; 76 writel(USBPHY_CTRL_CLKGATE, phy_reg); 77 } 78 79 static void usb_power_config(int index) 80 { 81 struct anatop_regs __iomem *anatop = 82 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; 83 void __iomem *chrg_detect; 84 void __iomem *pll_480_ctrl_clr; 85 void __iomem *pll_480_ctrl_set; 86 87 switch (index) { 88 case 0: 89 chrg_detect = &anatop->usb1_chrg_detect; 90 pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr; 91 pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set; 92 break; 93 case 1: 94 chrg_detect = &anatop->usb2_chrg_detect; 95 pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr; 96 pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set; 97 break; 98 default: 99 return; 100 } 101 /* 102 * Some phy and power's special controls 103 * 1. The external charger detector needs to be disabled 104 * or the signal at DP will be poor 105 * 2. The PLL's power and output to usb 106 * is totally controlled by IC, so the Software only needs 107 * to enable them at initializtion. 108 */ 109 writel(ANADIG_USB2_CHRG_DETECT_EN_B | 110 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B, 111 chrg_detect); 112 113 writel(ANADIG_USB2_PLL_480_CTRL_BYPASS, 114 pll_480_ctrl_clr); 115 116 writel(ANADIG_USB2_PLL_480_CTRL_ENABLE | 117 ANADIG_USB2_PLL_480_CTRL_POWER | 118 ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS, 119 pll_480_ctrl_set); 120 } 121 122 /* Return 0 : host node, <>0 : device mode */ 123 static int usb_phy_enable(int index, struct usb_ehci *ehci) 124 { 125 void __iomem *phy_reg; 126 void __iomem *phy_ctrl; 127 void __iomem *usb_cmd; 128 int ret; 129 130 if (index >= ARRAY_SIZE(phy_bases)) 131 return 0; 132 133 phy_reg = (void __iomem *)phy_bases[index]; 134 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); 135 usb_cmd = (void __iomem *)&ehci->usbcmd; 136 137 /* Stop then Reset */ 138 clrbits_le32(usb_cmd, UCMD_RUN_STOP); 139 ret = wait_for_bit(__func__, usb_cmd, UCMD_RUN_STOP, false, 10000, 140 false); 141 if (ret) 142 return ret; 143 144 setbits_le32(usb_cmd, UCMD_RESET); 145 ret = wait_for_bit(__func__, usb_cmd, UCMD_RESET, false, 10000, false); 146 if (ret) 147 return ret; 148 149 /* Reset USBPHY module */ 150 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); 151 udelay(10); 152 153 /* Remove CLKGATE and SFTRST */ 154 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); 155 udelay(10); 156 157 /* Power up the PHY */ 158 writel(0, phy_reg + USBPHY_PWD); 159 /* enable FS/LS device */ 160 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | 161 USBPHY_CTRL_ENUTMILEVEL3); 162 163 return 0; 164 } 165 166 int usb_phy_mode(int port) 167 { 168 void __iomem *phy_reg; 169 void __iomem *phy_ctrl; 170 u32 val; 171 172 phy_reg = (void __iomem *)phy_bases[port]; 173 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); 174 175 val = readl(phy_ctrl); 176 177 if (val & USBPHY_CTRL_OTG_ID) 178 return USB_INIT_DEVICE; 179 else 180 return USB_INIT_HOST; 181 } 182 183 /* Base address for this IP block is 0x02184800 */ 184 struct usbnc_regs { 185 u32 ctrl[4]; /* otg/host1-3 */ 186 u32 uh2_hsic_ctrl; 187 u32 uh3_hsic_ctrl; 188 u32 otg_phy_ctrl_0; 189 u32 uh1_phy_ctrl_0; 190 }; 191 #elif defined(CONFIG_MX7) 192 struct usbnc_regs { 193 u32 ctrl1; 194 u32 ctrl2; 195 u32 reserve1[10]; 196 u32 phy_cfg1; 197 u32 phy_cfg2; 198 u32 reserve2; 199 u32 phy_status; 200 u32 reserve3[4]; 201 u32 adp_cfg1; 202 u32 adp_cfg2; 203 u32 adp_status; 204 }; 205 206 static void usb_power_config(int index) 207 { 208 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + 209 (0x10000 * index) + USBNC_OFFSET); 210 void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2); 211 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1); 212 213 /* 214 * Clear the ACAENB to enable usb_otg_id detection, 215 * otherwise it is the ACA detection enabled. 216 */ 217 clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB); 218 219 /* Set power polarity to high active */ 220 #ifdef CONFIG_MXC_USB_OTG_HACTIVE 221 setbits_le32(ctrl, UCTRL_PWR_POL); 222 #else 223 clrbits_le32(ctrl, UCTRL_PWR_POL); 224 #endif 225 } 226 227 int usb_phy_mode(int port) 228 { 229 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + 230 (0x10000 * port) + USBNC_OFFSET); 231 void __iomem *status = (void __iomem *)(&usbnc->phy_status); 232 u32 val; 233 234 val = readl(status); 235 236 if (val & USBNC_PHYSTATUS_ID_DIG) 237 return USB_INIT_DEVICE; 238 else 239 return USB_INIT_HOST; 240 } 241 #endif 242 243 static void usb_oc_config(int index) 244 { 245 #if defined(CONFIG_MX6) 246 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + 247 USB_OTHERREGS_OFFSET); 248 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]); 249 #elif defined(CONFIG_MX7) 250 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + 251 (0x10000 * index) + USBNC_OFFSET); 252 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1); 253 #endif 254 255 #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2 256 /* mx6qarm2 seems to required a different setting*/ 257 clrbits_le32(ctrl, UCTRL_OVER_CUR_POL); 258 #else 259 setbits_le32(ctrl, UCTRL_OVER_CUR_POL); 260 #endif 261 262 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS); 263 } 264 265 /** 266 * board_usb_phy_mode - override usb phy mode 267 * @port: usb host/otg port 268 * 269 * Target board specific, override usb_phy_mode. 270 * When usb-otg is used as usb host port, iomux pad usb_otg_id can be 271 * left disconnected in this case usb_phy_mode will not be able to identify 272 * the phy mode that usb port is used. 273 * Machine file overrides board_usb_phy_mode. 274 * 275 * Return: USB_INIT_DEVICE or USB_INIT_HOST 276 */ 277 int __weak board_usb_phy_mode(int port) 278 { 279 return usb_phy_mode(port); 280 } 281 282 /** 283 * board_ehci_hcd_init - set usb vbus voltage 284 * @port: usb otg port 285 * 286 * Target board specific, setup iomux pad to setup supply vbus voltage 287 * for usb otg port. Machine board file overrides board_ehci_hcd_init 288 * 289 * Return: 0 Success 290 */ 291 int __weak board_ehci_hcd_init(int port) 292 { 293 return 0; 294 } 295 296 /** 297 * board_ehci_power - enables/disables usb vbus voltage 298 * @port: usb otg port 299 * @on: on/off vbus voltage 300 * 301 * Enables/disables supply vbus voltage for usb otg port. 302 * Machine board file overrides board_ehci_power 303 * 304 * Return: 0 Success 305 */ 306 int __weak board_ehci_power(int port, int on) 307 { 308 return 0; 309 } 310 311 int ehci_mx6_common_init(struct usb_ehci *ehci, int index) 312 { 313 int ret; 314 315 enable_usboh3_clk(1); 316 mdelay(1); 317 318 /* Do board specific initialization */ 319 ret = board_ehci_hcd_init(index); 320 if (ret) 321 return ret; 322 323 usb_power_config(index); 324 usb_oc_config(index); 325 326 #if defined(CONFIG_MX6) 327 usb_internal_phy_clock_gate(index, 1); 328 usb_phy_enable(index, ehci); 329 #endif 330 331 return 0; 332 } 333 334 #ifndef CONFIG_DM_USB 335 int ehci_hcd_init(int index, enum usb_init_type init, 336 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 337 { 338 enum usb_init_type type; 339 #if defined(CONFIG_MX6) 340 u32 controller_spacing = 0x200; 341 #elif defined(CONFIG_MX7) 342 u32 controller_spacing = 0x10000; 343 #endif 344 struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR + 345 (controller_spacing * index)); 346 int ret; 347 348 if (index > 3) 349 return -EINVAL; 350 351 ret = ehci_mx6_common_init(ehci, index); 352 if (ret) 353 return ret; 354 355 type = board_usb_phy_mode(index); 356 357 if (hccr && hcor) { 358 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 359 *hcor = (struct ehci_hcor *)((uint32_t)*hccr + 360 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 361 } 362 363 if ((type == init) || (type == USB_INIT_DEVICE)) 364 board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1); 365 if (type != init) 366 return -ENODEV; 367 if (type == USB_INIT_DEVICE) 368 return 0; 369 370 setbits_le32(&ehci->usbmode, CM_HOST); 371 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); 372 setbits_le32(&ehci->portsc, USB_EN); 373 374 mdelay(10); 375 376 return 0; 377 } 378 379 int ehci_hcd_stop(int index) 380 { 381 return 0; 382 } 383 #else 384 struct ehci_mx6_priv_data { 385 struct ehci_ctrl ctrl; 386 struct usb_ehci *ehci; 387 enum usb_init_type init_type; 388 int portnr; 389 }; 390 391 static int mx6_init_after_reset(struct ehci_ctrl *dev) 392 { 393 struct ehci_mx6_priv_data *priv = dev->priv; 394 enum usb_init_type type = priv->init_type; 395 struct usb_ehci *ehci = priv->ehci; 396 int ret; 397 398 ret = ehci_mx6_common_init(priv->ehci, priv->portnr); 399 if (ret) 400 return ret; 401 402 board_ehci_power(priv->portnr, (type == USB_INIT_DEVICE) ? 0 : 1); 403 404 if (type == USB_INIT_DEVICE) 405 return 0; 406 407 setbits_le32(&ehci->usbmode, CM_HOST); 408 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); 409 setbits_le32(&ehci->portsc, USB_EN); 410 411 mdelay(10); 412 413 return 0; 414 } 415 416 static const struct ehci_ops mx6_ehci_ops = { 417 .init_after_reset = mx6_init_after_reset 418 }; 419 420 static int ehci_usb_probe(struct udevice *dev) 421 { 422 struct usb_platdata *plat = dev_get_platdata(dev); 423 struct usb_ehci *ehci = (struct usb_ehci *)dev_get_addr(dev); 424 struct ehci_mx6_priv_data *priv = dev_get_priv(dev); 425 struct ehci_hccr *hccr; 426 struct ehci_hcor *hcor; 427 int ret; 428 429 priv->ehci = ehci; 430 priv->portnr = dev->seq; 431 priv->init_type = plat->init_type; 432 433 ret = ehci_mx6_common_init(ehci, priv->portnr); 434 if (ret) 435 return ret; 436 437 board_ehci_power(priv->portnr, (priv->init_type == USB_INIT_DEVICE) ? 0 : 1); 438 439 if (priv->init_type == USB_INIT_HOST) { 440 setbits_le32(&ehci->usbmode, CM_HOST); 441 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); 442 setbits_le32(&ehci->portsc, USB_EN); 443 } 444 445 mdelay(10); 446 447 hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 448 hcor = (struct ehci_hcor *)((uint32_t)hccr + 449 HC_LENGTH(ehci_readl(&(hccr)->cr_capbase))); 450 451 return ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type); 452 } 453 454 static const struct udevice_id mx6_usb_ids[] = { 455 { .compatible = "fsl,imx27-usb" }, 456 { } 457 }; 458 459 U_BOOT_DRIVER(usb_mx6) = { 460 .name = "ehci_mx6", 461 .id = UCLASS_USB, 462 .of_match = mx6_usb_ids, 463 .probe = ehci_usb_probe, 464 .remove = ehci_deregister, 465 .ops = &ehci_usb_ops, 466 .platdata_auto_alloc_size = sizeof(struct usb_platdata), 467 .priv_auto_alloc_size = sizeof(struct ehci_mx6_priv_data), 468 .flags = DM_FLAG_ALLOC_PRIV_DMA, 469 }; 470 #endif 471