1 /* 2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> 3 * Copyright (C) 2010 Freescale Semiconductor, Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * for more details. 14 */ 15 16 #include <common.h> 17 #include <usb.h> 18 #include <errno.h> 19 #include <linux/compiler.h> 20 #include <usb/ehci-fsl.h> 21 #include <asm/io.h> 22 #include <asm/arch/imx-regs.h> 23 #include <asm/arch/clock.h> 24 25 #include "ehci.h" 26 27 #define MX5_USBOTHER_REGS_OFFSET 0x800 28 29 30 #define MXC_OTG_OFFSET 0 31 #define MXC_H1_OFFSET 0x200 32 #define MXC_H2_OFFSET 0x400 33 #define MXC_H3_OFFSET 0x600 34 35 #define MXC_USBCTRL_OFFSET 0 36 #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 37 #define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc 38 #define MXC_USB_CTRL_1_OFFSET 0x10 39 #define MXC_USBH2CTRL_OFFSET 0x14 40 #define MXC_USBH3CTRL_OFFSET 0x18 41 42 /* USB_CTRL */ 43 /* OTG wakeup intr enable */ 44 #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) 45 /* OTG power mask */ 46 #define MXC_OTG_UCTRL_OPM_BIT (1 << 24) 47 /* OTG power pin polarity */ 48 #define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24) 49 /* Host1 ULPI interrupt enable */ 50 #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) 51 /* HOST1 wakeup intr enable */ 52 #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) 53 /* HOST1 power mask */ 54 #define MXC_H1_UCTRL_H1PM_BIT (1 << 8) 55 /* HOST1 power pin polarity */ 56 #define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8) 57 58 /* USB_PHY_CTRL_FUNC */ 59 /* OTG Polarity of Overcurrent */ 60 #define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) 61 /* OTG Disable Overcurrent Event */ 62 #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) 63 /* UH1 Polarity of Overcurrent */ 64 #define MXC_H1_OC_POL_BIT (1 << 6) 65 /* UH1 Disable Overcurrent Event */ 66 #define MXC_H1_OC_DIS_BIT (1 << 5) 67 /* OTG Power Pin Polarity */ 68 #define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) 69 70 /* USBH2CTRL */ 71 #define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31) 72 #define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30) 73 #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) 74 #define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) 75 #define MXC_H2_UCTRL_H2PM_BIT (1 << 4) 76 #define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4) 77 78 /* USBH3CTRL */ 79 #define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31) 80 #define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30) 81 #define MXC_H3_UCTRL_H3UIE_BIT (1 << 8) 82 #define MXC_H3_UCTRL_H3WIE_BIT (1 << 7) 83 #define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4) 84 85 /* USB_CTRL_1 */ 86 #define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) 87 88 int mxc_set_usbcontrol(int port, unsigned int flags) 89 { 90 unsigned int v; 91 void __iomem *usb_base = (void __iomem *)OTG_BASE_ADDR; 92 void __iomem *usbother_base; 93 int ret = 0; 94 95 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; 96 97 switch (port) { 98 case 0: /* OTG port */ 99 if (flags & MXC_EHCI_INTERNAL_PHY) { 100 v = __raw_readl(usbother_base + 101 MXC_USB_PHY_CTR_FUNC_OFFSET); 102 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) 103 v |= MXC_OTG_PHYCTRL_OC_POL_BIT; 104 else 105 v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT; 106 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 107 /* OC/USBPWR is used */ 108 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; 109 else 110 /* OC/USBPWR is not used */ 111 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; 112 #ifdef CONFIG_MX51 113 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 114 v |= MXC_OTG_PHYCTRL_PWR_POL_BIT; 115 else 116 v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT; 117 #endif 118 __raw_writel(v, usbother_base + 119 MXC_USB_PHY_CTR_FUNC_OFFSET); 120 121 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); 122 #ifdef CONFIG_MX51 123 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 124 v &= ~MXC_OTG_UCTRL_OPM_BIT; 125 else 126 v |= MXC_OTG_UCTRL_OPM_BIT; 127 #endif 128 #ifdef CONFIG_MX53 129 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 130 v |= MXC_OTG_UCTRL_O_PWR_POL_BIT; 131 else 132 v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT; 133 #endif 134 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); 135 } 136 break; 137 case 1: /* Host 1 ULPI */ 138 #ifdef CONFIG_MX51 139 /* The clock for the USBH1 ULPI port will come externally 140 from the PHY. */ 141 v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET); 142 __raw_writel(v | MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + 143 MXC_USB_CTRL_1_OFFSET); 144 #endif 145 146 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); 147 #ifdef CONFIG_MX51 148 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 149 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */ 150 else 151 v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */ 152 #endif 153 #ifdef CONFIG_MX53 154 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 155 v |= MXC_H1_UCTRL_H1_PWR_POL_BIT; 156 else 157 v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT; 158 #endif 159 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); 160 161 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); 162 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) 163 v |= MXC_H1_OC_POL_BIT; 164 else 165 v &= ~MXC_H1_OC_POL_BIT; 166 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 167 v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ 168 else 169 v |= MXC_H1_OC_DIS_BIT; /* OC is not used */ 170 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); 171 172 break; 173 case 2: /* Host 2 ULPI */ 174 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET); 175 #ifdef CONFIG_MX51 176 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 177 v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */ 178 else 179 v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */ 180 #endif 181 #ifdef CONFIG_MX53 182 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) 183 v |= MXC_H2_UCTRL_H2_OC_POL_BIT; 184 else 185 v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT; 186 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 187 v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */ 188 else 189 v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */ 190 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 191 v |= MXC_H2_UCTRL_H2_PWR_POL_BIT; 192 else 193 v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT; 194 #endif 195 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); 196 break; 197 #ifdef CONFIG_MX53 198 case 3: /* Host 3 ULPI */ 199 v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET); 200 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) 201 v |= MXC_H3_UCTRL_H3_OC_POL_BIT; 202 else 203 v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT; 204 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 205 v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */ 206 else 207 v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */ 208 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 209 v |= MXC_H3_UCTRL_H3_PWR_POL_BIT; 210 else 211 v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT; 212 __raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET); 213 break; 214 #endif 215 } 216 217 return ret; 218 } 219 220 int __weak board_ehci_hcd_init(int port) 221 { 222 return 0; 223 } 224 225 void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) 226 { 227 } 228 229 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) 230 { 231 struct usb_ehci *ehci; 232 #ifdef CONFIG_MX53 233 struct clkctl *sc_regs = (struct clkctl *)CCM_BASE_ADDR; 234 u32 reg; 235 236 reg = __raw_readl(&sc_regs->cscmr1) & ~(1 << 26); 237 /* derive USB PHY clock multiplexer from PLL3 */ 238 reg |= 1 << 26; 239 __raw_writel(reg, &sc_regs->cscmr1); 240 #endif 241 242 set_usboh3_clk(); 243 enable_usboh3_clk(1); 244 set_usb_phy_clk(); 245 enable_usb_phy1_clk(1); 246 enable_usb_phy2_clk(1); 247 mdelay(1); 248 249 /* Do board specific initialization */ 250 board_ehci_hcd_init(CONFIG_MXC_USB_PORT); 251 252 ehci = (struct usb_ehci *)(OTG_BASE_ADDR + 253 (0x200 * CONFIG_MXC_USB_PORT)); 254 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 255 *hcor = (struct ehci_hcor *)((uint32_t)*hccr + 256 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 257 setbits_le32(&ehci->usbmode, CM_HOST); 258 259 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); 260 setbits_le32(&ehci->portsc, USB_EN); 261 262 mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); 263 mdelay(10); 264 265 /* Do board specific post-initialization */ 266 board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT); 267 268 return 0; 269 } 270 271 int ehci_hcd_stop(int index) 272 { 273 return 0; 274 } 275