1 /* 2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> 3 * Copyright (C) 2010 Freescale Semiconductor, Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * for more details. 14 */ 15 16 #include <common.h> 17 #include <usb.h> 18 #include <errno.h> 19 #include <linux/compiler.h> 20 #include <usb/ehci-fsl.h> 21 #include <asm/io.h> 22 #include <asm/arch/imx-regs.h> 23 #include <asm/arch/clock.h> 24 #include <asm/arch/mx5x_pins.h> 25 #include <asm/arch/iomux.h> 26 27 #include "ehci.h" 28 29 #define MX5_USBOTHER_REGS_OFFSET 0x800 30 31 32 #define MXC_OTG_OFFSET 0 33 #define MXC_H1_OFFSET 0x200 34 #define MXC_H2_OFFSET 0x400 35 #define MXC_H3_OFFSET 0x600 36 37 #define MXC_USBCTRL_OFFSET 0 38 #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 39 #define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc 40 #define MXC_USB_CTRL_1_OFFSET 0x10 41 #define MXC_USBH2CTRL_OFFSET 0x14 42 #define MXC_USBH3CTRL_OFFSET 0x18 43 44 /* USB_CTRL */ 45 /* OTG wakeup intr enable */ 46 #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) 47 /* OTG power mask */ 48 #define MXC_OTG_UCTRL_OPM_BIT (1 << 24) 49 /* OTG power pin polarity */ 50 #define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24) 51 /* Host1 ULPI interrupt enable */ 52 #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) 53 /* HOST1 wakeup intr enable */ 54 #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) 55 /* HOST1 power mask */ 56 #define MXC_H1_UCTRL_H1PM_BIT (1 << 8) 57 /* HOST1 power pin polarity */ 58 #define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8) 59 60 /* USB_PHY_CTRL_FUNC */ 61 /* OTG Polarity of Overcurrent */ 62 #define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) 63 /* OTG Disable Overcurrent Event */ 64 #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) 65 /* UH1 Polarity of Overcurrent */ 66 #define MXC_H1_OC_POL_BIT (1 << 6) 67 /* UH1 Disable Overcurrent Event */ 68 #define MXC_H1_OC_DIS_BIT (1 << 5) 69 /* OTG Power Pin Polarity */ 70 #define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) 71 72 /* USBH2CTRL */ 73 #define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31) 74 #define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30) 75 #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) 76 #define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) 77 #define MXC_H2_UCTRL_H2PM_BIT (1 << 4) 78 #define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4) 79 80 /* USBH3CTRL */ 81 #define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31) 82 #define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30) 83 #define MXC_H3_UCTRL_H3UIE_BIT (1 << 8) 84 #define MXC_H3_UCTRL_H3WIE_BIT (1 << 7) 85 #define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4) 86 87 /* USB_CTRL_1 */ 88 #define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) 89 90 /* USB pin configuration */ 91 #define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \ 92 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \ 93 PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL) 94 95 #ifdef CONFIG_MX51 96 /* 97 * Configure the MX51 USB H1 IOMUX 98 */ 99 void setup_iomux_usb_h1(void) 100 { 101 mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0); 102 mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG); 103 mxc_request_iomux(MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT0); 104 mxc_iomux_set_pad(MX51_PIN_USBH1_CLK, USB_PAD_CONFIG); 105 mxc_request_iomux(MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT0); 106 mxc_iomux_set_pad(MX51_PIN_USBH1_DIR, USB_PAD_CONFIG); 107 mxc_request_iomux(MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT0); 108 mxc_iomux_set_pad(MX51_PIN_USBH1_NXT, USB_PAD_CONFIG); 109 110 mxc_request_iomux(MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_ALT0); 111 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA0, USB_PAD_CONFIG); 112 mxc_request_iomux(MX51_PIN_USBH1_DATA1, IOMUX_CONFIG_ALT0); 113 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA1, USB_PAD_CONFIG); 114 mxc_request_iomux(MX51_PIN_USBH1_DATA2, IOMUX_CONFIG_ALT0); 115 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA2, USB_PAD_CONFIG); 116 mxc_request_iomux(MX51_PIN_USBH1_DATA3, IOMUX_CONFIG_ALT0); 117 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA3, USB_PAD_CONFIG); 118 mxc_request_iomux(MX51_PIN_USBH1_DATA4, IOMUX_CONFIG_ALT0); 119 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA4, USB_PAD_CONFIG); 120 mxc_request_iomux(MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT0); 121 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA5, USB_PAD_CONFIG); 122 mxc_request_iomux(MX51_PIN_USBH1_DATA6, IOMUX_CONFIG_ALT0); 123 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA6, USB_PAD_CONFIG); 124 mxc_request_iomux(MX51_PIN_USBH1_DATA7, IOMUX_CONFIG_ALT0); 125 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA7, USB_PAD_CONFIG); 126 } 127 128 /* 129 * Configure the MX51 USB H2 IOMUX 130 */ 131 void setup_iomux_usb_h2(void) 132 { 133 mxc_request_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2); 134 mxc_iomux_set_pad(MX51_PIN_EIM_A24, USB_PAD_CONFIG); 135 mxc_request_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2); 136 mxc_iomux_set_pad(MX51_PIN_EIM_A25, USB_PAD_CONFIG); 137 mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2); 138 mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG); 139 mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT2); 140 mxc_iomux_set_pad(MX51_PIN_EIM_A27, USB_PAD_CONFIG); 141 142 mxc_request_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2); 143 mxc_iomux_set_pad(MX51_PIN_EIM_D16, USB_PAD_CONFIG); 144 mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2); 145 mxc_iomux_set_pad(MX51_PIN_EIM_D17, USB_PAD_CONFIG); 146 mxc_request_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2); 147 mxc_iomux_set_pad(MX51_PIN_EIM_D18, USB_PAD_CONFIG); 148 mxc_request_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2); 149 mxc_iomux_set_pad(MX51_PIN_EIM_D19, USB_PAD_CONFIG); 150 mxc_request_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2); 151 mxc_iomux_set_pad(MX51_PIN_EIM_D20, USB_PAD_CONFIG); 152 mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2); 153 mxc_iomux_set_pad(MX51_PIN_EIM_D21, USB_PAD_CONFIG); 154 mxc_request_iomux(MX51_PIN_EIM_D22, IOMUX_CONFIG_ALT2); 155 mxc_iomux_set_pad(MX51_PIN_EIM_D22, USB_PAD_CONFIG); 156 mxc_request_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT2); 157 mxc_iomux_set_pad(MX51_PIN_EIM_D23, USB_PAD_CONFIG); 158 } 159 #endif 160 161 int mxc_set_usbcontrol(int port, unsigned int flags) 162 { 163 unsigned int v; 164 void __iomem *usb_base = (void __iomem *)OTG_BASE_ADDR; 165 void __iomem *usbother_base; 166 int ret = 0; 167 168 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; 169 170 switch (port) { 171 case 0: /* OTG port */ 172 if (flags & MXC_EHCI_INTERNAL_PHY) { 173 v = __raw_readl(usbother_base + 174 MXC_USB_PHY_CTR_FUNC_OFFSET); 175 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) 176 v |= MXC_OTG_PHYCTRL_OC_POL_BIT; 177 else 178 v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT; 179 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 180 /* OC/USBPWR is used */ 181 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; 182 else 183 /* OC/USBPWR is not used */ 184 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; 185 #ifdef CONFIG_MX51 186 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 187 v |= MXC_OTG_PHYCTRL_PWR_POL_BIT; 188 else 189 v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT; 190 #endif 191 __raw_writel(v, usbother_base + 192 MXC_USB_PHY_CTR_FUNC_OFFSET); 193 194 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); 195 #ifdef CONFIG_MX51 196 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 197 v &= ~MXC_OTG_UCTRL_OPM_BIT; 198 else 199 v |= MXC_OTG_UCTRL_OPM_BIT; 200 #endif 201 #ifdef CONFIG_MX53 202 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 203 v |= MXC_OTG_UCTRL_O_PWR_POL_BIT; 204 else 205 v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT; 206 #endif 207 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); 208 } 209 break; 210 case 1: /* Host 1 ULPI */ 211 #ifdef CONFIG_MX51 212 /* The clock for the USBH1 ULPI port will come externally 213 from the PHY. */ 214 v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET); 215 __raw_writel(v | MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + 216 MXC_USB_CTRL_1_OFFSET); 217 #endif 218 219 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); 220 #ifdef CONFIG_MX51 221 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 222 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */ 223 else 224 v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */ 225 #endif 226 #ifdef CONFIG_MX53 227 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 228 v |= MXC_H1_UCTRL_H1_PWR_POL_BIT; 229 else 230 v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT; 231 #endif 232 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); 233 234 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); 235 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) 236 v |= MXC_H1_OC_POL_BIT; 237 else 238 v &= ~MXC_H1_OC_POL_BIT; 239 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 240 v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ 241 else 242 v |= MXC_H1_OC_DIS_BIT; /* OC is not used */ 243 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); 244 245 break; 246 case 2: /* Host 2 ULPI */ 247 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET); 248 #ifdef CONFIG_MX51 249 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 250 v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */ 251 else 252 v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */ 253 #endif 254 #ifdef CONFIG_MX53 255 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) 256 v |= MXC_H2_UCTRL_H2_OC_POL_BIT; 257 else 258 v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT; 259 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 260 v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */ 261 else 262 v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */ 263 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 264 v |= MXC_H2_UCTRL_H2_PWR_POL_BIT; 265 else 266 v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT; 267 #endif 268 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); 269 break; 270 #ifdef CONFIG_MX53 271 case 3: /* Host 3 ULPI */ 272 v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET); 273 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) 274 v |= MXC_H3_UCTRL_H3_OC_POL_BIT; 275 else 276 v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT; 277 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 278 v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */ 279 else 280 v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */ 281 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) 282 v |= MXC_H3_UCTRL_H3_PWR_POL_BIT; 283 else 284 v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT; 285 __raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET); 286 break; 287 #endif 288 } 289 290 return ret; 291 } 292 293 int __weak board_ehci_hcd_init(int port) 294 { 295 return 0; 296 } 297 298 void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) 299 { 300 } 301 302 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) 303 { 304 struct usb_ehci *ehci; 305 #ifdef CONFIG_MX53 306 struct clkctl *sc_regs = (struct clkctl *)CCM_BASE_ADDR; 307 u32 reg; 308 309 reg = __raw_readl(&sc_regs->cscmr1) & ~(1 << 26); 310 /* derive USB PHY clock multiplexer from PLL3 */ 311 reg |= 1 << 26; 312 __raw_writel(reg, &sc_regs->cscmr1); 313 #endif 314 315 set_usboh3_clk(); 316 enable_usboh3_clk(1); 317 set_usb_phy_clk(); 318 enable_usb_phy1_clk(1); 319 enable_usb_phy2_clk(1); 320 mdelay(1); 321 322 /* Do board specific initialization */ 323 board_ehci_hcd_init(CONFIG_MXC_USB_PORT); 324 325 ehci = (struct usb_ehci *)(OTG_BASE_ADDR + 326 (0x200 * CONFIG_MXC_USB_PORT)); 327 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 328 *hcor = (struct ehci_hcor *)((uint32_t)*hccr + 329 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 330 setbits_le32(&ehci->usbmode, CM_HOST); 331 332 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); 333 setbits_le32(&ehci->portsc, USB_EN); 334 335 mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); 336 mdelay(10); 337 338 /* Do board specific post-initialization */ 339 board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT); 340 341 return 0; 342 } 343 344 int ehci_hcd_stop(int index) 345 { 346 return 0; 347 } 348