1 /* 2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> 3 * Copyright (C) 2010 Freescale Semiconductor, Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * for more details. 14 */ 15 16 #include <common.h> 17 #include <usb.h> 18 #include <errno.h> 19 #include <linux/compiler.h> 20 #include <usb/ehci-fsl.h> 21 #include <asm/io.h> 22 #include <asm/arch/imx-regs.h> 23 #include <asm/arch/clock.h> 24 #include <asm/arch/mx5x_pins.h> 25 #include <asm/arch/iomux.h> 26 27 #include "ehci.h" 28 29 #define MX5_USBOTHER_REGS_OFFSET 0x800 30 31 32 #define MXC_OTG_OFFSET 0 33 #define MXC_H1_OFFSET 0x200 34 #define MXC_H2_OFFSET 0x400 35 36 #define MXC_USBCTRL_OFFSET 0 37 #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 38 #define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc 39 #define MXC_USB_CTRL_1_OFFSET 0x10 40 #define MXC_USBH2CTRL_OFFSET 0x14 41 42 /* USB_CTRL */ 43 #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */ 44 #define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */ 45 #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */ 46 #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */ 47 #define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ 48 49 /* USB_PHY_CTRL_FUNC */ 50 #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ 51 #define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ 52 53 /* USBH2CTRL */ 54 #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) 55 #define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) 56 #define MXC_H2_UCTRL_H2PM_BIT (1 << 4) 57 58 /* USB_CTRL_1 */ 59 #define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) 60 61 /* USB pin configuration */ 62 #define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \ 63 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \ 64 PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL) 65 66 #ifdef CONFIG_MX51 67 /* 68 * Configure the MX51 USB H1 IOMUX 69 */ 70 void setup_iomux_usb_h1(void) 71 { 72 mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0); 73 mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG); 74 mxc_request_iomux(MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT0); 75 mxc_iomux_set_pad(MX51_PIN_USBH1_CLK, USB_PAD_CONFIG); 76 mxc_request_iomux(MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT0); 77 mxc_iomux_set_pad(MX51_PIN_USBH1_DIR, USB_PAD_CONFIG); 78 mxc_request_iomux(MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT0); 79 mxc_iomux_set_pad(MX51_PIN_USBH1_NXT, USB_PAD_CONFIG); 80 81 mxc_request_iomux(MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_ALT0); 82 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA0, USB_PAD_CONFIG); 83 mxc_request_iomux(MX51_PIN_USBH1_DATA1, IOMUX_CONFIG_ALT0); 84 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA1, USB_PAD_CONFIG); 85 mxc_request_iomux(MX51_PIN_USBH1_DATA2, IOMUX_CONFIG_ALT0); 86 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA2, USB_PAD_CONFIG); 87 mxc_request_iomux(MX51_PIN_USBH1_DATA3, IOMUX_CONFIG_ALT0); 88 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA3, USB_PAD_CONFIG); 89 mxc_request_iomux(MX51_PIN_USBH1_DATA4, IOMUX_CONFIG_ALT0); 90 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA4, USB_PAD_CONFIG); 91 mxc_request_iomux(MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT0); 92 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA5, USB_PAD_CONFIG); 93 mxc_request_iomux(MX51_PIN_USBH1_DATA6, IOMUX_CONFIG_ALT0); 94 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA6, USB_PAD_CONFIG); 95 mxc_request_iomux(MX51_PIN_USBH1_DATA7, IOMUX_CONFIG_ALT0); 96 mxc_iomux_set_pad(MX51_PIN_USBH1_DATA7, USB_PAD_CONFIG); 97 } 98 99 /* 100 * Configure the MX51 USB H2 IOMUX 101 */ 102 void setup_iomux_usb_h2(void) 103 { 104 mxc_request_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2); 105 mxc_iomux_set_pad(MX51_PIN_EIM_A24, USB_PAD_CONFIG); 106 mxc_request_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2); 107 mxc_iomux_set_pad(MX51_PIN_EIM_A25, USB_PAD_CONFIG); 108 mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2); 109 mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG); 110 mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT2); 111 mxc_iomux_set_pad(MX51_PIN_EIM_A27, USB_PAD_CONFIG); 112 113 mxc_request_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2); 114 mxc_iomux_set_pad(MX51_PIN_EIM_D16, USB_PAD_CONFIG); 115 mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2); 116 mxc_iomux_set_pad(MX51_PIN_EIM_D17, USB_PAD_CONFIG); 117 mxc_request_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2); 118 mxc_iomux_set_pad(MX51_PIN_EIM_D18, USB_PAD_CONFIG); 119 mxc_request_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2); 120 mxc_iomux_set_pad(MX51_PIN_EIM_D19, USB_PAD_CONFIG); 121 mxc_request_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2); 122 mxc_iomux_set_pad(MX51_PIN_EIM_D20, USB_PAD_CONFIG); 123 mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2); 124 mxc_iomux_set_pad(MX51_PIN_EIM_D21, USB_PAD_CONFIG); 125 mxc_request_iomux(MX51_PIN_EIM_D22, IOMUX_CONFIG_ALT2); 126 mxc_iomux_set_pad(MX51_PIN_EIM_D22, USB_PAD_CONFIG); 127 mxc_request_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT2); 128 mxc_iomux_set_pad(MX51_PIN_EIM_D23, USB_PAD_CONFIG); 129 } 130 #endif 131 132 int mxc_set_usbcontrol(int port, unsigned int flags) 133 { 134 unsigned int v; 135 void __iomem *usb_base = (void __iomem *)OTG_BASE_ADDR; 136 void __iomem *usbother_base; 137 int ret = 0; 138 139 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; 140 141 switch (port) { 142 case 0: /* OTG port */ 143 if (flags & MXC_EHCI_INTERNAL_PHY) { 144 v = __raw_readl(usbother_base + 145 MXC_USB_PHY_CTR_FUNC_OFFSET); 146 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 147 /* OC/USBPWR is not used */ 148 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; 149 else 150 /* OC/USBPWR is used */ 151 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; 152 __raw_writel(v, usbother_base + 153 MXC_USB_PHY_CTR_FUNC_OFFSET); 154 155 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); 156 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 157 v |= MXC_OTG_UCTRL_OPM_BIT; 158 else 159 v &= ~MXC_OTG_UCTRL_OPM_BIT; 160 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); 161 } 162 break; 163 case 1: /* Host 1 Host ULPI */ 164 #ifdef CONFIG_MX51 165 /* The clock for the USBH1 ULPI port will come externally 166 from the PHY. */ 167 v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET); 168 __raw_writel(v | MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + 169 MXC_USB_CTRL_1_OFFSET); 170 #endif 171 172 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); 173 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 174 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */ 175 else 176 v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */ 177 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); 178 179 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); 180 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 181 v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ 182 else 183 v |= MXC_H1_OC_DIS_BIT; /* OC is not used */ 184 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); 185 186 break; 187 case 2: /* Host 2 ULPI */ 188 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET); 189 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 190 v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */ 191 else 192 v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */ 193 194 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); 195 break; 196 } 197 198 return ret; 199 } 200 201 void __board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) 202 { 203 } 204 205 void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) 206 __attribute((weak, alias("__board_ehci_hcd_postinit"))); 207 208 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) 209 { 210 struct usb_ehci *ehci; 211 #ifdef CONFIG_MX53 212 struct clkctl *sc_regs = (struct clkctl *)CCM_BASE_ADDR; 213 u32 reg; 214 215 reg = __raw_readl(&sc_regs->cscmr1) & ~(1 << 26); 216 /* derive USB PHY clock multiplexer from PLL3 */ 217 reg |= 1 << 26; 218 __raw_writel(reg, &sc_regs->cscmr1); 219 #endif 220 221 set_usboh3_clk(); 222 enable_usboh3_clk(1); 223 set_usb_phy_clk(); 224 enable_usb_phy1_clk(1); 225 enable_usb_phy2_clk(1); 226 mdelay(1); 227 228 /* Do board specific initialization */ 229 board_ehci_hcd_init(CONFIG_MXC_USB_PORT); 230 231 ehci = (struct usb_ehci *)(OTG_BASE_ADDR + 232 (0x200 * CONFIG_MXC_USB_PORT)); 233 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); 234 *hcor = (struct ehci_hcor *)((uint32_t)*hccr + 235 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); 236 setbits_le32(&ehci->usbmode, CM_HOST); 237 238 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); 239 setbits_le32(&ehci->portsc, USB_EN); 240 241 mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); 242 mdelay(10); 243 244 /* Do board specific post-initialization */ 245 board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT); 246 247 return 0; 248 } 249 250 int ehci_hcd_stop(int index) 251 { 252 return 0; 253 } 254